| blob | d6cb083b90a2c5675e42f253982645cf2a16a27d |
1 NVIDIA Tegra114 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7 for muxing and gating Tegra's clocks, and setting their rates.
9 Required properties :
10 - compatible : Should be "nvidia,tegra114-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
17 The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 160 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
25 The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26 above.
28 0 unassigned
29 1 unassigned
30 2 unassigned
31 3 unassigned
32 4 rtc
33 5 timer
34 6 uarta
35 7 unassigned (register bit affects uartb and vfir)
36 8 unassigned
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 unassigned
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 unassigned
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 i2s0
59 31 unassigned
61 32 unassigned
62 33 unassigned
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 unassigned
67 38 unassigned
68 39 unassigned (register bit affects fuse and fuse_burn)
69 40 kfuse
70 41 sbc1
71 42 nor
72 43 unassigned
73 44 sbc2
74 45 unassigned
75 46 sbc3
76 47 i2c5
77 48 dsia
78 49 unassigned
79 50 mipi
80 51 hdmi
81 52 csi
82 53 unassigned
83 54 i2c2
84 55 uartc
85 56 mipi-cal
86 57 emc
87 58 usb2
88 59 usb3
89 60 msenc
90 61 vde
91 62 bsea
92 63 bsev
94 64 unassigned
95 65 uartd
96 66 unassigned
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 unassigned
101 71 owr
102 72 afi
103 73 csite
104 74 unassigned
105 75 unassigned
106 76 la
107 77 trace
108 78 soc_therm
109 79 dtv
110 80 ndspeed
111 81 i2cslow
112 82 dsib
113 83 tsec
114 84 unassigned
115 85 unassigned
116 86 unassigned
117 87 unassigned
118 88 unassigned
119 89 xusb_host
120 90 unassigned
121 91 msenc
122 92 csus
123 93 unassigned
124 94 unassigned
125 95 unassigned (bit affects xusb_dev and xusb_dev_src)
127 96 unassigned
128 97 unassigned
129 98 unassigned
130 99 mselect
131 100 tsensor
132 101 i2s3
133 102 i2s4
134 103 i2c4
135 104 sbc5
136 105 sbc6
137 106 d_audio
138 107 apbif
139 108 dam0
140 109 dam1
141 110 dam2
142 111 hda2codec_2x
143 112 unassigned
144 113 audio0_2x
145 114 audio1_2x
146 115 audio2_2x
147 116 audio3_2x
148 117 audio4_2x
149 118 spdif_2x
150 119 actmon
151 120 extern1
152 121 extern2
153 122 extern3
154 123 unassigned
155 124 unassigned
156 125 hda
157 126 unassigned
158 127 se
160 128 hda2hdmi
161 129 unassigned
162 130 unassigned
163 131 unassigned
164 132 unassigned
165 133 unassigned
166 134 unassigned
167 135 unassigned
168 136 unassigned
169 137 unassigned
170 138 unassigned
171 139 unassigned
172 140 unassigned
173 141 unassigned
174 142 unassigned
175 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
176 xusb_host_src and xusb_ss_src)
177 144 cilab
178 145 cilcd
179 146 cile
180 147 dsialp
181 148 dsiblp
182 149 unassigned
183 150 dds
184 151 unassigned
185 152 dp2
186 153 amx
187 154 adx
188 155 unassigned (bit affects dfll_ref and dfll_soc)
189 156 xusb_ss
191 192 uartb
192 193 vfir
193 194 spdif_in
194 195 spdif_out
195 196 vi
196 197 vi_sensor
197 198 fuse
198 199 fuse_burn
199 200 clk_32k
200 201 clk_m
201 202 clk_m_div2
202 203 clk_m_div4
203 204 pll_ref
204 205 pll_c
205 206 pll_c_out1
206 207 pll_c2
207 208 pll_c3
208 209 pll_m
209 210 pll_m_out1
210 211 pll_p
211 212 pll_p_out1
212 213 pll_p_out2
213 214 pll_p_out3
214 215 pll_p_out4
215 216 pll_a
216 217 pll_a_out0
217 218 pll_d
218 219 pll_d_out0
219 220 pll_d2
220 221 pll_d2_out0
221 222 pll_u
222 223 pll_u_480M
223 224 pll_u_60M
224 225 pll_u_48M
225 226 pll_u_12M
226 227 pll_x
227 228 pll_x_out0
228 229 pll_re_vco
229 230 pll_re_out
230 231 pll_e_out0
231 232 spdif_in_sync
232 233 i2s0_sync
233 234 i2s1_sync
234 235 i2s2_sync
235 236 i2s3_sync
236 237 i2s4_sync
237 238 vimclk_sync
238 239 audio0
239 240 audio1
240 241 audio2
241 242 audio3
242 243 audio4
243 244 spdif
244 245 clk_out_1
245 246 clk_out_2
246 247 clk_out_3
247 248 blink
248 252 xusb_host_src
249 253 xusb_falcon_src
250 254 xusb_fs_src
251 255 xusb_ss_src
252 256 xusb_dev_src
253 257 xusb_dev
254 258 xusb_hs_src
255 259 sclk
256 260 hclk
257 261 pclk
258 262 cclk_g
259 263 cclk_lp
260 264 dfll_ref
261 265 dfll_soc
263 Example SoC include file:
265 / {
266 tegra_car: clock {
267 compatible = "nvidia,tegra114-car";
268 reg = <0x60006000 0x1000>;
269 #clock-cells = <1>;
270 };
272 usb@c5004000 {
273 clocks = <&tegra_car 58>; /* usb2 */
274 };
275 };
277 Example board file:
279 / {
280 clocks {
281 compatible = "simple-bus";
282 #address-cells = <1>;
283 #size-cells = <0>;
285 osc: clock@0 {
286 compatible = "fixed-clock";
287 reg = <0>;
288 #clock-cells = <0>;
289 clock-frequency = <12000000>;
290 };
292 clk_32k: clock@1 {
293 compatible = "fixed-clock";
294 reg = <1>;
295 #clock-cells = <0>;
296 clock-frequency = <32768>;
297 };
298 };
300 &tegra_car {
301 clocks = <&clk_32k> <&osc>;
302 };
303 };