Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

   1 NVIDIA Tegra host1x
   2
   3 Required properties:
   4 - compatible: "nvidia,tegra<chip>-host1x"
   5 - reg: Physical base address and length of the controller's registers.
   6 - interrupts: The interrupt outputs from the controller.
   7 - #address-cells: The number of cells used to represent physical base addresses
   8   in the host1x address space. Should be 1.
   9 - #size-cells: The number of cells used to represent the size of an address
  10   range in the host1x address space. Should be 1.
  11 - ranges: The mapping of the host1x address space to the CPU address space.
  12
  13 The host1x top-level node defines a number of children, each representing one
  14 of the following host1x client modules:
  15
  16 - mpe: video encoder
  17
  18   Required properties:
  19   - compatible: "nvidia,tegra<chip>-mpe"
  20   - reg: Physical base address and length of the controller's registers.
  21   - interrupts: The interrupt outputs from the controller.
  22
  23 - vi: video input
  24
  25   Required properties:
  26   - compatible: "nvidia,tegra<chip>-vi"
  27   - reg: Physical base address and length of the controller's registers.
  28   - interrupts: The interrupt outputs from the controller.
  29
  30 - epp: encoder pre-processor
  31
  32   Required properties:
  33   - compatible: "nvidia,tegra<chip>-epp"
  34   - reg: Physical base address and length of the controller's registers.
  35   - interrupts: The interrupt outputs from the controller.
  36
  37 - isp: image signal processor
  38
  39   Required properties:
  40   - compatible: "nvidia,tegra<chip>-isp"
  41   - reg: Physical base address and length of the controller's registers.
  42   - interrupts: The interrupt outputs from the controller.
  43
  44 - gr2d: 2D graphics engine
  45
  46   Required properties:
  47   - compatible: "nvidia,tegra<chip>-gr2d"
  48   - reg: Physical base address and length of the controller's registers.
  49   - interrupts: The interrupt outputs from the controller.
  50
  51 - gr3d: 3D graphics engine
  52
  53   Required properties:
  54   - compatible: "nvidia,tegra<chip>-gr3d"
  55   - reg: Physical base address and length of the controller's registers.
  56
  57 - dc: display controller
  58
  59   Required properties:
  60   - compatible: "nvidia,tegra<chip>-dc"
  61   - reg: Physical base address and length of the controller's registers.
  62   - interrupts: The interrupt outputs from the controller.
  63
  64   Each display controller node has a child node, named "rgb", that represents
  65   the RGB output associated with the controller. It can take the following
  66   optional properties:
  67   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  68   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  69   - nvidia,edid: supplies a binary EDID blob
  70
  71 - hdmi: High Definition Multimedia Interface
  72
  73   Required properties:
  74   - compatible: "nvidia,tegra<chip>-hdmi"
  75   - reg: Physical base address and length of the controller's registers.
  76   - interrupts: The interrupt outputs from the controller.
  77   - vdd-supply: regulator for supply voltage
  78   - pll-supply: regulator for PLL
  79
  80   Optional properties:
  81   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  82   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  83   - nvidia,edid: supplies a binary EDID blob
  84
  85 - tvo: TV encoder output
  86
  87   Required properties:
  88   - compatible: "nvidia,tegra<chip>-tvo"
  89   - reg: Physical base address and length of the controller's registers.
  90   - interrupts: The interrupt outputs from the controller.
  91
  92 - dsi: display serial interface
  93
  94   Required properties:
  95   - compatible: "nvidia,tegra<chip>-dsi"
  96   - reg: Physical base address and length of the controller's registers.
  97
  98 Example:
  99
 100 / {
 101         ...
 102
 103         host1x {
 104                 compatible = "nvidia,tegra20-host1x", "simple-bus";
 105                 reg = <0x50000000 0x00024000>;
 106                 interrupts = <0 65 0x04   /* mpcore syncpt */
 107                               0 67 0x04>; /* mpcore general */
 108
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111
 112                 ranges = <0x54000000 0x54000000 0x04000000>;
 113
 114                 mpe {
 115                         compatible = "nvidia,tegra20-mpe";
 116                         reg = <0x54040000 0x00040000>;
 117                         interrupts = <0 68 0x04>;
 118                 };
 119
 120                 vi {
 121                         compatible = "nvidia,tegra20-vi";
 122                         reg = <0x54080000 0x00040000>;
 123                         interrupts = <0 69 0x04>;
 124                 };
 125
 126                 epp {
 127                         compatible = "nvidia,tegra20-epp";
 128                         reg = <0x540c0000 0x00040000>;
 129                         interrupts = <0 70 0x04>;
 130                 };
 131
 132                 isp {
 133                         compatible = "nvidia,tegra20-isp";
 134                         reg = <0x54100000 0x00040000>;
 135                         interrupts = <0 71 0x04>;
 136                 };
 137
 138                 gr2d {
 139                         compatible = "nvidia,tegra20-gr2d";
 140                         reg = <0x54140000 0x00040000>;
 141                         interrupts = <0 72 0x04>;
 142                 };
 143
 144                 gr3d {
 145                         compatible = "nvidia,tegra20-gr3d";
 146                         reg = <0x54180000 0x00040000>;
 147                 };
 148
 149                 dc@54200000 {
 150                         compatible = "nvidia,tegra20-dc";
 151                         reg = <0x54200000 0x00040000>;
 152                         interrupts = <0 73 0x04>;
 153
 154                         rgb {
 155                                 status = "disabled";
 156                         };
 157                 };
 158
 159                 dc@54240000 {
 160                         compatible = "nvidia,tegra20-dc";
 161                         reg = <0x54240000 0x00040000>;
 162                         interrupts = <0 74 0x04>;
 163
 164                         rgb {
 165                                 status = "disabled";
 166                         };
 167                 };
 168
 169                 hdmi {
 170                         compatible = "nvidia,tegra20-hdmi";
 171                         reg = <0x54280000 0x00040000>;
 172                         interrupts = <0 75 0x04>;
 173                         status = "disabled";
 174                 };
 175
 176                 tvo {
 177                         compatible = "nvidia,tegra20-tvo";
 178                         reg = <0x542c0000 0x00040000>;
 179                         interrupts = <0 76 0x04>;
 180                         status = "disabled";
 181                 };
 182
 183                 dsi {
 184                         compatible = "nvidia,tegra20-dsi";
 185                         reg = <0x54300000 0x00040000>;
 186                         status = "disabled";
 187                 };
 188         };
 189
 190         ...
 191 };