1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
5 controller, or the HW block containing it, is referred to occasionally
6 as "armctrl" in the SoC documentation, hence naming of this binding.
10 - compatible : should be "brcm,bcm2835-armctrl-ic"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : Specifies the number of cells needed to encode an
14 interrupt source. The value shall be 2.
16 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
17 pending" register, or 1/2 respectively for interrupts in the "IRQ pending
20 The 2nd cell contains the interrupt number within the bank. Valid values
21 are 0..7 for bank 0, and 0..31 for bank 1.
23 The interrupt sources are as follows:
105 intc: interrupt-controller {
106 compatible = "brcm,bcm2835-armctrl-ic";
107 reg = <0x7e00b200 0x200>;
108 interrupt-controller;
109 #interrupt-cells = <2>;