1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to the NAND flash and all accesses
11 are made in native endianness.
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
13 representing partitions.
14 - gpios : specifies the gpio pins to control the NAND device. nwp is an
15 optional gpio and may be set to 0 if not present.
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
21 read registers (tR). If not present then a default of 20us is used.
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
23 location used to guard against bus reordering with regards to accesses to
24 the GPIO's and the NAND flash data bus. If present, then after changing
25 GPIO state and before and after command byte writes, this register will be
26 read to ensure that the GPIO accesses have completed.
28 The device tree may optionally contain sub-nodes describing partitions of the
29 address space. See partition.txt for more detail.
34 compatible = "gpio-control-nand";
38 gpios = <&banka 1 0 /* rdy */