Documentation/devicetree/bindings/mtd/gpmc-nand.txt

   1 Device tree bindings for GPMC connected NANDs
   2
   3 GPMC connected NAND (found on OMAP boards) are represented as child nodes of
   4 the GPMC controller with a name of "nand".
   5
   6 All timing relevant properties as well as generic gpmc child properties are
   7 explained in a separate documents - please refer to
   8 Documentation/devicetree/bindings/bus/ti-gpmc.txt
   9
  10 For NAND specific properties such as ECC modes or bus width, please refer to
  11 Documentation/devicetree/bindings/mtd/nand.txt
  12
  13
  14 Required properties:
  15
  16  - reg:         The CS line the peripheral is connected to
  17
  18 Optional properties:
  19
  20  - nand-bus-width:              Set this numeric value to 16 if the hardware
  21                                 is wired that way. If not specified, a bus
  22                                 width of 8 is assumed.
  23
  24  - ti,nand-ecc-opt:             A string setting the ECC layout to use. One of:
  25
  26                 "sw"            Software method (default)
  27                 "hw"            Hardware method
  28                 "hw-romcode"    gpmc hamming mode method & romcode layout
  29                 "bch4"          4-bit BCH ecc code
  30                 "bch8"          8-bit BCH ecc code
  31
  32  - elm_id:      Specifies elm device node. This is required to support BCH
  33                 error correction using ELM module.
  34
  35 For inline partiton table parsing (optional):
  36
  37  - #address-cells: should be set to 1
  38  - #size-cells: should be set to 1
  39
  40 Example for an AM33xx board:
  41
  42         gpmc: gpmc@50000000 {
  43                 compatible = "ti,am3352-gpmc";
  44                 ti,hwmods = "gpmc";
  45                 reg = <0x50000000 0x1000000>;
  46                 interrupts = <100>;
  47                 gpmc,num-cs = <8>;
  48                 gpmc,num-waitpins = <2>;
  49                 #address-cells = <2>;
  50                 #size-cells = <1>;
  51                 ranges = <0 0 0x08000000 0x2000>;       /* CS0: NAND */
  52                 elm_id = <&elm>;
  53
  54                 nand@0,0 {
  55                         reg = <0 0 0>; /* CS0, offset 0 */
  56                         nand-bus-width = <16>;
  57                         ti,nand-ecc-opt = "bch8";
  58
  59                         gpmc,sync-clk-ps = <0>;
  60                         gpmc,cs-on-ns = <0>;
  61                         gpmc,cs-rd-off-ns = <44>;
  62                         gpmc,cs-wr-off-ns = <44>;
  63                         gpmc,adv-on-ns = <6>;
  64                         gpmc,adv-rd-off-ns = <34>;
  65                         gpmc,adv-wr-off-ns = <44>;
  66                         gpmc,we-off-ns = <40>;
  67                         gpmc,oe-off-ns = <54>;
  68                         gpmc,access-ns = <64>;
  69                         gpmc,rd-cycle-ns = <82>;
  70                         gpmc,wr-cycle-ns = <82>;
  71                         gpmc,wr-access-ns = <40>;
  72                         gpmc,wr-data-mux-bus-ns = <0>;
  73
  74                         #address-cells = <1>;
  75                         #size-cells = <1>;
  76
  77                         /* partitions go here */
  78                 };
  79         };
  80