arch/arm/boot/dts/armada-xp-gp.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP development board
   3  * (DB-MV784MP-GP)
   4  *
   5  * Copyright (C) 2013 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 /dts-v1/;
  17 /include/ "armada-xp-mv78460.dtsi"
  18
  19 / {
  20         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
  21         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /*
  30                  * 8 GB of plug-in RAM modules by default.The amount
  31                  * of memory available can be changed by the
  32                  * bootloader according the size of the module
  33                  * actually plugged. Only 7GB are usable because
  34                  * addresses from 0xC0000000 to 0xffffffff are used by
  35                  * the internal registers of the SoC.
  36                  */
  37                 reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
  38                       <0x00000001 0x00000000 0x00000001 0x00000000>;
  39         };
  40
  41         soc {
  42                 ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
  43                           0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
  44                           0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
  45
  46                 internal-regs {
  47                         serial@12000 {
  48                                 clock-frequency = <250000000>;
  49                                 status = "okay";
  50                         };
  51                         serial@12100 {
  52                                 clock-frequency = <250000000>;
  53                                 status = "okay";
  54                         };
  55                         serial@12200 {
  56                                 clock-frequency = <250000000>;
  57                                 status = "okay";
  58                         };
  59                         serial@12300 {
  60                                 clock-frequency = <250000000>;
  61                                 status = "okay";
  62                         };
  63
  64                         sata@a0000 {
  65                                 nr-ports = <2>;
  66                                 status = "okay";
  67                         };
  68
  69                         mdio {
  70                                 phy0: ethernet-phy@0 {
  71                                         reg = <16>;
  72                                 };
  73
  74                                 phy1: ethernet-phy@1 {
  75                                         reg = <17>;
  76                                 };
  77
  78                                 phy2: ethernet-phy@2 {
  79                                         reg = <18>;
  80                                 };
  81
  82                                 phy3: ethernet-phy@3 {
  83                                         reg = <19>;
  84                                 };
  85                         };
  86
  87                         ethernet@70000 {
  88                                 status = "okay";
  89                                 phy = <&phy0>;
  90                                 phy-mode = "rgmii-id";
  91                         };
  92                         ethernet@74000 {
  93                                 status = "okay";
  94                                 phy = <&phy1>;
  95                                 phy-mode = "rgmii-id";
  96                         };
  97                         ethernet@30000 {
  98                                 status = "okay";
  99                                 phy = <&phy2>;
 100                                 phy-mode = "rgmii-id";
 101                         };
 102                         ethernet@34000 {
 103                                 status = "okay";
 104                                 phy = <&phy3>;
 105                                 phy-mode = "rgmii-id";
 106                         };
 107
 108                         spi0: spi@10600 {
 109                                 status = "okay";
 110
 111                                 spi-flash@0 {
 112                                         #address-cells = <1>;
 113                                         #size-cells = <1>;
 114                                         compatible = "n25q128a13";
 115                                         reg = <0>; /* Chip select 0 */
 116                                         spi-max-frequency = <108000000>;
 117                                 };
 118                         };
 119
 120                         devbus-bootcs@10400 {
 121                                 status = "okay";
 122                                 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
 123
 124                                 /* Device Bus parameters are required */
 125
 126                                 /* Read parameters */
 127                                 devbus,bus-width    = <8>;
 128                                 devbus,turn-off-ps  = <60000>;
 129                                 devbus,badr-skew-ps = <0>;
 130                                 devbus,acc-first-ps = <124000>;
 131                                 devbus,acc-next-ps  = <248000>;
 132                                 devbus,rd-setup-ps  = <0>;
 133                                 devbus,rd-hold-ps   = <0>;
 134
 135                                 /* Write parameters */
 136                                 devbus,sync-enable = <0>;
 137                                 devbus,wr-high-ps  = <60000>;
 138                                 devbus,wr-low-ps   = <60000>;
 139                                 devbus,ale-wr-ps   = <60000>;
 140
 141                                 /* NOR 16 MiB */
 142                                 nor@0 {
 143                                         compatible = "cfi-flash";
 144                                         reg = <0 0x1000000>;
 145                                         bank-width = <2>;
 146                                 };
 147                         };
 148
 149                         pcie-controller {
 150                                 status = "okay";
 151
 152                                 /*
 153                                  * The 3 slots are physically present as
 154                                  * standard PCIe slots on the board.
 155                                  */
 156                                 pcie@1,0 {
 157                                         /* Port 0, Lane 0 */
 158                                         status = "okay";
 159                                 };
 160                                 pcie@9,0 {
 161                                         /* Port 2, Lane 0 */
 162                                         status = "okay";
 163                                 };
 164                                 pcie@10,0 {
 165                                         /* Port 3, Lane 0 */
 166                                         status = "okay";
 167                                 };
 168                         };
 169                 };
 170         };
 171 };