| blob | 6ab56bd35de926aaab239966f87bb78b193dac2d |
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78460 SoC that are not
13 * common to all Armada XP SoCs.
14 */
16 /include/ "armada-xp.dtsi"
18 / {
19 model = "Marvell Armada XP MV78460 SoC";
20 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7";
36 reg = <0>;
37 clocks = <&cpuclk 0>;
38 };
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7";
43 reg = <1>;
44 clocks = <&cpuclk 1>;
45 };
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "marvell,sheeva-v7";
50 reg = <2>;
51 clocks = <&cpuclk 2>;
52 };
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "marvell,sheeva-v7";
57 reg = <3>;
58 clocks = <&cpuclk 3>;
59 };
60 };
62 soc {
63 internal-regs {
64 pinctrl {
65 compatible = "marvell,mv78460-pinctrl";
66 reg = <0x18000 0x38>;
68 sdio_pins: sdio-pins {
69 marvell,pins = "mpp30", "mpp31", "mpp32",
70 "mpp33", "mpp34", "mpp35";
71 marvell,function = "sd0";
72 };
73 };
75 gpio0: gpio@18100 {
76 compatible = "marvell,orion-gpio";
77 reg = <0x18100 0x40>;
78 ngpios = <32>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupts-cells = <2>;
83 interrupts = <82>, <83>, <84>, <85>;
84 };
86 gpio1: gpio@18140 {
87 compatible = "marvell,orion-gpio";
88 reg = <0x18140 0x40>;
89 ngpios = <32>;
90 gpio-controller;
91 #gpio-cells = <2>;
92 interrupt-controller;
93 #interrupts-cells = <2>;
94 interrupts = <87>, <88>, <89>, <90>;
95 };
97 gpio2: gpio@18180 {
98 compatible = "marvell,orion-gpio";
99 reg = <0x18180 0x40>;
100 ngpios = <3>;
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupts-cells = <2>;
105 interrupts = <91>;
106 };
108 ethernet@34000 {
109 compatible = "marvell,armada-370-neta";
110 reg = <0x34000 0x2500>;
111 interrupts = <14>;
112 clocks = <&gateclk 1>;
113 status = "disabled";
114 };
116 /*
117 * MV78460 has 4 PCIe units Gen2.0: Two units can be
118 * configured as x4 or quad x1 lanes. Two units are
119 * x4/x1.
120 */
121 pcie-controller {
122 compatible = "marvell,armada-xp-pcie";
123 status = "disabled";
124 device_type = "pci";
126 #address-cells = <3>;
127 #size-cells = <2>;
129 bus-range = <0x00 0xff>;
131 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
132 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
133 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
134 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
135 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
136 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
137 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
138 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
139 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
140 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
141 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
142 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
144 pcie@1,0 {
145 device_type = "pci";
146 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
147 reg = <0x0800 0 0 0 0>;
148 #address-cells = <3>;
149 #size-cells = <2>;
150 #interrupt-cells = <1>;
151 ranges;
152 interrupt-map-mask = <0 0 0 0>;
153 interrupt-map = <0 0 0 0 &mpic 58>;
154 marvell,pcie-port = <0>;
155 marvell,pcie-lane = <0>;
156 clocks = <&gateclk 5>;
157 status = "disabled";
158 };
160 pcie@2,0 {
161 device_type = "pci";
162 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
163 reg = <0x1000 0 0 0 0>;
164 #address-cells = <3>;
165 #size-cells = <2>;
166 #interrupt-cells = <1>;
167 ranges;
168 interrupt-map-mask = <0 0 0 0>;
169 interrupt-map = <0 0 0 0 &mpic 59>;
170 marvell,pcie-port = <0>;
171 marvell,pcie-lane = <1>;
172 clocks = <&gateclk 6>;
173 status = "disabled";
174 };
176 pcie@3,0 {
177 device_type = "pci";
178 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
179 reg = <0x1800 0 0 0 0>;
180 #address-cells = <3>;
181 #size-cells = <2>;
182 #interrupt-cells = <1>;
183 ranges;
184 interrupt-map-mask = <0 0 0 0>;
185 interrupt-map = <0 0 0 0 &mpic 60>;
186 marvell,pcie-port = <0>;
187 marvell,pcie-lane = <2>;
188 clocks = <&gateclk 7>;
189 status = "disabled";
190 };
192 pcie@4,0 {
193 device_type = "pci";
194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
195 reg = <0x2000 0 0 0 0>;
196 #address-cells = <3>;
197 #size-cells = <2>;
198 #interrupt-cells = <1>;
199 ranges;
200 interrupt-map-mask = <0 0 0 0>;
201 interrupt-map = <0 0 0 0 &mpic 61>;
202 marvell,pcie-port = <0>;
203 marvell,pcie-lane = <3>;
204 clocks = <&gateclk 8>;
205 status = "disabled";
206 };
208 pcie@5,0 {
209 device_type = "pci";
210 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
211 reg = <0x2800 0 0 0 0>;
212 #address-cells = <3>;
213 #size-cells = <2>;
214 #interrupt-cells = <1>;
215 ranges;
216 interrupt-map-mask = <0 0 0 0>;
217 interrupt-map = <0 0 0 0 &mpic 62>;
218 marvell,pcie-port = <1>;
219 marvell,pcie-lane = <0>;
220 clocks = <&gateclk 9>;
221 status = "disabled";
222 };
224 pcie@6,0 {
225 device_type = "pci";
226 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
227 reg = <0x3000 0 0 0 0>;
228 #address-cells = <3>;
229 #size-cells = <2>;
230 #interrupt-cells = <1>;
231 ranges;
232 interrupt-map-mask = <0 0 0 0>;
233 interrupt-map = <0 0 0 0 &mpic 63>;
234 marvell,pcie-port = <1>;
235 marvell,pcie-lane = <1>;
236 clocks = <&gateclk 10>;
237 status = "disabled";
238 };
240 pcie@7,0 {
241 device_type = "pci";
242 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
243 reg = <0x3800 0 0 0 0>;
244 #address-cells = <3>;
245 #size-cells = <2>;
246 #interrupt-cells = <1>;
247 ranges;
248 interrupt-map-mask = <0 0 0 0>;
249 interrupt-map = <0 0 0 0 &mpic 64>;
250 marvell,pcie-port = <1>;
251 marvell,pcie-lane = <2>;
252 clocks = <&gateclk 11>;
253 status = "disabled";
254 };
256 pcie@8,0 {
257 device_type = "pci";
258 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
259 reg = <0x4000 0 0 0 0>;
260 #address-cells = <3>;
261 #size-cells = <2>;
262 #interrupt-cells = <1>;
263 ranges;
264 interrupt-map-mask = <0 0 0 0>;
265 interrupt-map = <0 0 0 0 &mpic 65>;
266 marvell,pcie-port = <1>;
267 marvell,pcie-lane = <3>;
268 clocks = <&gateclk 12>;
269 status = "disabled";
270 };
271 pcie@9,0 {
272 device_type = "pci";
273 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
274 reg = <0x4800 0 0 0 0>;
275 #address-cells = <3>;
276 #size-cells = <2>;
277 #interrupt-cells = <1>;
278 ranges;
279 interrupt-map-mask = <0 0 0 0>;
280 interrupt-map = <0 0 0 0 &mpic 99>;
281 marvell,pcie-port = <2>;
282 marvell,pcie-lane = <0>;
283 clocks = <&gateclk 26>;
284 status = "disabled";
285 };
287 pcie@10,0 {
288 device_type = "pci";
289 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
290 reg = <0x5000 0 0 0 0>;
291 #address-cells = <3>;
292 #size-cells = <2>;
293 #interrupt-cells = <1>;
294 ranges;
295 interrupt-map-mask = <0 0 0 0>;
296 interrupt-map = <0 0 0 0 &mpic 103>;
297 marvell,pcie-port = <3>;
298 marvell,pcie-lane = <0>;
299 clocks = <&gateclk 27>;
300 status = "disabled";
301 };
302 };
303 };
304 };
305 };