arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6qdl.dtsi"
  12 #include "imx6dl-pinfunc.h"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                 };
  24
  25                 cpu@1 {
  26                         compatible = "arm,cortex-a9";
  27                         reg = <1>;
  28                         next-level-cache = <&L2>;
  29                 };
  30         };
  31
  32         soc {
  33                 aips1: aips-bus@02000000 {
  34                         iomuxc: iomuxc@020e0000 {
  35                                 compatible = "fsl,imx6dl-iomuxc";
  36                                 reg = <0x020e0000 0x4000>;
  37
  38                                 enet {
  39                                         pinctrl_enet_1: enetgrp-1 {
  40                                                 fsl,pins = <
  41                                                         MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
  42                                                         MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
  43                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  44                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  45                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  46                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  47                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  48                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  49                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
  50                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
  51                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
  52                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
  53                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
  54                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
  55                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  56                                                         MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
  57                                                 >;
  58                                         };
  59
  60                                         pinctrl_enet_2: enetgrp-2 {
  61                                                 fsl,pins = <
  62                                                         MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
  63                                                         MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
  64                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  65                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  66                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  67                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  68                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  69                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  70                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
  71                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
  72                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
  73                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
  74                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
  75                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
  76                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  77                                                 >;
  78                                         };
  79                                 };
  80
  81                                 uart1 {
  82                                         pinctrl_uart1_1: uart1grp-1 {
  83                                                 fsl,pins = <
  84                                                         MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  85                                                         MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  86                                                 >;
  87                                         };
  88                                 };
  89
  90                                 uart4 {
  91                                         pinctrl_uart4_1: uart4grp-1 {
  92                                                 fsl,pins = <
  93                                                         MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  94                                                         MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  95                                                 >;
  96                                         };
  97                                 };
  98
  99                                 usbotg {
 100                                         pinctrl_usbotg_2: usbotggrp-2 {
 101                                                 fsl,pins = <
 102                                                         MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 103                                                 >;
 104                                         };
 105                                 };
 106
 107                                 usdhc2 {
 108                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 109                                                 fsl,pins = <
 110                                                         MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
 111                                                         MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
 112                                                         MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 113                                                         MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 114                                                         MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 115                                                         MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 116                                                         MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
 117                                                         MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
 118                                                         MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
 119                                                         MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
 120                                                 >;
 121                                         };
 122                                 };
 123
 124                                 usdhc3 {
 125                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 126                                                 fsl,pins = <
 127                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 128                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 129                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 130                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 131                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 132                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 133                                                         MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 134                                                         MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 135                                                         MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 136                                                         MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 137                                                 >;
 138                                         };
 139
 140                                         pinctrl_usdhc3_2: usdhc3grp_2 {
 141                                                 fsl,pins = <
 142                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 143                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 144                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 145                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 146                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 147                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 148                                                 >;
 149                                         };
 150                                 };
 151
 152
 153                         };
 154
 155                         pxp: pxp@020f0000 {
 156                                 reg = <0x020f0000 0x4000>;
 157                                 interrupts = <0 98 0x04>;
 158                         };
 159
 160                         epdc: epdc@020f4000 {
 161                                 reg = <0x020f4000 0x4000>;
 162                                 interrupts = <0 97 0x04>;
 163                         };
 164
 165                         lcdif: lcdif@020f8000 {
 166                                 reg = <0x020f8000 0x4000>;
 167                                 interrupts = <0 39 0x04>;
 168                         };
 169                 };
 170
 171                 aips2: aips-bus@02100000 {
 172                         i2c4: i2c@021f8000 {
 173                                 #address-cells = <1>;
 174                                 #size-cells = <0>;
 175                                 compatible = "fsl,imx1-i2c";
 176                                 reg = <0x021f8000 0x4000>;
 177                                 interrupts = <0 35 0x04>;
 178                                 status = "disabled";
 179                         };
 180                 };
 181         };
 182 };