| blob | 9e8296e4c3434afdf61004e62e2af83c9bbc8490 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
15 / {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 };
31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
68 dma_apbh: dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
73 #dma-cells = <1>;
74 dma-channels = <4>;
75 clocks = <&clks 106>;
76 };
78 gpmi: gpmi-nand@00112000 {
79 compatible = "fsl,imx6q-gpmi-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
90 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx";
92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled";
94 };
96 timer@00a00600 {
97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
100 clocks = <&clks 15>;
101 };
103 L2: l2-cache@00a02000 {
104 compatible = "arm,pl310-cache";
105 reg = <0x00a02000 0x1000>;
106 interrupts = <0 92 0x04>;
107 cache-unified;
108 cache-level = <2>;
109 };
111 pmu {
112 compatible = "arm,cortex-a9-pmu";
113 interrupts = <0 94 0x04>;
114 };
116 aips-bus@02000000 { /* AIPS1 */
117 compatible = "fsl,aips-bus", "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 reg = <0x02000000 0x100000>;
121 ranges;
123 spba-bus@02000000 {
124 compatible = "fsl,spba-bus", "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x02000000 0x40000>;
128 ranges;
130 spdif: spdif@02004000 {
131 reg = <0x02004000 0x4000>;
132 interrupts = <0 52 0x04>;
133 };
135 ecspi1: ecspi@02008000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
139 reg = <0x02008000 0x4000>;
140 interrupts = <0 31 0x04>;
141 clocks = <&clks 112>, <&clks 112>;
142 clock-names = "ipg", "per";
143 status = "disabled";
144 };
146 ecspi2: ecspi@0200c000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
150 reg = <0x0200c000 0x4000>;
151 interrupts = <0 32 0x04>;
152 clocks = <&clks 113>, <&clks 113>;
153 clock-names = "ipg", "per";
154 status = "disabled";
155 };
157 ecspi3: ecspi@02010000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
161 reg = <0x02010000 0x4000>;
162 interrupts = <0 33 0x04>;
163 clocks = <&clks 114>, <&clks 114>;
164 clock-names = "ipg", "per";
165 status = "disabled";
166 };
168 ecspi4: ecspi@02014000 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
172 reg = <0x02014000 0x4000>;
173 interrupts = <0 34 0x04>;
174 clocks = <&clks 115>, <&clks 115>;
175 clock-names = "ipg", "per";
176 status = "disabled";
177 };
179 uart1: serial@02020000 {
180 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
181 reg = <0x02020000 0x4000>;
182 interrupts = <0 26 0x04>;
183 clocks = <&clks 160>, <&clks 161>;
184 clock-names = "ipg", "per";
185 status = "disabled";
186 };
188 esai: esai@02024000 {
189 reg = <0x02024000 0x4000>;
190 interrupts = <0 51 0x04>;
191 };
193 ssi1: ssi@02028000 {
194 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
195 reg = <0x02028000 0x4000>;
196 interrupts = <0 46 0x04>;
197 clocks = <&clks 178>;
198 fsl,fifo-depth = <15>;
199 fsl,ssi-dma-events = <38 37>;
200 status = "disabled";
201 };
203 ssi2: ssi@0202c000 {
204 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
205 reg = <0x0202c000 0x4000>;
206 interrupts = <0 47 0x04>;
207 clocks = <&clks 179>;
208 fsl,fifo-depth = <15>;
209 fsl,ssi-dma-events = <42 41>;
210 status = "disabled";
211 };
213 ssi3: ssi@02030000 {
214 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
215 reg = <0x02030000 0x4000>;
216 interrupts = <0 48 0x04>;
217 clocks = <&clks 180>;
218 fsl,fifo-depth = <15>;
219 fsl,ssi-dma-events = <46 45>;
220 status = "disabled";
221 };
223 asrc: asrc@02034000 {
224 reg = <0x02034000 0x4000>;
225 interrupts = <0 50 0x04>;
226 };
228 spba@0203c000 {
229 reg = <0x0203c000 0x4000>;
230 };
231 };
233 vpu: vpu@02040000 {
234 reg = <0x02040000 0x3c000>;
235 interrupts = <0 3 0x04 0 12 0x04>;
236 };
238 aipstz@0207c000 { /* AIPSTZ1 */
239 reg = <0x0207c000 0x4000>;
240 };
242 pwm1: pwm@02080000 {
243 #pwm-cells = <2>;
244 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
245 reg = <0x02080000 0x4000>;
246 interrupts = <0 83 0x04>;
247 clocks = <&clks 62>, <&clks 145>;
248 clock-names = "ipg", "per";
249 };
251 pwm2: pwm@02084000 {
252 #pwm-cells = <2>;
253 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
254 reg = <0x02084000 0x4000>;
255 interrupts = <0 84 0x04>;
256 clocks = <&clks 62>, <&clks 146>;
257 clock-names = "ipg", "per";
258 };
260 pwm3: pwm@02088000 {
261 #pwm-cells = <2>;
262 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
263 reg = <0x02088000 0x4000>;
264 interrupts = <0 85 0x04>;
265 clocks = <&clks 62>, <&clks 147>;
266 clock-names = "ipg", "per";
267 };
269 pwm4: pwm@0208c000 {
270 #pwm-cells = <2>;
271 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
272 reg = <0x0208c000 0x4000>;
273 interrupts = <0 86 0x04>;
274 clocks = <&clks 62>, <&clks 148>;
275 clock-names = "ipg", "per";
276 };
278 can1: flexcan@02090000 {
279 reg = <0x02090000 0x4000>;
280 interrupts = <0 110 0x04>;
281 };
283 can2: flexcan@02094000 {
284 reg = <0x02094000 0x4000>;
285 interrupts = <0 111 0x04>;
286 };
288 gpt: gpt@02098000 {
289 compatible = "fsl,imx6q-gpt";
290 reg = <0x02098000 0x4000>;
291 interrupts = <0 55 0x04>;
292 clocks = <&clks 119>, <&clks 120>;
293 clock-names = "ipg", "per";
294 };
296 gpio1: gpio@0209c000 {
297 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
298 reg = <0x0209c000 0x4000>;
299 interrupts = <0 66 0x04 0 67 0x04>;
300 gpio-controller;
301 #gpio-cells = <2>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 };
306 gpio2: gpio@020a0000 {
307 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
308 reg = <0x020a0000 0x4000>;
309 interrupts = <0 68 0x04 0 69 0x04>;
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
316 gpio3: gpio@020a4000 {
317 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
318 reg = <0x020a4000 0x4000>;
319 interrupts = <0 70 0x04 0 71 0x04>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 };
326 gpio4: gpio@020a8000 {
327 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
328 reg = <0x020a8000 0x4000>;
329 interrupts = <0 72 0x04 0 73 0x04>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 };
336 gpio5: gpio@020ac000 {
337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
338 reg = <0x020ac000 0x4000>;
339 interrupts = <0 74 0x04 0 75 0x04>;
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 };
346 gpio6: gpio@020b0000 {
347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
348 reg = <0x020b0000 0x4000>;
349 interrupts = <0 76 0x04 0 77 0x04>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 };
356 gpio7: gpio@020b4000 {
357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
358 reg = <0x020b4000 0x4000>;
359 interrupts = <0 78 0x04 0 79 0x04>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
366 kpp: kpp@020b8000 {
367 reg = <0x020b8000 0x4000>;
368 interrupts = <0 82 0x04>;
369 };
371 wdog1: wdog@020bc000 {
372 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
373 reg = <0x020bc000 0x4000>;
374 interrupts = <0 80 0x04>;
375 clocks = <&clks 0>;
376 };
378 wdog2: wdog@020c0000 {
379 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
380 reg = <0x020c0000 0x4000>;
381 interrupts = <0 81 0x04>;
382 clocks = <&clks 0>;
383 status = "disabled";
384 };
386 clks: ccm@020c4000 {
387 compatible = "fsl,imx6q-ccm";
388 reg = <0x020c4000 0x4000>;
389 interrupts = <0 87 0x04 0 88 0x04>;
390 #clock-cells = <1>;
391 };
393 anatop: anatop@020c8000 {
394 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
395 reg = <0x020c8000 0x1000>;
396 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
398 regulator-1p1@110 {
399 compatible = "fsl,anatop-regulator";
400 regulator-name = "vdd1p1";
401 regulator-min-microvolt = <800000>;
402 regulator-max-microvolt = <1375000>;
403 regulator-always-on;
404 anatop-reg-offset = <0x110>;
405 anatop-vol-bit-shift = <8>;
406 anatop-vol-bit-width = <5>;
407 anatop-min-bit-val = <4>;
408 anatop-min-voltage = <800000>;
409 anatop-max-voltage = <1375000>;
410 };
412 regulator-3p0@120 {
413 compatible = "fsl,anatop-regulator";
414 regulator-name = "vdd3p0";
415 regulator-min-microvolt = <2800000>;
416 regulator-max-microvolt = <3150000>;
417 regulator-always-on;
418 anatop-reg-offset = <0x120>;
419 anatop-vol-bit-shift = <8>;
420 anatop-vol-bit-width = <5>;
421 anatop-min-bit-val = <0>;
422 anatop-min-voltage = <2625000>;
423 anatop-max-voltage = <3400000>;
424 };
426 regulator-2p5@130 {
427 compatible = "fsl,anatop-regulator";
428 regulator-name = "vdd2p5";
429 regulator-min-microvolt = <2000000>;
430 regulator-max-microvolt = <2750000>;
431 regulator-always-on;
432 anatop-reg-offset = <0x130>;
433 anatop-vol-bit-shift = <8>;
434 anatop-vol-bit-width = <5>;
435 anatop-min-bit-val = <0>;
436 anatop-min-voltage = <2000000>;
437 anatop-max-voltage = <2750000>;
438 };
440 reg_arm: regulator-vddcore@140 {
441 compatible = "fsl,anatop-regulator";
442 regulator-name = "cpu";
443 regulator-min-microvolt = <725000>;
444 regulator-max-microvolt = <1450000>;
445 regulator-always-on;
446 anatop-reg-offset = <0x140>;
447 anatop-vol-bit-shift = <0>;
448 anatop-vol-bit-width = <5>;
449 anatop-delay-reg-offset = <0x170>;
450 anatop-delay-bit-shift = <24>;
451 anatop-delay-bit-width = <2>;
452 anatop-min-bit-val = <1>;
453 anatop-min-voltage = <725000>;
454 anatop-max-voltage = <1450000>;
455 };
457 reg_pu: regulator-vddpu@140 {
458 compatible = "fsl,anatop-regulator";
459 regulator-name = "vddpu";
460 regulator-min-microvolt = <725000>;
461 regulator-max-microvolt = <1450000>;
462 regulator-always-on;
463 anatop-reg-offset = <0x140>;
464 anatop-vol-bit-shift = <9>;
465 anatop-vol-bit-width = <5>;
466 anatop-delay-reg-offset = <0x170>;
467 anatop-delay-bit-shift = <26>;
468 anatop-delay-bit-width = <2>;
469 anatop-min-bit-val = <1>;
470 anatop-min-voltage = <725000>;
471 anatop-max-voltage = <1450000>;
472 };
474 reg_soc: regulator-vddsoc@140 {
475 compatible = "fsl,anatop-regulator";
476 regulator-name = "vddsoc";
477 regulator-min-microvolt = <725000>;
478 regulator-max-microvolt = <1450000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x140>;
481 anatop-vol-bit-shift = <18>;
482 anatop-vol-bit-width = <5>;
483 anatop-delay-reg-offset = <0x170>;
484 anatop-delay-bit-shift = <28>;
485 anatop-delay-bit-width = <2>;
486 anatop-min-bit-val = <1>;
487 anatop-min-voltage = <725000>;
488 anatop-max-voltage = <1450000>;
489 };
490 };
492 usbphy1: usbphy@020c9000 {
493 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
494 reg = <0x020c9000 0x1000>;
495 interrupts = <0 44 0x04>;
496 clocks = <&clks 182>;
497 };
499 usbphy2: usbphy@020ca000 {
500 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
501 reg = <0x020ca000 0x1000>;
502 interrupts = <0 45 0x04>;
503 clocks = <&clks 183>;
504 };
506 snvs@020cc000 {
507 compatible = "fsl,sec-v4.0-mon", "simple-bus";
508 #address-cells = <1>;
509 #size-cells = <1>;
510 ranges = <0 0x020cc000 0x4000>;
512 snvs-rtc-lp@34 {
513 compatible = "fsl,sec-v4.0-mon-rtc-lp";
514 reg = <0x34 0x58>;
515 interrupts = <0 19 0x04 0 20 0x04>;
516 };
517 };
519 epit1: epit@020d0000 { /* EPIT1 */
520 reg = <0x020d0000 0x4000>;
521 interrupts = <0 56 0x04>;
522 };
524 epit2: epit@020d4000 { /* EPIT2 */
525 reg = <0x020d4000 0x4000>;
526 interrupts = <0 57 0x04>;
527 };
529 src: src@020d8000 {
530 compatible = "fsl,imx6q-src", "fsl,imx51-src";
531 reg = <0x020d8000 0x4000>;
532 interrupts = <0 91 0x04 0 96 0x04>;
533 #reset-cells = <1>;
534 };
536 gpc: gpc@020dc000 {
537 compatible = "fsl,imx6q-gpc";
538 reg = <0x020dc000 0x4000>;
539 interrupts = <0 89 0x04 0 90 0x04>;
540 };
542 gpr: iomuxc-gpr@020e0000 {
543 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
544 reg = <0x020e0000 0x38>;
545 };
547 ldb: ldb@020e0008 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
551 gpr = <&gpr>;
552 status = "disabled";
554 lvds-channel@0 {
555 reg = <0>;
556 crtcs = <&ipu1 0>;
557 status = "disabled";
558 };
560 lvds-channel@1 {
561 reg = <1>;
562 crtcs = <&ipu1 1>;
563 status = "disabled";
564 };
565 };
567 dcic1: dcic@020e4000 {
568 reg = <0x020e4000 0x4000>;
569 interrupts = <0 124 0x04>;
570 };
572 dcic2: dcic@020e8000 {
573 reg = <0x020e8000 0x4000>;
574 interrupts = <0 125 0x04>;
575 };
577 sdma: sdma@020ec000 {
578 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
579 reg = <0x020ec000 0x4000>;
580 interrupts = <0 2 0x04>;
581 clocks = <&clks 155>, <&clks 155>;
582 clock-names = "ipg", "ahb";
583 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
584 };
585 };
587 aips-bus@02100000 { /* AIPS2 */
588 compatible = "fsl,aips-bus", "simple-bus";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 reg = <0x02100000 0x100000>;
592 ranges;
594 caam@02100000 {
595 reg = <0x02100000 0x40000>;
596 interrupts = <0 105 0x04 0 106 0x04>;
597 };
599 aipstz@0217c000 { /* AIPSTZ2 */
600 reg = <0x0217c000 0x4000>;
601 };
603 usbotg: usb@02184000 {
604 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
605 reg = <0x02184000 0x200>;
606 interrupts = <0 43 0x04>;
607 clocks = <&clks 162>;
608 fsl,usbphy = <&usbphy1>;
609 fsl,usbmisc = <&usbmisc 0>;
610 status = "disabled";
611 };
613 usbh1: usb@02184200 {
614 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
615 reg = <0x02184200 0x200>;
616 interrupts = <0 40 0x04>;
617 clocks = <&clks 162>;
618 fsl,usbphy = <&usbphy2>;
619 fsl,usbmisc = <&usbmisc 1>;
620 status = "disabled";
621 };
623 usbh2: usb@02184400 {
624 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
625 reg = <0x02184400 0x200>;
626 interrupts = <0 41 0x04>;
627 clocks = <&clks 162>;
628 fsl,usbmisc = <&usbmisc 2>;
629 status = "disabled";
630 };
632 usbh3: usb@02184600 {
633 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
634 reg = <0x02184600 0x200>;
635 interrupts = <0 42 0x04>;
636 clocks = <&clks 162>;
637 fsl,usbmisc = <&usbmisc 3>;
638 status = "disabled";
639 };
641 usbmisc: usbmisc: usbmisc@02184800 {
642 #index-cells = <1>;
643 compatible = "fsl,imx6q-usbmisc";
644 reg = <0x02184800 0x200>;
645 clocks = <&clks 162>;
646 };
648 fec: ethernet@02188000 {
649 compatible = "fsl,imx6q-fec";
650 reg = <0x02188000 0x4000>;
651 interrupts = <0 118 0x04 0 119 0x04>;
652 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
653 clock-names = "ipg", "ahb", "ptp";
654 status = "disabled";
655 };
657 mlb@0218c000 {
658 reg = <0x0218c000 0x4000>;
659 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
660 };
662 usdhc1: usdhc@02190000 {
663 compatible = "fsl,imx6q-usdhc";
664 reg = <0x02190000 0x4000>;
665 interrupts = <0 22 0x04>;
666 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
667 clock-names = "ipg", "ahb", "per";
668 bus-width = <4>;
669 status = "disabled";
670 };
672 usdhc2: usdhc@02194000 {
673 compatible = "fsl,imx6q-usdhc";
674 reg = <0x02194000 0x4000>;
675 interrupts = <0 23 0x04>;
676 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
677 clock-names = "ipg", "ahb", "per";
678 bus-width = <4>;
679 status = "disabled";
680 };
682 usdhc3: usdhc@02198000 {
683 compatible = "fsl,imx6q-usdhc";
684 reg = <0x02198000 0x4000>;
685 interrupts = <0 24 0x04>;
686 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
687 clock-names = "ipg", "ahb", "per";
688 bus-width = <4>;
689 status = "disabled";
690 };
692 usdhc4: usdhc@0219c000 {
693 compatible = "fsl,imx6q-usdhc";
694 reg = <0x0219c000 0x4000>;
695 interrupts = <0 25 0x04>;
696 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
697 clock-names = "ipg", "ahb", "per";
698 bus-width = <4>;
699 status = "disabled";
700 };
702 i2c1: i2c@021a0000 {
703 #address-cells = <1>;
704 #size-cells = <0>;
705 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
706 reg = <0x021a0000 0x4000>;
707 interrupts = <0 36 0x04>;
708 clocks = <&clks 125>;
709 status = "disabled";
710 };
712 i2c2: i2c@021a4000 {
713 #address-cells = <1>;
714 #size-cells = <0>;
715 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
716 reg = <0x021a4000 0x4000>;
717 interrupts = <0 37 0x04>;
718 clocks = <&clks 126>;
719 status = "disabled";
720 };
722 i2c3: i2c@021a8000 {
723 #address-cells = <1>;
724 #size-cells = <0>;
725 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
726 reg = <0x021a8000 0x4000>;
727 interrupts = <0 38 0x04>;
728 clocks = <&clks 127>;
729 status = "disabled";
730 };
732 romcp@021ac000 {
733 reg = <0x021ac000 0x4000>;
734 };
736 mmdc0: mmdc@021b0000 { /* MMDC0 */
737 compatible = "fsl,imx6q-mmdc";
738 reg = <0x021b0000 0x4000>;
739 };
741 mmdc1: mmdc@021b4000 { /* MMDC1 */
742 reg = <0x021b4000 0x4000>;
743 };
745 weim@021b8000 {
746 reg = <0x021b8000 0x4000>;
747 interrupts = <0 14 0x04>;
748 };
750 ocotp@021bc000 {
751 compatible = "fsl,imx6q-ocotp";
752 reg = <0x021bc000 0x4000>;
753 };
755 ocotp@021c0000 {
756 reg = <0x021c0000 0x4000>;
757 interrupts = <0 21 0x04>;
758 };
760 tzasc@021d0000 { /* TZASC1 */
761 reg = <0x021d0000 0x4000>;
762 interrupts = <0 108 0x04>;
763 };
765 tzasc@021d4000 { /* TZASC2 */
766 reg = <0x021d4000 0x4000>;
767 interrupts = <0 109 0x04>;
768 };
770 audmux: audmux@021d8000 {
771 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
772 reg = <0x021d8000 0x4000>;
773 status = "disabled";
774 };
776 mipi@021dc000 { /* MIPI-CSI */
777 reg = <0x021dc000 0x4000>;
778 };
780 mipi@021e0000 { /* MIPI-DSI */
781 reg = <0x021e0000 0x4000>;
782 };
784 vdoa@021e4000 {
785 reg = <0x021e4000 0x4000>;
786 interrupts = <0 18 0x04>;
787 };
789 uart2: serial@021e8000 {
790 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
791 reg = <0x021e8000 0x4000>;
792 interrupts = <0 27 0x04>;
793 clocks = <&clks 160>, <&clks 161>;
794 clock-names = "ipg", "per";
795 status = "disabled";
796 };
798 uart3: serial@021ec000 {
799 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
800 reg = <0x021ec000 0x4000>;
801 interrupts = <0 28 0x04>;
802 clocks = <&clks 160>, <&clks 161>;
803 clock-names = "ipg", "per";
804 status = "disabled";
805 };
807 uart4: serial@021f0000 {
808 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
809 reg = <0x021f0000 0x4000>;
810 interrupts = <0 29 0x04>;
811 clocks = <&clks 160>, <&clks 161>;
812 clock-names = "ipg", "per";
813 status = "disabled";
814 };
816 uart5: serial@021f4000 {
817 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
818 reg = <0x021f4000 0x4000>;
819 interrupts = <0 30 0x04>;
820 clocks = <&clks 160>, <&clks 161>;
821 clock-names = "ipg", "per";
822 status = "disabled";
823 };
824 };
826 ipu1: ipu@02400000 {
827 #crtc-cells = <1>;
828 compatible = "fsl,imx6q-ipu";
829 reg = <0x02400000 0x400000>;
830 interrupts = <0 6 0x4 0 5 0x4>;
831 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
832 clock-names = "bus", "di0", "di1";
833 resets = <&src 2>;
834 };
835 };
836 };