arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a8";
  22                 };
  23         };
  24
  25         memory {
  26                 reg = <0x40000000 0x20000000>;
  27         };
  28
  29         clocks {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 ranges;
  33
  34                 /*
  35                  * This is a dummy clock, to be used as placeholder on
  36                  * other mux clocks when a specific parent clock is not
  37                  * yet implemented. It should be dropped when the driver
  38                  * is complete.
  39                  */
  40                 dummy: dummy {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <0>;
  44                 };
  45
  46                 osc24M: osc24M@01c20050 {
  47                         #clock-cells = <0>;
  48                         compatible = "allwinner,sun4i-osc-clk";
  49                         reg = <0x01c20050 0x4>;
  50                         clock-frequency = <24000000>;
  51                 };
  52
  53                 osc32k: osc32k {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <32768>;
  57                 };
  58
  59                 pll1: pll1@01c20000 {
  60                         #clock-cells = <0>;
  61                         compatible = "allwinner,sun4i-pll1-clk";
  62                         reg = <0x01c20000 0x4>;
  63                         clocks = <&osc24M>;
  64                 };
  65
  66                 /* dummy is 200M */
  67                 cpu: cpu@01c20054 {
  68                         #clock-cells = <0>;
  69                         compatible = "allwinner,sun4i-cpu-clk";
  70                         reg = <0x01c20054 0x4>;
  71                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  72                 };
  73
  74                 axi: axi@01c20054 {
  75                         #clock-cells = <0>;
  76                         compatible = "allwinner,sun4i-axi-clk";
  77                         reg = <0x01c20054 0x4>;
  78                         clocks = <&cpu>;
  79                 };
  80
  81                 axi_gates: axi_gates@01c2005c {
  82                         #clock-cells = <1>;
  83                         compatible = "allwinner,sun4i-axi-gates-clk";
  84                         reg = <0x01c2005c 0x4>;
  85                         clocks = <&axi>;
  86                         clock-output-names = "axi_dram";
  87                 };
  88
  89                 ahb: ahb@01c20054 {
  90                         #clock-cells = <0>;
  91                         compatible = "allwinner,sun4i-ahb-clk";
  92                         reg = <0x01c20054 0x4>;
  93                         clocks = <&axi>;
  94                 };
  95
  96                 ahb_gates: ahb_gates@01c20060 {
  97                         #clock-cells = <1>;
  98                         compatible = "allwinner,sun4i-ahb-gates-clk";
  99                         reg = <0x01c20060 0x8>;
 100                         clocks = <&ahb>;
 101                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 102                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 103                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 104                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 105                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 106                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 107                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 108                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 109                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 110                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 111                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 112                 };
 113
 114                 apb0: apb0@01c20054 {
 115                         #clock-cells = <0>;
 116                         compatible = "allwinner,sun4i-apb0-clk";
 117                         reg = <0x01c20054 0x4>;
 118                         clocks = <&ahb>;
 119                 };
 120
 121                 apb0_gates: apb0_gates@01c20068 {
 122                         #clock-cells = <1>;
 123                         compatible = "allwinner,sun4i-apb0-gates-clk";
 124                         reg = <0x01c20068 0x4>;
 125                         clocks = <&apb0>;
 126                         clock-output-names = "apb0_codec", "apb0_spdif",
 127                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 128                                 "apb0_ir1", "apb0_keypad";
 129                 };
 130
 131                 /* dummy is pll62 */
 132                 apb1_mux: apb1_mux@01c20058 {
 133                         #clock-cells = <0>;
 134                         compatible = "allwinner,sun4i-apb1-mux-clk";
 135                         reg = <0x01c20058 0x4>;
 136                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 137                 };
 138
 139                 apb1: apb1@01c20058 {
 140                         #clock-cells = <0>;
 141                         compatible = "allwinner,sun4i-apb1-clk";
 142                         reg = <0x01c20058 0x4>;
 143                         clocks = <&apb1_mux>;
 144                 };
 145
 146                 apb1_gates: apb1_gates@01c2006c {
 147                         #clock-cells = <1>;
 148                         compatible = "allwinner,sun4i-apb1-gates-clk";
 149                         reg = <0x01c2006c 0x4>;
 150                         clocks = <&apb1>;
 151                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 152                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 153                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 154                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 155                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 156                                 "apb1_uart7";
 157                 };
 158         };
 159
 160         soc@01c20000 {
 161                 compatible = "simple-bus";
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 reg = <0x01c20000 0x300000>;
 165                 ranges;
 166
 167                 intc: interrupt-controller@01c20400 {
 168                         compatible = "allwinner,sun4i-ic";
 169                         reg = <0x01c20400 0x400>;
 170                         interrupt-controller;
 171                         #interrupt-cells = <1>;
 172                 };
 173
 174                 pio: pinctrl@01c20800 {
 175                         compatible = "allwinner,sun5i-a13-pinctrl";
 176                         reg = <0x01c20800 0x400>;
 177                         clocks = <&apb0_gates 5>;
 178                         gpio-controller;
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         #gpio-cells = <3>;
 182
 183                         uart1_pins_a: uart1@0 {
 184                                 allwinner,pins = "PE10", "PE11";
 185                                 allwinner,function = "uart1";
 186                                 allwinner,drive = <0>;
 187                                 allwinner,pull = <0>;
 188                         };
 189
 190                         uart1_pins_b: uart1@1 {
 191                                 allwinner,pins = "PG3", "PG4";
 192                                 allwinner,function = "uart1";
 193                                 allwinner,drive = <0>;
 194                                 allwinner,pull = <0>;
 195                         };
 196                 };
 197
 198                 timer@01c20c00 {
 199                         compatible = "allwinner,sun4i-timer";
 200                         reg = <0x01c20c00 0x90>;
 201                         interrupts = <22>;
 202                         clocks = <&osc24M>;
 203                 };
 204
 205                 wdt: watchdog@01c20c90 {
 206                         compatible = "allwinner,sun4i-wdt";
 207                         reg = <0x01c20c90 0x10>;
 208                 };
 209
 210                 uart1: serial@01c28400 {
 211                         compatible = "snps,dw-apb-uart";
 212                         reg = <0x01c28400 0x400>;
 213                         interrupts = <2>;
 214                         reg-shift = <2>;
 215                         reg-io-width = <4>;
 216                         clocks = <&apb1_gates 17>;
 217                         status = "disabled";
 218                 };
 219
 220                 uart3: serial@01c28c00 {
 221                         compatible = "snps,dw-apb-uart";
 222                         reg = <0x01c28c00 0x400>;
 223                         interrupts = <4>;
 224                         reg-shift = <2>;
 225                         reg-io-width = <4>;
 226                         clocks = <&apb1_gates 19>;
 227                         status = "disabled";
 228                 };
 229         };
 230 };