arch/arm/boot/dts/tegra114.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra114";
   5         interrupt-parent = <&gic>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12         };
  13
  14         gic: interrupt-controller {
  15                 compatible = "arm,cortex-a15-gic";
  16                 #interrupt-cells = <3>;
  17                 interrupt-controller;
  18                 reg = <0x50041000 0x1000>,
  19                       <0x50042000 0x1000>,
  20                       <0x50044000 0x2000>,
  21                       <0x50046000 0x2000>;
  22                 interrupts = <1 9 0xf04>;
  23         };
  24
  25         timer@60005000 {
  26                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
  27                 reg = <0x60005000 0x400>;
  28                 interrupts = <0 0 0x04
  29                               0 1 0x04
  30                               0 41 0x04
  31                               0 42 0x04
  32                               0 121 0x04
  33                               0 122 0x04>;
  34                 clocks = <&tegra_car 5>;
  35         };
  36
  37         tegra_car: clock {
  38                 compatible = "nvidia,tegra114-car";
  39                 reg = <0x60006000 0x1000>;
  40                 #clock-cells = <1>;
  41         };
  42
  43         apbdma: dma {
  44                 compatible = "nvidia,tegra114-apbdma";
  45                 reg = <0x6000a000 0x1400>;
  46                 interrupts = <0 104 0x04
  47                               0 105 0x04
  48                               0 106 0x04
  49                               0 107 0x04
  50                               0 108 0x04
  51                               0 109 0x04
  52                               0 110 0x04
  53                               0 111 0x04
  54                               0 112 0x04
  55                               0 113 0x04
  56                               0 114 0x04
  57                               0 115 0x04
  58                               0 116 0x04
  59                               0 117 0x04
  60                               0 118 0x04
  61                               0 119 0x04
  62                               0 128 0x04
  63                               0 129 0x04
  64                               0 130 0x04
  65                               0 131 0x04
  66                               0 132 0x04
  67                               0 133 0x04
  68                               0 134 0x04
  69                               0 135 0x04
  70                               0 136 0x04
  71                               0 137 0x04
  72                               0 138 0x04
  73                               0 139 0x04
  74                               0 140 0x04
  75                               0 141 0x04
  76                               0 142 0x04
  77                               0 143 0x04>;
  78                 clocks = <&tegra_car 34>;
  79         };
  80
  81         ahb: ahb {
  82                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
  83                 reg = <0x6000c004 0x14c>;
  84         };
  85
  86         gpio: gpio {
  87                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
  88                 reg = <0x6000d000 0x1000>;
  89                 interrupts = <0 32 0x04
  90                               0 33 0x04
  91                               0 34 0x04
  92                               0 35 0x04
  93                               0 55 0x04
  94                               0 87 0x04
  95                               0 89 0x04
  96                               0 125 0x04>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         pinmux: pinmux {
 104                 compatible = "nvidia,tegra114-pinmux";
 105                 reg = <0x70000868 0x148         /* Pad control registers */
 106                        0x70003000 0x40c>;       /* Mux registers */
 107         };
 108
 109         /*
 110          * There are two serial driver i.e. 8250 based simple serial
 111          * driver and APB DMA based serial driver for higher baudrate
 112          * and performace. To enable the 8250 based driver, the compatible
 113          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 114          * the APB DMA based serial driver, the comptible is
 115          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 116          */
 117         uarta: serial@70006000 {
 118                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 119                 reg = <0x70006000 0x40>;
 120                 reg-shift = <2>;
 121                 interrupts = <0 36 0x04>;
 122                 nvidia,dma-request-selector = <&apbdma 8>;
 123                 status = "disabled";
 124                 clocks = <&tegra_car 6>;
 125         };
 126
 127         uartb: serial@70006040 {
 128                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 129                 reg = <0x70006040 0x40>;
 130                 reg-shift = <2>;
 131                 interrupts = <0 37 0x04>;
 132                 nvidia,dma-request-selector = <&apbdma 9>;
 133                 status = "disabled";
 134                 clocks = <&tegra_car 192>;
 135         };
 136
 137         uartc: serial@70006200 {
 138                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 139                 reg = <0x70006200 0x100>;
 140                 reg-shift = <2>;
 141                 interrupts = <0 46 0x04>;
 142                 nvidia,dma-request-selector = <&apbdma 10>;
 143                 status = "disabled";
 144                 clocks = <&tegra_car 55>;
 145         };
 146
 147         uartd: serial@70006300 {
 148                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 149                 reg = <0x70006300 0x100>;
 150                 reg-shift = <2>;
 151                 interrupts = <0 90 0x04>;
 152                 nvidia,dma-request-selector = <&apbdma 19>;
 153                 status = "disabled";
 154                 clocks = <&tegra_car 65>;
 155         };
 156
 157         pwm: pwm {
 158                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 159                 reg = <0x7000a000 0x100>;
 160                 #pwm-cells = <2>;
 161                 clocks = <&tegra_car 17>;
 162                 status = "disabled";
 163         };
 164
 165         i2c@7000c000 {
 166                 compatible = "nvidia,tegra114-i2c";
 167                 reg = <0x7000c000 0x100>;
 168                 interrupts = <0 38 0x04>;
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 clocks = <&tegra_car 12>;
 172                 clock-names = "div-clk";
 173                 status = "disabled";
 174         };
 175
 176         i2c@7000c400 {
 177                 compatible = "nvidia,tegra114-i2c";
 178                 reg = <0x7000c400 0x100>;
 179                 interrupts = <0 84 0x04>;
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 clocks = <&tegra_car 54>;
 183                 clock-names = "div-clk";
 184                 status = "disabled";
 185         };
 186
 187         i2c@7000c500 {
 188                 compatible = "nvidia,tegra114-i2c";
 189                 reg = <0x7000c500 0x100>;
 190                 interrupts = <0 92 0x04>;
 191                 #address-cells = <1>;
 192                 #size-cells = <0>;
 193                 clocks = <&tegra_car 67>;
 194                 clock-names = "div-clk";
 195                 status = "disabled";
 196         };
 197
 198         i2c@7000c700 {
 199                 compatible = "nvidia,tegra114-i2c";
 200                 reg = <0x7000c700 0x100>;
 201                 interrupts = <0 120 0x04>;
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 clocks = <&tegra_car 103>;
 205                 clock-names = "div-clk";
 206                 status = "disabled";
 207         };
 208
 209         i2c@7000d000 {
 210                 compatible = "nvidia,tegra114-i2c";
 211                 reg = <0x7000d000 0x100>;
 212                 interrupts = <0 53 0x04>;
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 clocks = <&tegra_car 47>;
 216                 clock-names = "div-clk";
 217                 status = "disabled";
 218         };
 219
 220         spi@7000d400 {
 221                 compatible = "nvidia,tegra114-spi";
 222                 reg = <0x7000d400 0x200>;
 223                 interrupts = <0 59 0x04>;
 224                 nvidia,dma-request-selector = <&apbdma 15>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 clocks = <&tegra_car 41>;
 228                 clock-names = "spi";
 229                 status = "disabled";
 230         };
 231
 232         spi@7000d600 {
 233                 compatible = "nvidia,tegra114-spi";
 234                 reg = <0x7000d600 0x200>;
 235                 interrupts = <0 82 0x04>;
 236                 nvidia,dma-request-selector = <&apbdma 16>;
 237                 #address-cells = <1>;
 238                 #size-cells = <0>;
 239                 clocks = <&tegra_car 44>;
 240                 clock-names = "spi";
 241                 status = "disabled";
 242         };
 243
 244         spi@7000d800 {
 245                 compatible = "nvidia,tegra114-spi";
 246                 reg = <0x7000d800 0x200>;
 247                 interrupts = <0 83 0x04>;
 248                 nvidia,dma-request-selector = <&apbdma 17>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 clocks = <&tegra_car 46>;
 252                 clock-names = "spi";
 253                 status = "disabled";
 254         };
 255
 256         spi@7000da00 {
 257                 compatible = "nvidia,tegra114-spi";
 258                 reg = <0x7000da00 0x200>;
 259                 interrupts = <0 93 0x04>;
 260                 nvidia,dma-request-selector = <&apbdma 18>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 clocks = <&tegra_car 68>;
 264                 clock-names = "spi";
 265                 status = "disabled";
 266         };
 267
 268         spi@7000dc00 {
 269                 compatible = "nvidia,tegra114-spi";
 270                 reg = <0x7000dc00 0x200>;
 271                 interrupts = <0 94 0x04>;
 272                 nvidia,dma-request-selector = <&apbdma 27>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 clocks = <&tegra_car 104>;
 276                 clock-names = "spi";
 277                 status = "disabled";
 278         };
 279
 280         spi@7000de00 {
 281                 compatible = "nvidia,tegra114-spi";
 282                 reg = <0x7000de00 0x200>;
 283                 interrupts = <0 79 0x04>;
 284                 nvidia,dma-request-selector = <&apbdma 28>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 clocks = <&tegra_car 105>;
 288                 clock-names = "spi";
 289                 status = "disabled";
 290         };
 291
 292         rtc {
 293                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 294                 reg = <0x7000e000 0x100>;
 295                 interrupts = <0 2 0x04>;
 296                 clocks = <&tegra_car 4>;
 297         };
 298
 299         kbc {
 300                 compatible = "nvidia,tegra114-kbc";
 301                 reg = <0x7000e200 0x100>;
 302                 interrupts = <0 85 0x04>;
 303                 clocks = <&tegra_car 36>;
 304                 status = "disabled";
 305         };
 306
 307         pmc {
 308                 compatible = "nvidia,tegra114-pmc";
 309                 reg = <0x7000e400 0x400>;
 310                 clocks = <&tegra_car 261>, <&clk32k_in>;
 311                 clock-names = "pclk", "clk32k_in";
 312         };
 313
 314         iommu {
 315                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 316                 reg = <0x7000f010 0x02c
 317                        0x7000f1f0 0x010
 318                        0x7000f228 0x074>;
 319                 nvidia,#asids = <4>;
 320                 dma-window = <0 0x40000000>;
 321                 nvidia,swgroups = <0x18659fe>;
 322                 nvidia,ahb = <&ahb>;
 323         };
 324
 325         sdhci@78000000 {
 326                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 327                 reg = <0x78000000 0x200>;
 328                 interrupts = <0 14 0x04>;
 329                 clocks = <&tegra_car 14>;
 330                 status = "disable";
 331         };
 332
 333         sdhci@78000200 {
 334                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 335                 reg = <0x78000200 0x200>;
 336                 interrupts = <0 15 0x04>;
 337                 clocks = <&tegra_car 9>;
 338                 status = "disable";
 339         };
 340
 341         sdhci@78000400 {
 342                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 343                 reg = <0x78000400 0x200>;
 344                 interrupts = <0 19 0x04>;
 345                 clocks = <&tegra_car 69>;
 346                 status = "disable";
 347         };
 348
 349         sdhci@78000600 {
 350                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 351                 reg = <0x78000600 0x200>;
 352                 interrupts = <0 31 0x04>;
 353                 clocks = <&tegra_car 15>;
 354                 status = "disable";
 355         };
 356
 357         cpus {
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360
 361                 cpu@0 {
 362                         device_type = "cpu";
 363                         compatible = "arm,cortex-a15";
 364                         reg = <0>;
 365                 };
 366
 367                 cpu@1 {
 368                         device_type = "cpu";
 369                         compatible = "arm,cortex-a15";
 370                         reg = <1>;
 371                 };
 372
 373                 cpu@2 {
 374                         device_type = "cpu";
 375                         compatible = "arm,cortex-a15";
 376                         reg = <2>;
 377                 };
 378
 379                 cpu@3 {
 380                         device_type = "cpu";
 381                         compatible = "arm,cortex-a15";
 382                         reg = <3>;
 383                 };
 384         };
 385
 386         timer {
 387                 compatible = "arm,armv7-timer";
 388                 interrupts = <1 13 0xf08>,
 389                              <1 14 0xf08>,
 390                              <1 11 0xf08>,
 391                              <1 10 0xf08>;
 392         };
 393 };