arch/arm/kvm/coproc.c

   1 /*
   2  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   3  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   4  *          Christoffer Dall <c.dall@virtualopensystems.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19 #include <linux/mm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/uaccess.h>
  22 #include <asm/kvm_arm.h>
  23 #include <asm/kvm_host.h>
  24 #include <asm/kvm_emulate.h>
  25 #include <asm/kvm_coproc.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/cputype.h>
  28 #include <trace/events/kvm.h>
  29 #include <asm/vfp.h>
  30 #include "../vfp/vfpinstr.h"
  31
  32 #include "trace.h"
  33 #include "coproc.h"
  34
  35
  36 /******************************************************************************
  37  * Co-processor emulation
  38  *****************************************************************************/
  39
  40 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  41 static u32 cache_levels;
  42
  43 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  44 #define CSSELR_MAX 12
  45
  46 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
  47 {
  48         kvm_inject_undefined(vcpu);
  49         return 1;
  50 }
  51
  52 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  53 {
  54         /*
  55          * We can get here, if the host has been built without VFPv3 support,
  56          * but the guest attempted a floating point operation.
  57          */
  58         kvm_inject_undefined(vcpu);
  59         return 1;
  60 }
  61
  62 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
  63 {
  64         kvm_inject_undefined(vcpu);
  65         return 1;
  66 }
  67
  68 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  69 {
  70         kvm_inject_undefined(vcpu);
  71         return 1;
  72 }
  73
  74 /* See note at ARM ARM B1.14.4 */
  75 static bool access_dcsw(struct kvm_vcpu *vcpu,
  76                         const struct coproc_params *p,
  77                         const struct coproc_reg *r)
  78 {
  79         unsigned long val;
  80         int cpu;
  81
  82         if (!p->is_write)
  83                 return read_from_write_only(vcpu, p);
  84
  85         cpu = get_cpu();
  86
  87         cpumask_setall(&vcpu->arch.require_dcache_flush);
  88         cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
  89
  90         /* If we were already preempted, take the long way around */
  91         if (cpu != vcpu->arch.last_pcpu) {
  92                 flush_cache_all();
  93                 goto done;
  94         }
  95
  96         val = *vcpu_reg(vcpu, p->Rt1);
  97
  98         switch (p->CRm) {
  99         case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
 100         case 14:                /* DCCISW */
 101                 asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
 102                 break;
 103
 104         case 10:                /* DCCSW */
 105                 asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
 106                 break;
 107         }
 108
 109 done:
 110         put_cpu();
 111
 112         return true;
 113 }
 114
 115 /*
 116  * We could trap ID_DFR0 and tell the guest we don't support performance
 117  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 118  * NAKed, so it will read the PMCR anyway.
 119  *
 120  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 121  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 122  * all PM registers, which doesn't crash the guest kernel at least.
 123  */
 124 static bool pm_fake(struct kvm_vcpu *vcpu,
 125                     const struct coproc_params *p,
 126                     const struct coproc_reg *r)
 127 {
 128         if (p->is_write)
 129                 return ignore_write(vcpu, p);
 130         else
 131                 return read_zero(vcpu, p);
 132 }
 133
 134 #define access_pmcr pm_fake
 135 #define access_pmcntenset pm_fake
 136 #define access_pmcntenclr pm_fake
 137 #define access_pmovsr pm_fake
 138 #define access_pmselr pm_fake
 139 #define access_pmceid0 pm_fake
 140 #define access_pmceid1 pm_fake
 141 #define access_pmccntr pm_fake
 142 #define access_pmxevtyper pm_fake
 143 #define access_pmxevcntr pm_fake
 144 #define access_pmuserenr pm_fake
 145 #define access_pmintenset pm_fake
 146 #define access_pmintenclr pm_fake
 147
 148 /* Architected CP15 registers.
 149  * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
 150  */
 151 static const struct coproc_reg cp15_regs[] = {
 152         /* CSSELR: swapped by interrupt.S. */
 153         { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
 154                         NULL, reset_unknown, c0_CSSELR },
 155
 156         /* TTBR0/TTBR1: swapped by interrupt.S. */
 157         { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
 158         { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
 159
 160         /* TTBCR: swapped by interrupt.S. */
 161         { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
 162                         NULL, reset_val, c2_TTBCR, 0x00000000 },
 163
 164         /* DACR: swapped by interrupt.S. */
 165         { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
 166                         NULL, reset_unknown, c3_DACR },
 167
 168         /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
 169         { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
 170                         NULL, reset_unknown, c5_DFSR },
 171         { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
 172                         NULL, reset_unknown, c5_IFSR },
 173         { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
 174                         NULL, reset_unknown, c5_ADFSR },
 175         { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
 176                         NULL, reset_unknown, c5_AIFSR },
 177
 178         /* DFAR/IFAR: swapped by interrupt.S. */
 179         { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
 180                         NULL, reset_unknown, c6_DFAR },
 181         { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
 182                         NULL, reset_unknown, c6_IFAR },
 183         /*
 184          * DC{C,I,CI}SW operations:
 185          */
 186         { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
 187         { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
 188         { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
 189         /*
 190          * Dummy performance monitor implementation.
 191          */
 192         { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
 193         { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
 194         { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
 195         { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
 196         { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
 197         { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
 198         { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
 199         { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
 200         { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
 201         { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
 202         { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
 203         { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
 204         { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
 205
 206         /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
 207         { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
 208                         NULL, reset_unknown, c10_PRRR},
 209         { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
 210                         NULL, reset_unknown, c10_NMRR},
 211
 212         /* VBAR: swapped by interrupt.S. */
 213         { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
 214                         NULL, reset_val, c12_VBAR, 0x00000000 },
 215
 216         /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
 217         { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
 218                         NULL, reset_val, c13_CID, 0x00000000 },
 219         { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
 220                         NULL, reset_unknown, c13_TID_URW },
 221         { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
 222                         NULL, reset_unknown, c13_TID_URO },
 223         { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
 224                         NULL, reset_unknown, c13_TID_PRIV },
 225
 226         /* CNTKCTL: swapped by interrupt.S. */
 227         { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
 228                         NULL, reset_val, c14_CNTKCTL, 0x00000000 },
 229 };
 230
 231 /* Target specific emulation tables */
 232 static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 233
 234 void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
 235 {
 236         target_tables[table->target] = table;
 237 }
 238
 239 /* Get specific register table for this target. */
 240 static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
 241 {
 242         struct kvm_coproc_target_table *table;
 243
 244         table = target_tables[target];
 245         *num = table->num;
 246         return table->table;
 247 }
 248
 249 static const struct coproc_reg *find_reg(const struct coproc_params *params,
 250                                          const struct coproc_reg table[],
 251                                          unsigned int num)
 252 {
 253         unsigned int i;
 254
 255         for (i = 0; i < num; i++) {
 256                 const struct coproc_reg *r = &table[i];
 257
 258                 if (params->is_64bit != r->is_64)
 259                         continue;
 260                 if (params->CRn != r->CRn)
 261                         continue;
 262                 if (params->CRm != r->CRm)
 263                         continue;
 264                 if (params->Op1 != r->Op1)
 265                         continue;
 266                 if (params->Op2 != r->Op2)
 267                         continue;
 268
 269                 return r;
 270         }
 271         return NULL;
 272 }
 273
 274 static int emulate_cp15(struct kvm_vcpu *vcpu,
 275                         const struct coproc_params *params)
 276 {
 277         size_t num;
 278         const struct coproc_reg *table, *r;
 279
 280         trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
 281                                    params->CRm, params->Op2, params->is_write);
 282
 283         table = get_target_table(vcpu->arch.target, &num);
 284
 285         /* Search target-specific then generic table. */
 286         r = find_reg(params, table, num);
 287         if (!r)
 288                 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
 289
 290         if (likely(r)) {
 291                 /* If we don't have an accessor, we should never get here! */
 292                 BUG_ON(!r->access);
 293
 294                 if (likely(r->access(vcpu, params, r))) {
 295                         /* Skip instruction, since it was emulated */
 296                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 297                         return 1;
 298                 }
 299                 /* If access function fails, it should complain. */
 300         } else {
 301                 kvm_err("Unsupported guest CP15 access at: %08lx\n",
 302                         *vcpu_pc(vcpu));
 303                 print_cp_instr(params);
 304         }
 305         kvm_inject_undefined(vcpu);
 306         return 1;
 307 }
 308
 309 /**
 310  * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 311  * @vcpu: The VCPU pointer
 312  * @run:  The kvm_run struct
 313  */
 314 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 315 {
 316         struct coproc_params params;
 317
 318         params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
 319         params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
 320         params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
 321         params.is_64bit = true;
 322
 323         params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
 324         params.Op2 = 0;
 325         params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
 326         params.CRn = 0;
 327
 328         return emulate_cp15(vcpu, &params);
 329 }
 330
 331 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
 332                               const struct coproc_reg *table, size_t num)
 333 {
 334         unsigned long i;
 335
 336         for (i = 0; i < num; i++)
 337                 if (table[i].reset)
 338                         table[i].reset(vcpu, &table[i]);
 339 }
 340
 341 /**
 342  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 343  * @vcpu: The VCPU pointer
 344  * @run:  The kvm_run struct
 345  */
 346 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 347 {
 348         struct coproc_params params;
 349
 350         params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
 351         params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
 352         params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
 353         params.is_64bit = false;
 354
 355         params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
 356         params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
 357         params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
 358         params.Rt2 = 0;
 359
 360         return emulate_cp15(vcpu, &params);
 361 }
 362
 363 /******************************************************************************
 364  * Userspace API
 365  *****************************************************************************/
 366
 367 static bool index_to_params(u64 id, struct coproc_params *params)
 368 {
 369         switch (id & KVM_REG_SIZE_MASK) {
 370         case KVM_REG_SIZE_U32:
 371                 /* Any unused index bits means it's not valid. */
 372                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
 373                            | KVM_REG_ARM_COPROC_MASK
 374                            | KVM_REG_ARM_32_CRN_MASK
 375                            | KVM_REG_ARM_CRM_MASK
 376                            | KVM_REG_ARM_OPC1_MASK
 377                            | KVM_REG_ARM_32_OPC2_MASK))
 378                         return false;
 379
 380                 params->is_64bit = false;
 381                 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
 382                                >> KVM_REG_ARM_32_CRN_SHIFT);
 383                 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
 384                                >> KVM_REG_ARM_CRM_SHIFT);
 385                 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
 386                                >> KVM_REG_ARM_OPC1_SHIFT);
 387                 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
 388                                >> KVM_REG_ARM_32_OPC2_SHIFT);
 389                 return true;
 390         case KVM_REG_SIZE_U64:
 391                 /* Any unused index bits means it's not valid. */
 392                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
 393                               | KVM_REG_ARM_COPROC_MASK
 394                               | KVM_REG_ARM_CRM_MASK
 395                               | KVM_REG_ARM_OPC1_MASK))
 396                         return false;
 397                 params->is_64bit = true;
 398                 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
 399                                >> KVM_REG_ARM_CRM_SHIFT);
 400                 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
 401                                >> KVM_REG_ARM_OPC1_SHIFT);
 402                 params->Op2 = 0;
 403                 params->CRn = 0;
 404                 return true;
 405         default:
 406                 return false;
 407         }
 408 }
 409
 410 /* Decode an index value, and find the cp15 coproc_reg entry. */
 411 static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
 412                                                     u64 id)
 413 {
 414         size_t num;
 415         const struct coproc_reg *table, *r;
 416         struct coproc_params params;
 417
 418         /* We only do cp15 for now. */
 419         if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
 420                 return NULL;
 421
 422         if (!index_to_params(id, &params))
 423                 return NULL;
 424
 425         table = get_target_table(vcpu->arch.target, &num);
 426         r = find_reg(&params, table, num);
 427         if (!r)
 428                 r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
 429
 430         /* Not saved in the cp15 array? */
 431         if (r && !r->reg)
 432                 r = NULL;
 433
 434         return r;
 435 }
 436
 437 /*
 438  * These are the invariant cp15 registers: we let the guest see the host
 439  * versions of these, so they're part of the guest state.
 440  *
 441  * A future CPU may provide a mechanism to present different values to
 442  * the guest, or a future kvm may trap them.
 443  */
 444 /* Unfortunately, there's no register-argument for mrc, so generate. */
 445 #define FUNCTION_FOR32(crn, crm, op1, op2, name)                        \
 446         static void get_##name(struct kvm_vcpu *v,                      \
 447                                const struct coproc_reg *r)              \
 448         {                                                               \
 449                 u32 val;                                                \
 450                                                                         \
 451                 asm volatile("mrc p15, " __stringify(op1)               \
 452                              ", %0, c" __stringify(crn)                 \
 453                              ", c" __stringify(crm)                     \
 454                              ", " __stringify(op2) "\n" : "=r" (val));  \
 455                 ((struct coproc_reg *)r)->val = val;                    \
 456         }
 457
 458 FUNCTION_FOR32(0, 0, 0, 0, MIDR)
 459 FUNCTION_FOR32(0, 0, 0, 1, CTR)
 460 FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
 461 FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
 462 FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
 463 FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
 464 FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
 465 FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
 466 FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
 467 FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
 468 FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
 469 FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
 470 FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
 471 FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
 472 FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
 473 FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
 474 FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
 475 FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
 476 FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
 477 FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
 478 FUNCTION_FOR32(0, 0, 1, 7, AIDR)
 479
 480 /* ->val is filled in by kvm_invariant_coproc_table_init() */
 481 static struct coproc_reg invariant_cp15[] = {
 482         { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
 483         { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
 484         { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
 485         { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
 486         { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
 487
 488         { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
 489         { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
 490         { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
 491         { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
 492         { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
 493         { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
 494         { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
 495         { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
 496
 497         { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
 498         { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
 499         { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
 500         { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
 501         { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
 502         { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
 503
 504         { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
 505         { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
 506 };
 507
 508 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
 509 {
 510         /* This Just Works because we are little endian. */
 511         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
 512                 return -EFAULT;
 513         return 0;
 514 }
 515
 516 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
 517 {
 518         /* This Just Works because we are little endian. */
 519         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
 520                 return -EFAULT;
 521         return 0;
 522 }
 523
 524 static int get_invariant_cp15(u64 id, void __user *uaddr)
 525 {
 526         struct coproc_params params;
 527         const struct coproc_reg *r;
 528
 529         if (!index_to_params(id, &params))
 530                 return -ENOENT;
 531
 532         r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
 533         if (!r)
 534                 return -ENOENT;
 535
 536         return reg_to_user(uaddr, &r->val, id);
 537 }
 538
 539 static int set_invariant_cp15(u64 id, void __user *uaddr)
 540 {
 541         struct coproc_params params;
 542         const struct coproc_reg *r;
 543         int err;
 544         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
 545
 546         if (!index_to_params(id, &params))
 547                 return -ENOENT;
 548         r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
 549         if (!r)
 550                 return -ENOENT;
 551
 552         err = reg_from_user(&val, uaddr, id);
 553         if (err)
 554                 return err;
 555
 556         /* This is what we mean by invariant: you can't change it. */
 557         if (r->val != val)
 558                 return -EINVAL;
 559
 560         return 0;
 561 }
 562
 563 static bool is_valid_cache(u32 val)
 564 {
 565         u32 level, ctype;
 566
 567         if (val >= CSSELR_MAX)
 568                 return -ENOENT;
 569
 570         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
 571         level = (val >> 1);
 572         ctype = (cache_levels >> (level * 3)) & 7;
 573
 574         switch (ctype) {
 575         case 0: /* No cache */
 576                 return false;
 577         case 1: /* Instruction cache only */
 578                 return (val & 1);
 579         case 2: /* Data cache only */
 580         case 4: /* Unified cache */
 581                 return !(val & 1);
 582         case 3: /* Separate instruction and data caches */
 583                 return true;
 584         default: /* Reserved: we can't know instruction or data. */
 585                 return false;
 586         }
 587 }
 588
 589 /* Which cache CCSIDR represents depends on CSSELR value. */
 590 static u32 get_ccsidr(u32 csselr)
 591 {
 592         u32 ccsidr;
 593
 594         /* Make sure noone else changes CSSELR during this! */
 595         local_irq_disable();
 596         /* Put value into CSSELR */
 597         asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
 598         isb();
 599         /* Read result out of CCSIDR */
 600         asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
 601         local_irq_enable();
 602
 603         return ccsidr;
 604 }
 605
 606 static int demux_c15_get(u64 id, void __user *uaddr)
 607 {
 608         u32 val;
 609         u32 __user *uval = uaddr;
 610
 611         /* Fail if we have unknown bits set. */
 612         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 613                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 614                 return -ENOENT;
 615
 616         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 617         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 618                 if (KVM_REG_SIZE(id) != 4)
 619                         return -ENOENT;
 620                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
 621                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
 622                 if (!is_valid_cache(val))
 623                         return -ENOENT;
 624
 625                 return put_user(get_ccsidr(val), uval);
 626         default:
 627                 return -ENOENT;
 628         }
 629 }
 630
 631 static int demux_c15_set(u64 id, void __user *uaddr)
 632 {
 633         u32 val, newval;
 634         u32 __user *uval = uaddr;
 635
 636         /* Fail if we have unknown bits set. */
 637         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 638                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 639                 return -ENOENT;
 640
 641         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
 642         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
 643                 if (KVM_REG_SIZE(id) != 4)
 644                         return -ENOENT;
 645                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
 646                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
 647                 if (!is_valid_cache(val))
 648                         return -ENOENT;
 649
 650                 if (get_user(newval, uval))
 651                         return -EFAULT;
 652
 653                 /* This is also invariant: you can't change it. */
 654                 if (newval != get_ccsidr(val))
 655                         return -EINVAL;
 656                 return 0;
 657         default:
 658                 return -ENOENT;
 659         }
 660 }
 661
 662 #ifdef CONFIG_VFPv3
 663 static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
 664                                    KVM_REG_ARM_VFP_FPSCR,
 665                                    KVM_REG_ARM_VFP_FPINST,
 666                                    KVM_REG_ARM_VFP_FPINST2,
 667                                    KVM_REG_ARM_VFP_MVFR0,
 668                                    KVM_REG_ARM_VFP_MVFR1,
 669                                    KVM_REG_ARM_VFP_FPSID };
 670
 671 static unsigned int num_fp_regs(void)
 672 {
 673         if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
 674                 return 32;
 675         else
 676                 return 16;
 677 }
 678
 679 static unsigned int num_vfp_regs(void)
 680 {
 681         /* Normal FP regs + control regs. */
 682         return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
 683 }
 684
 685 static int copy_vfp_regids(u64 __user *uindices)
 686 {
 687         unsigned int i;
 688         const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
 689         const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 690
 691         for (i = 0; i < num_fp_regs(); i++) {
 692                 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
 693                              uindices))
 694                         return -EFAULT;
 695                 uindices++;
 696         }
 697
 698         for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
 699                 if (put_user(u32reg | vfp_sysregs[i], uindices))
 700                         return -EFAULT;
 701                 uindices++;
 702         }
 703
 704         return num_vfp_regs();
 705 }
 706
 707 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
 708 {
 709         u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
 710         u32 val;
 711
 712         /* Fail if we have unknown bits set. */
 713         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 714                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 715                 return -ENOENT;
 716
 717         if (vfpid < num_fp_regs()) {
 718                 if (KVM_REG_SIZE(id) != 8)
 719                         return -ENOENT;
 720                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
 721                                    id);
 722         }
 723
 724         /* FP control registers are all 32 bit. */
 725         if (KVM_REG_SIZE(id) != 4)
 726                 return -ENOENT;
 727
 728         switch (vfpid) {
 729         case KVM_REG_ARM_VFP_FPEXC:
 730                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
 731         case KVM_REG_ARM_VFP_FPSCR:
 732                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
 733         case KVM_REG_ARM_VFP_FPINST:
 734                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
 735         case KVM_REG_ARM_VFP_FPINST2:
 736                 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
 737         case KVM_REG_ARM_VFP_MVFR0:
 738                 val = fmrx(MVFR0);
 739                 return reg_to_user(uaddr, &val, id);
 740         case KVM_REG_ARM_VFP_MVFR1:
 741                 val = fmrx(MVFR1);
 742                 return reg_to_user(uaddr, &val, id);
 743         case KVM_REG_ARM_VFP_FPSID:
 744                 val = fmrx(FPSID);
 745                 return reg_to_user(uaddr, &val, id);
 746         default:
 747                 return -ENOENT;
 748         }
 749 }
 750
 751 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
 752 {
 753         u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
 754         u32 val;
 755
 756         /* Fail if we have unknown bits set. */
 757         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
 758                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
 759                 return -ENOENT;
 760
 761         if (vfpid < num_fp_regs()) {
 762                 if (KVM_REG_SIZE(id) != 8)
 763                         return -ENOENT;
 764                 return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
 765                                      uaddr, id);
 766         }
 767
 768         /* FP control registers are all 32 bit. */
 769         if (KVM_REG_SIZE(id) != 4)
 770                 return -ENOENT;
 771
 772         switch (vfpid) {
 773         case KVM_REG_ARM_VFP_FPEXC:
 774                 return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
 775         case KVM_REG_ARM_VFP_FPSCR:
 776                 return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
 777         case KVM_REG_ARM_VFP_FPINST:
 778                 return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
 779         case KVM_REG_ARM_VFP_FPINST2:
 780                 return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
 781         /* These are invariant. */
 782         case KVM_REG_ARM_VFP_MVFR0:
 783                 if (reg_from_user(&val, uaddr, id))
 784                         return -EFAULT;
 785                 if (val != fmrx(MVFR0))
 786                         return -EINVAL;
 787                 return 0;
 788         case KVM_REG_ARM_VFP_MVFR1:
 789                 if (reg_from_user(&val, uaddr, id))
 790                         return -EFAULT;
 791                 if (val != fmrx(MVFR1))
 792                         return -EINVAL;
 793                 return 0;
 794         case KVM_REG_ARM_VFP_FPSID:
 795                 if (reg_from_user(&val, uaddr, id))
 796                         return -EFAULT;
 797                 if (val != fmrx(FPSID))
 798                         return -EINVAL;
 799                 return 0;
 800         default:
 801                 return -ENOENT;
 802         }
 803 }
 804 #else /* !CONFIG_VFPv3 */
 805 static unsigned int num_vfp_regs(void)
 806 {
 807         return 0;
 808 }
 809
 810 static int copy_vfp_regids(u64 __user *uindices)
 811 {
 812         return 0;
 813 }
 814
 815 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
 816 {
 817         return -ENOENT;
 818 }
 819
 820 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
 821 {
 822         return -ENOENT;
 823 }
 824 #endif /* !CONFIG_VFPv3 */
 825
 826 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 827 {
 828         const struct coproc_reg *r;
 829         void __user *uaddr = (void __user *)(long)reg->addr;
 830
 831         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 832                 return demux_c15_get(reg->id, uaddr);
 833
 834         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
 835                 return vfp_get_reg(vcpu, reg->id, uaddr);
 836
 837         r = index_to_coproc_reg(vcpu, reg->id);
 838         if (!r)
 839                 return get_invariant_cp15(reg->id, uaddr);
 840
 841         /* Note: copies two regs if size is 64 bit. */
 842         return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
 843 }
 844
 845 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
 846 {
 847         const struct coproc_reg *r;
 848         void __user *uaddr = (void __user *)(long)reg->addr;
 849
 850         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
 851                 return demux_c15_set(reg->id, uaddr);
 852
 853         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
 854                 return vfp_set_reg(vcpu, reg->id, uaddr);
 855
 856         r = index_to_coproc_reg(vcpu, reg->id);
 857         if (!r)
 858                 return set_invariant_cp15(reg->id, uaddr);
 859
 860         /* Note: copies two regs if size is 64 bit */
 861         return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
 862 }
 863
 864 static unsigned int num_demux_regs(void)
 865 {
 866         unsigned int i, count = 0;
 867
 868         for (i = 0; i < CSSELR_MAX; i++)
 869                 if (is_valid_cache(i))
 870                         count++;
 871
 872         return count;
 873 }
 874
 875 static int write_demux_regids(u64 __user *uindices)
 876 {
 877         u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
 878         unsigned int i;
 879
 880         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
 881         for (i = 0; i < CSSELR_MAX; i++) {
 882                 if (!is_valid_cache(i))
 883                         continue;
 884                 if (put_user(val | i, uindices))
 885                         return -EFAULT;
 886                 uindices++;
 887         }
 888         return 0;
 889 }
 890
 891 static u64 cp15_to_index(const struct coproc_reg *reg)
 892 {
 893         u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
 894         if (reg->is_64) {
 895                 val |= KVM_REG_SIZE_U64;
 896                 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
 897                 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
 898         } else {
 899                 val |= KVM_REG_SIZE_U32;
 900                 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
 901                 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
 902                 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
 903                 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
 904         }
 905         return val;
 906 }
 907
 908 static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
 909 {
 910         if (!*uind)
 911                 return true;
 912
 913         if (put_user(cp15_to_index(reg), *uind))
 914                 return false;
 915
 916         (*uind)++;
 917         return true;
 918 }
 919
 920 /* Assumed ordered tables, see kvm_coproc_table_init. */
 921 static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
 922 {
 923         const struct coproc_reg *i1, *i2, *end1, *end2;
 924         unsigned int total = 0;
 925         size_t num;
 926
 927         /* We check for duplicates here, to allow arch-specific overrides. */
 928         i1 = get_target_table(vcpu->arch.target, &num);
 929         end1 = i1 + num;
 930         i2 = cp15_regs;
 931         end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
 932
 933         BUG_ON(i1 == end1 || i2 == end2);
 934
 935         /* Walk carefully, as both tables may refer to the same register. */
 936         while (i1 || i2) {
 937                 int cmp = cmp_reg(i1, i2);
 938                 /* target-specific overrides generic entry. */
 939                 if (cmp <= 0) {
 940                         /* Ignore registers we trap but don't save. */
 941                         if (i1->reg) {
 942                                 if (!copy_reg_to_user(i1, &uind))
 943                                         return -EFAULT;
 944                                 total++;
 945                         }
 946                 } else {
 947                         /* Ignore registers we trap but don't save. */
 948                         if (i2->reg) {
 949                                 if (!copy_reg_to_user(i2, &uind))
 950                                         return -EFAULT;
 951                                 total++;
 952                         }
 953                 }
 954
 955                 if (cmp <= 0 && ++i1 == end1)
 956                         i1 = NULL;
 957                 if (cmp >= 0 && ++i2 == end2)
 958                         i2 = NULL;
 959         }
 960         return total;
 961 }
 962
 963 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
 964 {
 965         return ARRAY_SIZE(invariant_cp15)
 966                 + num_demux_regs()
 967                 + num_vfp_regs()
 968                 + walk_cp15(vcpu, (u64 __user *)NULL);
 969 }
 970
 971 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 972 {
 973         unsigned int i;
 974         int err;
 975
 976         /* Then give them all the invariant registers' indices. */
 977         for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
 978                 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
 979                         return -EFAULT;
 980                 uindices++;
 981         }
 982
 983         err = walk_cp15(vcpu, uindices);
 984         if (err < 0)
 985                 return err;
 986         uindices += err;
 987
 988         err = copy_vfp_regids(uindices);
 989         if (err < 0)
 990                 return err;
 991         uindices += err;
 992
 993         return write_demux_regids(uindices);
 994 }
 995
 996 void kvm_coproc_table_init(void)
 997 {
 998         unsigned int i;
 999
1000         /* Make sure tables are unique and in order. */
1001         for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
1002                 BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
1003
1004         /* We abuse the reset function to overwrite the table itself. */
1005         for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1006                 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1007
1008         /*
1009          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1010          *
1011          *   If software reads the Cache Type fields from Ctype1
1012          *   upwards, once it has seen a value of 0b000, no caches
1013          *   exist at further-out levels of the hierarchy. So, for
1014          *   example, if Ctype3 is the first Cache Type field with a
1015          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1016          *   ignored.
1017          */
1018         asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1019         for (i = 0; i < 7; i++)
1020                 if (((cache_levels >> (i*3)) & 7) == 0)
1021                         break;
1022         /* Clear all higher bits. */
1023         cache_levels &= (1 << (i*3))-1;
1024 }
1025
1026 /**
1027  * kvm_reset_coprocs - sets cp15 registers to reset value
1028  * @vcpu: The VCPU pointer
1029  *
1030  * This function finds the right table above and sets the registers on the
1031  * virtual CPU struct to their architecturally defined reset values.
1032  */
1033 void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1034 {
1035         size_t num;
1036         const struct coproc_reg *table;
1037
1038         /* Catch someone adding a register without putting in reset entry. */
1039         memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
1040
1041         /* Generic chip reset first (so target could override). */
1042         reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1043
1044         table = get_target_table(vcpu->arch.target, &num);
1045         reset_coproc_regs(vcpu, table, num);
1046
1047         for (num = 1; num < NR_CP15_REGS; num++)
1048                 if (vcpu->arch.cp15[num] == 0x42424242)
1049                         panic("Didn't reset vcpu->arch.cp15[%zi]", num);
1050 }