?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / amd / powerplay / hwmgr / vega12_hwmgr.c
blob0789d64246ca5dd0567fba6655fe4c5e5684e58c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/fb.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28
29 #include "hwmgr.h"
30 #include "amd_powerplay.h"
31 #include "vega12_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega12_inc.h"
37 #include "pppcielanes.h"
38 #include "vega12_hwmgr.h"
39 #include "vega12_processpptables.h"
40 #include "vega12_pptable.h"
41 #include "vega12_thermal.h"
42 #include "vega12_ppsmc.h"
43 #include "pp_debug.h"
44 #include "amd_pcie_helpers.h"
45 #include "ppinterrupt.h"
46 #include "pp_overdriver.h"
47 #include "pp_thermal.h"
48
49
50 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
51 enum pp_clock_type type, uint32_t mask);
52 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
53 uint32_t *clock,
54 PPCLK_e clock_select,
55 bool max);
56
57 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
58 {
59 struct vega12_hwmgr *data =
60 (struct vega12_hwmgr *)(hwmgr->backend);
61
62 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
63 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
64 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
65 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
66 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
67
68 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
69 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
70 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
71 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
72 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
73 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
74 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
75 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
76 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
77 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
78 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
79 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
80 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
81
82 data->registry_data.disallowed_features = 0x0;
83 data->registry_data.od_state_in_dc_support = 0;
84 data->registry_data.thermal_support = 1;
85 data->registry_data.skip_baco_hardware = 0;
86
87 data->registry_data.log_avfs_param = 0;
88 data->registry_data.sclk_throttle_low_notification = 1;
89 data->registry_data.force_dpm_high = 0;
90 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
91
92 data->registry_data.didt_support = 0;
93 if (data->registry_data.didt_support) {
94 data->registry_data.didt_mode = 6;
95 data->registry_data.sq_ramping_support = 1;
96 data->registry_data.db_ramping_support = 0;
97 data->registry_data.td_ramping_support = 0;
98 data->registry_data.tcp_ramping_support = 0;
99 data->registry_data.dbr_ramping_support = 0;
100 data->registry_data.edc_didt_support = 1;
101 data->registry_data.gc_didt_support = 0;
102 data->registry_data.psm_didt_support = 0;
103 }
104
105 data->registry_data.pcie_lane_override = 0xff;
106 data->registry_data.pcie_speed_override = 0xff;
107 data->registry_data.pcie_clock_override = 0xffffffff;
108 data->registry_data.regulator_hot_gpio_support = 1;
109 data->registry_data.ac_dc_switch_gpio_support = 0;
110 data->registry_data.quick_transition_support = 0;
111 data->registry_data.zrpm_start_temp = 0xffff;
112 data->registry_data.zrpm_stop_temp = 0xffff;
113 data->registry_data.odn_feature_enable = 1;
114 data->registry_data.disable_water_mark = 0;
115 data->registry_data.disable_pp_tuning = 0;
116 data->registry_data.disable_xlpp_tuning = 0;
117 data->registry_data.disable_workload_policy = 0;
118 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
119 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
120 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
121 data->registry_data.force_workload_policy_mask = 0;
122 data->registry_data.disable_3d_fs_detection = 0;
123 data->registry_data.fps_support = 1;
124 data->registry_data.disable_auto_wattman = 1;
125 data->registry_data.auto_wattman_debug = 0;
126 data->registry_data.auto_wattman_sample_period = 100;
127 data->registry_data.auto_wattman_threshold = 50;
128 }
129
130 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
131 {
132 struct vega12_hwmgr *data =
133 (struct vega12_hwmgr *)(hwmgr->backend);
134 struct amdgpu_device *adev = hwmgr->adev;
135
136 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
137 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
138 PHM_PlatformCaps_ControlVDDCI);
139
140 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
141 PHM_PlatformCaps_TablelessHardwareInterface);
142
143 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
144 PHM_PlatformCaps_EnableSMU7ThermalManagement);
145
146 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
147 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
148 PHM_PlatformCaps_UVDPowerGating);
149 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
150 PHM_PlatformCaps_UVDDynamicPowerGating);
151 }
152
153 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
154 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
155 PHM_PlatformCaps_VCEPowerGating);
156
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_UnTabledHardwareInterface);
159
160 if (data->registry_data.odn_feature_enable)
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_ODNinACSupport);
163 else {
164 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
165 PHM_PlatformCaps_OD6inACSupport);
166 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
167 PHM_PlatformCaps_OD6PlusinACSupport);
168 }
169
170 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
171 PHM_PlatformCaps_ActivityReporting);
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_FanSpeedInTableIsRPM);
174
175 if (data->registry_data.od_state_in_dc_support) {
176 if (data->registry_data.odn_feature_enable)
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
178 PHM_PlatformCaps_ODNinDCSupport);
179 else {
180 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
181 PHM_PlatformCaps_OD6inDCSupport);
182 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
183 PHM_PlatformCaps_OD6PlusinDCSupport);
184 }
185 }
186
187 if (data->registry_data.thermal_support
188 && data->registry_data.fuzzy_fan_control_support
189 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 PHM_PlatformCaps_ODFuzzyFanControlSupport);
192
193 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
194 PHM_PlatformCaps_DynamicPowerManagement);
195 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
196 PHM_PlatformCaps_SMC);
197 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
198 PHM_PlatformCaps_ThermalPolicyDelay);
199
200 if (data->registry_data.force_dpm_high)
201 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
202 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
203
204 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
205 PHM_PlatformCaps_DynamicUVDState);
206
207 if (data->registry_data.sclk_throttle_low_notification)
208 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_SclkThrottleLowNotification);
210
211 /* power tune caps */
212 /* assume disabled */
213 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
214 PHM_PlatformCaps_PowerContainment);
215 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
216 PHM_PlatformCaps_DiDtSupport);
217 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
218 PHM_PlatformCaps_SQRamping);
219 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
220 PHM_PlatformCaps_DBRamping);
221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
222 PHM_PlatformCaps_TDRamping);
223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
224 PHM_PlatformCaps_TCPRamping);
225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_DBRRamping);
227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
228 PHM_PlatformCaps_DiDtEDCEnable);
229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
230 PHM_PlatformCaps_GCEDC);
231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_PSM);
233
234 if (data->registry_data.didt_support) {
235 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
236 if (data->registry_data.sq_ramping_support)
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
238 if (data->registry_data.db_ramping_support)
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
240 if (data->registry_data.td_ramping_support)
241 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
242 if (data->registry_data.tcp_ramping_support)
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
244 if (data->registry_data.dbr_ramping_support)
245 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
246 if (data->registry_data.edc_didt_support)
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
248 if (data->registry_data.gc_didt_support)
249 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
250 if (data->registry_data.psm_didt_support)
251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
252 }
253
254 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_RegulatorHot);
256
257 if (data->registry_data.ac_dc_switch_gpio_support) {
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_AutomaticDCTransition);
260 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
261 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
262 }
263
264 if (data->registry_data.quick_transition_support) {
265 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
266 PHM_PlatformCaps_AutomaticDCTransition);
267 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
268 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
269 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
270 PHM_PlatformCaps_Falcon_QuickTransition);
271 }
272
273 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
274 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
275 PHM_PlatformCaps_LowestUclkReservedForUlv);
276 if (data->lowest_uclk_reserved_for_ulv == 1)
277 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
278 PHM_PlatformCaps_LowestUclkReservedForUlv);
279 }
280
281 if (data->registry_data.custom_fan_support)
282 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
283 PHM_PlatformCaps_CustomFanControlSupport);
284
285 return 0;
286 }
287
288 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
289 {
290 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
291 int i;
292
293 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
294 FEATURE_DPM_PREFETCHER_BIT;
295 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
296 FEATURE_DPM_GFXCLK_BIT;
297 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
298 FEATURE_DPM_UCLK_BIT;
299 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
300 FEATURE_DPM_SOCCLK_BIT;
301 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
302 FEATURE_DPM_UVD_BIT;
303 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
304 FEATURE_DPM_VCE_BIT;
305 data->smu_features[GNLD_ULV].smu_feature_id =
306 FEATURE_ULV_BIT;
307 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
308 FEATURE_DPM_MP0CLK_BIT;
309 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
310 FEATURE_DPM_LINK_BIT;
311 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
312 FEATURE_DPM_DCEFCLK_BIT;
313 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
314 FEATURE_DS_GFXCLK_BIT;
315 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
316 FEATURE_DS_SOCCLK_BIT;
317 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
318 FEATURE_DS_LCLK_BIT;
319 data->smu_features[GNLD_PPT].smu_feature_id =
320 FEATURE_PPT_BIT;
321 data->smu_features[GNLD_TDC].smu_feature_id =
322 FEATURE_TDC_BIT;
323 data->smu_features[GNLD_THERMAL].smu_feature_id =
324 FEATURE_THERMAL_BIT;
325 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
326 FEATURE_GFX_PER_CU_CG_BIT;
327 data->smu_features[GNLD_RM].smu_feature_id =
328 FEATURE_RM_BIT;
329 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
330 FEATURE_DS_DCEFCLK_BIT;
331 data->smu_features[GNLD_ACDC].smu_feature_id =
332 FEATURE_ACDC_BIT;
333 data->smu_features[GNLD_VR0HOT].smu_feature_id =
334 FEATURE_VR0HOT_BIT;
335 data->smu_features[GNLD_VR1HOT].smu_feature_id =
336 FEATURE_VR1HOT_BIT;
337 data->smu_features[GNLD_FW_CTF].smu_feature_id =
338 FEATURE_FW_CTF_BIT;
339 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
340 FEATURE_LED_DISPLAY_BIT;
341 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
342 FEATURE_FAN_CONTROL_BIT;
343 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
344 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
345 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
346 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
347
348 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
349 data->smu_features[i].smu_feature_bitmap =
350 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
351 data->smu_features[i].allowed =
352 ((data->registry_data.disallowed_features >> i) & 1) ?
353 false : true;
354 }
355 }
356
357 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
358 {
359 return 0;
360 }
361
362 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
363 {
364 kfree(hwmgr->backend);
365 hwmgr->backend = NULL;
366
367 return 0;
368 }
369
370 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
371 {
372 int result = 0;
373 struct vega12_hwmgr *data;
374 struct amdgpu_device *adev = hwmgr->adev;
375
376 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
377 if (data == NULL)
378 return -ENOMEM;
379
380 hwmgr->backend = data;
381
382 vega12_set_default_registry_data(hwmgr);
383
384 data->disable_dpm_mask = 0xff;
385 data->workload_mask = 0xff;
386
387 /* need to set voltage control types before EVV patching */
388 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
389 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
390 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
391
392 data->water_marks_bitmap = 0;
393 data->avfs_exist = false;
394
395 vega12_set_features_platform_caps(hwmgr);
396
397 vega12_init_dpm_defaults(hwmgr);
398
399 /* Parse pptable data read from VBIOS */
400 vega12_set_private_data_based_on_pptable(hwmgr);
401
402 data->is_tlu_enabled = false;
403
404 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
405 VEGA12_MAX_HARDWARE_POWERLEVELS;
406 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
407 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
408
409 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
410 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
411 hwmgr->platform_descriptor.clockStep.engineClock = 500;
412 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
413
414 data->total_active_cus = adev->gfx.cu_info.number;
415 /* Setup default Overdrive Fan control settings */
416 data->odn_fan_table.target_fan_speed =
417 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
418 data->odn_fan_table.target_temperature =
419 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
420 data->odn_fan_table.min_performance_clock =
421 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
422 data->odn_fan_table.min_fan_limit =
423 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
424 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
425
426 if (hwmgr->feature_mask & PP_GFXOFF_MASK)
427 data->gfxoff_controlled_by_driver = true;
428 else
429 data->gfxoff_controlled_by_driver = false;
430
431 return result;
432 }
433
434 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
435 {
436 struct vega12_hwmgr *data =
437 (struct vega12_hwmgr *)(hwmgr->backend);
438
439 data->low_sclk_interrupt_threshold = 0;
440
441 return 0;
442 }
443
444 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
445 {
446 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
447 "Failed to init sclk threshold!",
448 return -EINVAL);
449
450 return 0;
451 }
452
453 /*
454 * @fn vega12_init_dpm_state
455 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
456 *
457 * @param dpm_state - the address of the DPM Table to initiailize.
458 * @return None.
459 */
460 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
461 {
462 dpm_state->soft_min_level = 0x0;
463 dpm_state->soft_max_level = 0xffff;
464 dpm_state->hard_min_level = 0x0;
465 dpm_state->hard_max_level = 0xffff;
466 }
467
468 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
469 PPCLK_e clk_id, uint32_t *num_of_levels)
470 {
471 int ret = 0;
472
473 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
474 PPSMC_MSG_GetDpmFreqByIndex,
475 (clk_id << 16 | 0xFF));
476 PP_ASSERT_WITH_CODE(!ret,
477 "[GetNumOfDpmLevel] failed to get dpm levels!",
478 return ret);
479
480 *num_of_levels = smum_get_argument(hwmgr);
481 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
482 "[GetNumOfDpmLevel] number of clk levels is invalid!",
483 return -EINVAL);
484
485 return ret;
486 }
487
488 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
489 PPCLK_e clkID, uint32_t index, uint32_t *clock)
490 {
491 int result = 0;
492
493 /*
494 *SMU expects the Clock ID to be in the top 16 bits.
495 *Lower 16 bits specify the level
496 */
497 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
498 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index)) == 0,
499 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
500 return -EINVAL);
501
502 *clock = smum_get_argument(hwmgr);
503
504 return result;
505 }
506
507 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
508 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
509 {
510 int ret = 0;
511 uint32_t i, num_of_levels, clk;
512
513 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
514 PP_ASSERT_WITH_CODE(!ret,
515 "[SetupSingleDpmTable] failed to get clk levels!",
516 return ret);
517
518 dpm_table->count = num_of_levels;
519
520 for (i = 0; i < num_of_levels; i++) {
521 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
522 PP_ASSERT_WITH_CODE(!ret,
523 "[SetupSingleDpmTable] failed to get clk of specific level!",
524 return ret);
525 dpm_table->dpm_levels[i].value = clk;
526 dpm_table->dpm_levels[i].enabled = true;
527 }
528
529 return ret;
530 }
531
532 /*
533 * This function is to initialize all DPM state tables
534 * for SMU based on the dependency table.
535 * Dynamic state patching function will then trim these
536 * state tables to the allowed range based
537 * on the power policy or external client requests,
538 * such as UVD request, etc.
539 */
540 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
541 {
542
543 struct vega12_hwmgr *data =
544 (struct vega12_hwmgr *)(hwmgr->backend);
545 struct vega12_single_dpm_table *dpm_table;
546 int ret = 0;
547
548 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
549
550 /* socclk */
551 dpm_table = &(data->dpm_table.soc_table);
552 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
553 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
554 PP_ASSERT_WITH_CODE(!ret,
555 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
556 return ret);
557 } else {
558 dpm_table->count = 1;
559 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
560 }
561 vega12_init_dpm_state(&(dpm_table->dpm_state));
562
563 /* gfxclk */
564 dpm_table = &(data->dpm_table.gfx_table);
565 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
566 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
567 PP_ASSERT_WITH_CODE(!ret,
568 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
569 return ret);
570 } else {
571 dpm_table->count = 1;
572 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
573 }
574 vega12_init_dpm_state(&(dpm_table->dpm_state));
575
576 /* memclk */
577 dpm_table = &(data->dpm_table.mem_table);
578 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
579 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
580 PP_ASSERT_WITH_CODE(!ret,
581 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
582 return ret);
583 } else {
584 dpm_table->count = 1;
585 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
586 }
587 vega12_init_dpm_state(&(dpm_table->dpm_state));
588
589 /* eclk */
590 dpm_table = &(data->dpm_table.eclk_table);
591 if (data->smu_features[GNLD_DPM_VCE].enabled) {
592 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
593 PP_ASSERT_WITH_CODE(!ret,
594 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
595 return ret);
596 } else {
597 dpm_table->count = 1;
598 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
599 }
600 vega12_init_dpm_state(&(dpm_table->dpm_state));
601
602 /* vclk */
603 dpm_table = &(data->dpm_table.vclk_table);
604 if (data->smu_features[GNLD_DPM_UVD].enabled) {
605 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
606 PP_ASSERT_WITH_CODE(!ret,
607 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
608 return ret);
609 } else {
610 dpm_table->count = 1;
611 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
612 }
613 vega12_init_dpm_state(&(dpm_table->dpm_state));
614
615 /* dclk */
616 dpm_table = &(data->dpm_table.dclk_table);
617 if (data->smu_features[GNLD_DPM_UVD].enabled) {
618 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
619 PP_ASSERT_WITH_CODE(!ret,
620 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
621 return ret);
622 } else {
623 dpm_table->count = 1;
624 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
625 }
626 vega12_init_dpm_state(&(dpm_table->dpm_state));
627
628 /* dcefclk */
629 dpm_table = &(data->dpm_table.dcef_table);
630 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
631 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
632 PP_ASSERT_WITH_CODE(!ret,
633 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
634 return ret);
635 } else {
636 dpm_table->count = 1;
637 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
638 }
639 vega12_init_dpm_state(&(dpm_table->dpm_state));
640
641 /* pixclk */
642 dpm_table = &(data->dpm_table.pixel_table);
643 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
644 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
645 PP_ASSERT_WITH_CODE(!ret,
646 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
647 return ret);
648 } else
649 dpm_table->count = 0;
650 vega12_init_dpm_state(&(dpm_table->dpm_state));
651
652 /* dispclk */
653 dpm_table = &(data->dpm_table.display_table);
654 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
655 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
656 PP_ASSERT_WITH_CODE(!ret,
657 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
658 return ret);
659 } else
660 dpm_table->count = 0;
661 vega12_init_dpm_state(&(dpm_table->dpm_state));
662
663 /* phyclk */
664 dpm_table = &(data->dpm_table.phy_table);
665 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
666 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
667 PP_ASSERT_WITH_CODE(!ret,
668 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
669 return ret);
670 } else
671 dpm_table->count = 0;
672 vega12_init_dpm_state(&(dpm_table->dpm_state));
673
674 /* save a copy of the default DPM table */
675 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
676 sizeof(struct vega12_dpm_table));
677
678 return 0;
679 }
680
681 #if 0
682 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
683 {
684 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
685 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
686 uint32_t min_level;
687
688 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
689 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
690
691 /* Optimize compute power profile: Use only highest
692 * 2 power levels (if more than 2 are available)
693 */
694 if (dpm_table->count > 2)
695 min_level = dpm_table->count - 2;
696 else if (dpm_table->count == 2)
697 min_level = 1;
698 else
699 min_level = 0;
700
701 hwmgr->default_compute_power_profile.min_sclk =
702 dpm_table->dpm_levels[min_level].value;
703
704 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
705 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
706
707 return 0;
708 }
709 #endif
710
711 /**
712 * Initializes the SMC table and uploads it
713 *
714 * @param hwmgr the address of the powerplay hardware manager.
715 * @param pInput the pointer to input data (PowerState)
716 * @return always 0
717 */
718 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
719 {
720 int result;
721 struct vega12_hwmgr *data =
722 (struct vega12_hwmgr *)(hwmgr->backend);
723 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
724 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
725 struct phm_ppt_v3_information *pptable_information =
726 (struct phm_ppt_v3_information *)hwmgr->pptable;
727
728 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
729 if (!result) {
730 data->vbios_boot_state.vddc = boot_up_values.usVddc;
731 data->vbios_boot_state.vddci = boot_up_values.usVddci;
732 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
733 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
734 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
735 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
736 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
737 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
738 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
739 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
740 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
741 smum_send_msg_to_smc_with_parameter(hwmgr,
742 PPSMC_MSG_SetMinDeepSleepDcefclk,
743 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
744 }
745
746 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
747
748 result = vega12_copy_table_to_smc(hwmgr,
749 (uint8_t *)pp_table, TABLE_PPTABLE);
750 PP_ASSERT_WITH_CODE(!result,
751 "Failed to upload PPtable!", return result);
752
753 return 0;
754 }
755
756 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
757 {
758 struct vega12_hwmgr *data =
759 (struct vega12_hwmgr *)(hwmgr->backend);
760 int i;
761 uint32_t allowed_features_low = 0, allowed_features_high = 0;
762
763 for (i = 0; i < GNLD_FEATURES_MAX; i++)
764 if (data->smu_features[i].allowed)
765 data->smu_features[i].smu_feature_id > 31 ?
766 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
767 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
768
769 PP_ASSERT_WITH_CODE(
770 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high) == 0,
771 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
772 return -1);
773
774 PP_ASSERT_WITH_CODE(
775 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low) == 0,
776 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
777 return -1);
778
779 return 0;
780 }
781
782 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
783 {
784 struct vega12_hwmgr *data =
785 (struct vega12_hwmgr *)(hwmgr->backend);
786
787 data->uvd_power_gated = true;
788 data->vce_power_gated = true;
789
790 if (data->smu_features[GNLD_DPM_UVD].enabled)
791 data->uvd_power_gated = false;
792
793 if (data->smu_features[GNLD_DPM_VCE].enabled)
794 data->vce_power_gated = false;
795 }
796
797 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
798 {
799 struct vega12_hwmgr *data =
800 (struct vega12_hwmgr *)(hwmgr->backend);
801 uint64_t features_enabled;
802 int i;
803 bool enabled;
804
805 PP_ASSERT_WITH_CODE(
806 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures) == 0,
807 "[EnableAllSMUFeatures] Failed to enable all smu features!",
808 return -1);
809
810 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
811 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
812 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
813 data->smu_features[i].enabled = enabled;
814 data->smu_features[i].supported = enabled;
815 }
816 }
817
818 vega12_init_powergate_state(hwmgr);
819
820 return 0;
821 }
822
823 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
824 {
825 struct vega12_hwmgr *data =
826 (struct vega12_hwmgr *)(hwmgr->backend);
827 uint64_t features_enabled;
828 int i;
829 bool enabled;
830
831 PP_ASSERT_WITH_CODE(
832 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures) == 0,
833 "[DisableAllSMUFeatures] Failed to disable all smu features!",
834 return -1);
835
836 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
837 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
838 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
839 data->smu_features[i].enabled = enabled;
840 data->smu_features[i].supported = enabled;
841 }
842 }
843
844 return 0;
845 }
846
847 static int vega12_odn_initialize_default_settings(
848 struct pp_hwmgr *hwmgr)
849 {
850 return 0;
851 }
852
853 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
854 uint32_t adjust_percent)
855 {
856 return smum_send_msg_to_smc_with_parameter(hwmgr,
857 PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
858 }
859
860 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
861 {
862 int adjust_percent, result = 0;
863
864 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
865 adjust_percent =
866 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
867 hwmgr->platform_descriptor.TDPAdjustment :
868 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
869 result = vega12_set_overdrive_target_percentage(hwmgr,
870 (uint32_t)adjust_percent);
871 }
872 return result;
873 }
874
875 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
876 PPCLK_e clkid, struct vega12_clock_range *clock)
877 {
878 /* AC Max */
879 PP_ASSERT_WITH_CODE(
880 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0,
881 "[GetClockRanges] Failed to get max ac clock from SMC!",
882 return -EINVAL);
883 clock->ACMax = smum_get_argument(hwmgr);
884
885 /* AC Min */
886 PP_ASSERT_WITH_CODE(
887 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0,
888 "[GetClockRanges] Failed to get min ac clock from SMC!",
889 return -EINVAL);
890 clock->ACMin = smum_get_argument(hwmgr);
891
892 /* DC Max */
893 PP_ASSERT_WITH_CODE(
894 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0,
895 "[GetClockRanges] Failed to get max dc clock from SMC!",
896 return -EINVAL);
897 clock->DCMax = smum_get_argument(hwmgr);
898
899 return 0;
900 }
901
902 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
903 {
904 struct vega12_hwmgr *data =
905 (struct vega12_hwmgr *)(hwmgr->backend);
906 uint32_t i;
907
908 for (i = 0; i < PPCLK_COUNT; i++)
909 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
910 i, &(data->clk_range[i])),
911 "Failed to get clk range from SMC!",
912 return -EINVAL);
913
914 return 0;
915 }
916
917 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
918 {
919 int tmp_result, result = 0;
920
921 smum_send_msg_to_smc_with_parameter(hwmgr,
922 PPSMC_MSG_NumOfDisplays, 0);
923
924 result = vega12_set_allowed_featuresmask(hwmgr);
925 PP_ASSERT_WITH_CODE(result == 0,
926 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
927 return result);
928
929 tmp_result = vega12_init_smc_table(hwmgr);
930 PP_ASSERT_WITH_CODE(!tmp_result,
931 "Failed to initialize SMC table!",
932 result = tmp_result);
933
934 result = vega12_enable_all_smu_features(hwmgr);
935 PP_ASSERT_WITH_CODE(!result,
936 "Failed to enable all smu features!",
937 return result);
938
939 tmp_result = vega12_power_control_set_level(hwmgr);
940 PP_ASSERT_WITH_CODE(!tmp_result,
941 "Failed to power control set level!",
942 result = tmp_result);
943
944 result = vega12_get_all_clock_ranges(hwmgr);
945 PP_ASSERT_WITH_CODE(!result,
946 "Failed to get all clock ranges!",
947 return result);
948
949 result = vega12_odn_initialize_default_settings(hwmgr);
950 PP_ASSERT_WITH_CODE(!result,
951 "Failed to power control set level!",
952 return result);
953
954 result = vega12_setup_default_dpm_tables(hwmgr);
955 PP_ASSERT_WITH_CODE(!result,
956 "Failed to setup default DPM tables!",
957 return result);
958 return result;
959 }
960
961 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
962 struct pp_hw_power_state *hw_ps)
963 {
964 return 0;
965 }
966
967 static uint32_t vega12_find_lowest_dpm_level(
968 struct vega12_single_dpm_table *table)
969 {
970 uint32_t i;
971
972 for (i = 0; i < table->count; i++) {
973 if (table->dpm_levels[i].enabled)
974 break;
975 }
976
977 if (i >= table->count) {
978 i = 0;
979 table->dpm_levels[i].enabled = true;
980 }
981
982 return i;
983 }
984
985 static uint32_t vega12_find_highest_dpm_level(
986 struct vega12_single_dpm_table *table)
987 {
988 int32_t i = 0;
989 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
990 "[FindHighestDPMLevel] DPM Table has too many entries!",
991 return MAX_REGULAR_DPM_NUMBER - 1);
992
993 for (i = table->count - 1; i >= 0; i--) {
994 if (table->dpm_levels[i].enabled)
995 break;
996 }
997
998 if (i < 0) {
999 i = 0;
1000 table->dpm_levels[i].enabled = true;
1001 }
1002
1003 return (uint32_t)i;
1004 }
1005
1006 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1007 {
1008 struct vega12_hwmgr *data = hwmgr->backend;
1009 uint32_t min_freq;
1010 int ret = 0;
1011
1012 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1013 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1014 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1015 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1016 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1017 "Failed to set soft min gfxclk !",
1018 return ret);
1019 }
1020
1021 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1022 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1023 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1024 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1025 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1026 "Failed to set soft min memclk !",
1027 return ret);
1028
1029 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1030 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1031 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1032 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1033 "Failed to set hard min memclk !",
1034 return ret);
1035 }
1036
1037 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1038 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1039
1040 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1041 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1042 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1043 "Failed to set soft min vclk!",
1044 return ret);
1045
1046 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1047
1048 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1049 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1050 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1051 "Failed to set soft min dclk!",
1052 return ret);
1053 }
1054
1055 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1056 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1057
1058 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1059 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1060 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1061 "Failed to set soft min eclk!",
1062 return ret);
1063 }
1064
1065 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1066 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1067
1068 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1069 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1070 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1071 "Failed to set soft min socclk!",
1072 return ret);
1073 }
1074
1075 return ret;
1076
1077 }
1078
1079 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1080 {
1081 struct vega12_hwmgr *data = hwmgr->backend;
1082 uint32_t max_freq;
1083 int ret = 0;
1084
1085 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1086 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1087
1088 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1089 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1090 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1091 "Failed to set soft max gfxclk!",
1092 return ret);
1093 }
1094
1095 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1096 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1097
1098 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1099 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1100 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1101 "Failed to set soft max memclk!",
1102 return ret);
1103 }
1104
1105 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1106 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1107
1108 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1109 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1110 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1111 "Failed to set soft max vclk!",
1112 return ret);
1113
1114 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1115 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1116 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1117 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1118 "Failed to set soft max dclk!",
1119 return ret);
1120 }
1121
1122 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1123 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1124
1125 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1126 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1127 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1128 "Failed to set soft max eclk!",
1129 return ret);
1130 }
1131
1132 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1133 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1134
1135 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1136 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1137 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1138 "Failed to set soft max socclk!",
1139 return ret);
1140 }
1141
1142 return ret;
1143 }
1144
1145 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1146 {
1147 struct vega12_hwmgr *data =
1148 (struct vega12_hwmgr *)(hwmgr->backend);
1149
1150 if (data->smu_features[GNLD_DPM_VCE].supported) {
1151 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1152 enable,
1153 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1154 "Attempt to Enable/Disable DPM VCE Failed!",
1155 return -1);
1156 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1157 }
1158
1159 return 0;
1160 }
1161
1162 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1163 {
1164 struct vega12_hwmgr *data =
1165 (struct vega12_hwmgr *)(hwmgr->backend);
1166 uint32_t gfx_clk;
1167
1168 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1169 return -1;
1170
1171 if (low)
1172 PP_ASSERT_WITH_CODE(
1173 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1174 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1175 return -1);
1176 else
1177 PP_ASSERT_WITH_CODE(
1178 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1179 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1180 return -1);
1181
1182 return (gfx_clk * 100);
1183 }
1184
1185 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1186 {
1187 struct vega12_hwmgr *data =
1188 (struct vega12_hwmgr *)(hwmgr->backend);
1189 uint32_t mem_clk;
1190
1191 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1192 return -1;
1193
1194 if (low)
1195 PP_ASSERT_WITH_CODE(
1196 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1197 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1198 return -1);
1199 else
1200 PP_ASSERT_WITH_CODE(
1201 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1202 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1203 return -1);
1204
1205 return (mem_clk * 100);
1206 }
1207
1208 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1209 {
1210 #if 0
1211 uint32_t value;
1212
1213 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
1214 PPSMC_MSG_GetCurrPkgPwr),
1215 "Failed to get current package power!",
1216 return -EINVAL);
1217
1218 value = smum_get_argument(hwmgr);
1219 /* power value is an integer */
1220 *query = value << 8;
1221 #endif
1222 return 0;
1223 }
1224
1225 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1226 {
1227 uint32_t gfx_clk = 0;
1228
1229 *gfx_freq = 0;
1230
1231 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1232 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,
1233 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1234 return -EINVAL);
1235 gfx_clk = smum_get_argument(hwmgr);
1236
1237 *gfx_freq = gfx_clk * 100;
1238
1239 return 0;
1240 }
1241
1242 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1243 {
1244 uint32_t mem_clk = 0;
1245
1246 *mclk_freq = 0;
1247
1248 PP_ASSERT_WITH_CODE(
1249 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
1250 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1251 return -EINVAL);
1252 mem_clk = smum_get_argument(hwmgr);
1253
1254 *mclk_freq = mem_clk * 100;
1255
1256 return 0;
1257 }
1258
1259 static int vega12_get_current_activity_percent(
1260 struct pp_hwmgr *hwmgr,
1261 uint32_t *activity_percent)
1262 {
1263 int ret = 0;
1264 uint32_t current_activity = 50;
1265
1266 #if 0
1267 ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
1268 if (!ret) {
1269 current_activity = smum_get_argument(hwmgr);
1270 if (current_activity > 100) {
1271 PP_ASSERT(false,
1272 "[GetCurrentActivityPercent] Activity Percentage Exceeds 100!");
1273 current_activity = 100;
1274 }
1275 } else
1276 PP_ASSERT(false,
1277 "[GetCurrentActivityPercent] Attempt To Send Get Average Graphics Activity to SMU Failed!");
1278 #endif
1279 *activity_percent = current_activity;
1280
1281 return ret;
1282 }
1283
1284 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1285 void *value, int *size)
1286 {
1287 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1288 int ret = 0;
1289
1290 switch (idx) {
1291 case AMDGPU_PP_SENSOR_GFX_SCLK:
1292 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1293 if (!ret)
1294 *size = 4;
1295 break;
1296 case AMDGPU_PP_SENSOR_GFX_MCLK:
1297 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1298 if (!ret)
1299 *size = 4;
1300 break;
1301 case AMDGPU_PP_SENSOR_GPU_LOAD:
1302 ret = vega12_get_current_activity_percent(hwmgr, (uint32_t *)value);
1303 if (!ret)
1304 *size = 4;
1305 break;
1306 case AMDGPU_PP_SENSOR_GPU_TEMP:
1307 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1308 *size = 4;
1309 break;
1310 case AMDGPU_PP_SENSOR_UVD_POWER:
1311 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1312 *size = 4;
1313 break;
1314 case AMDGPU_PP_SENSOR_VCE_POWER:
1315 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1316 *size = 4;
1317 break;
1318 case AMDGPU_PP_SENSOR_GPU_POWER:
1319 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1320
1321 break;
1322 default:
1323 ret = -EINVAL;
1324 break;
1325 }
1326 return ret;
1327 }
1328
1329 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1330 bool has_disp)
1331 {
1332 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1333
1334 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1335 return smum_send_msg_to_smc_with_parameter(hwmgr,
1336 PPSMC_MSG_SetUclkFastSwitch,
1337 has_disp ? 1 : 0);
1338
1339 return 0;
1340 }
1341
1342 int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1343 struct pp_display_clock_request *clock_req)
1344 {
1345 int result = 0;
1346 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1347 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1348 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1349 PPCLK_e clk_select = 0;
1350 uint32_t clk_request = 0;
1351
1352 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1353 switch (clk_type) {
1354 case amd_pp_dcef_clock:
1355 clk_select = PPCLK_DCEFCLK;
1356 break;
1357 case amd_pp_disp_clock:
1358 clk_select = PPCLK_DISPCLK;
1359 break;
1360 case amd_pp_pixel_clock:
1361 clk_select = PPCLK_PIXCLK;
1362 break;
1363 case amd_pp_phy_clock:
1364 clk_select = PPCLK_PHYCLK;
1365 break;
1366 default:
1367 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1368 result = -1;
1369 break;
1370 }
1371
1372 if (!result) {
1373 clk_request = (clk_select << 16) | clk_freq;
1374 result = smum_send_msg_to_smc_with_parameter(hwmgr,
1375 PPSMC_MSG_SetHardMinByFreq,
1376 clk_request);
1377 }
1378 }
1379
1380 return result;
1381 }
1382
1383 static int vega12_notify_smc_display_config_after_ps_adjustment(
1384 struct pp_hwmgr *hwmgr)
1385 {
1386 struct vega12_hwmgr *data =
1387 (struct vega12_hwmgr *)(hwmgr->backend);
1388 struct PP_Clocks min_clocks = {0};
1389 struct pp_display_clock_request clock_req;
1390
1391 if ((hwmgr->display_config->num_display > 1) &&
1392 !hwmgr->display_config->multi_monitor_in_sync &&
1393 !hwmgr->display_config->nb_pstate_switch_disable)
1394 vega12_notify_smc_display_change(hwmgr, false);
1395 else
1396 vega12_notify_smc_display_change(hwmgr, true);
1397
1398 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1399 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1400 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1401
1402 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1403 clock_req.clock_type = amd_pp_dcef_clock;
1404 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1405 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1406 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1407 PP_ASSERT_WITH_CODE(
1408 !smum_send_msg_to_smc_with_parameter(
1409 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1410 min_clocks.dcefClockInSR /100),
1411 "Attempt to set divider for DCEFCLK Failed!",
1412 return -1);
1413 } else {
1414 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1415 }
1416 }
1417
1418 return 0;
1419 }
1420
1421 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1422 {
1423 struct vega12_hwmgr *data =
1424 (struct vega12_hwmgr *)(hwmgr->backend);
1425
1426 uint32_t soft_level;
1427
1428 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1429
1430 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1431 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1432 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1433
1434 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1435
1436 data->dpm_table.mem_table.dpm_state.soft_min_level =
1437 data->dpm_table.mem_table.dpm_state.soft_max_level =
1438 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1439
1440 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1441 "Failed to upload boot level to highest!",
1442 return -1);
1443
1444 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1445 "Failed to upload dpm max level to highest!",
1446 return -1);
1447
1448 return 0;
1449 }
1450
1451 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1452 {
1453 struct vega12_hwmgr *data =
1454 (struct vega12_hwmgr *)(hwmgr->backend);
1455 uint32_t soft_level;
1456
1457 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1458
1459 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1460 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1461 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1462
1463 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1464
1465 data->dpm_table.mem_table.dpm_state.soft_min_level =
1466 data->dpm_table.mem_table.dpm_state.soft_max_level =
1467 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1468
1469 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1470 "Failed to upload boot level to highest!",
1471 return -1);
1472
1473 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1474 "Failed to upload dpm max level to highest!",
1475 return -1);
1476
1477 return 0;
1478
1479 }
1480
1481 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1482 {
1483 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1484 "Failed to upload DPM Bootup Levels!",
1485 return -1);
1486
1487 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1488 "Failed to upload DPM Max Levels!",
1489 return -1);
1490
1491 return 0;
1492 }
1493
1494 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1495 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1496 {
1497 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1498 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1499 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1500 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1501
1502 *sclk_mask = 0;
1503 *mclk_mask = 0;
1504 *soc_mask = 0;
1505
1506 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1507 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1508 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1509 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1510 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1511 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1512 }
1513
1514 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1515 *sclk_mask = 0;
1516 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1517 *mclk_mask = 0;
1518 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1519 *sclk_mask = gfx_dpm_table->count - 1;
1520 *mclk_mask = mem_dpm_table->count - 1;
1521 *soc_mask = soc_dpm_table->count - 1;
1522 }
1523
1524 return 0;
1525 }
1526
1527 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1528 {
1529 switch (mode) {
1530 case AMD_FAN_CTRL_NONE:
1531 break;
1532 case AMD_FAN_CTRL_MANUAL:
1533 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1534 vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1535 break;
1536 case AMD_FAN_CTRL_AUTO:
1537 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1538 vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1539 break;
1540 default:
1541 break;
1542 }
1543 }
1544
1545 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1546 enum amd_dpm_forced_level level)
1547 {
1548 int ret = 0;
1549 uint32_t sclk_mask = 0;
1550 uint32_t mclk_mask = 0;
1551 uint32_t soc_mask = 0;
1552
1553 switch (level) {
1554 case AMD_DPM_FORCED_LEVEL_HIGH:
1555 ret = vega12_force_dpm_highest(hwmgr);
1556 break;
1557 case AMD_DPM_FORCED_LEVEL_LOW:
1558 ret = vega12_force_dpm_lowest(hwmgr);
1559 break;
1560 case AMD_DPM_FORCED_LEVEL_AUTO:
1561 ret = vega12_unforce_dpm_levels(hwmgr);
1562 break;
1563 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1564 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1565 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1566 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1567 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1568 if (ret)
1569 return ret;
1570 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1571 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1572 break;
1573 case AMD_DPM_FORCED_LEVEL_MANUAL:
1574 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1575 default:
1576 break;
1577 }
1578
1579 return ret;
1580 }
1581
1582 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1583 {
1584 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1585
1586 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1587 return AMD_FAN_CTRL_MANUAL;
1588 else
1589 return AMD_FAN_CTRL_AUTO;
1590 }
1591
1592 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1593 struct amd_pp_simple_clock_info *info)
1594 {
1595 #if 0
1596 struct phm_ppt_v2_information *table_info =
1597 (struct phm_ppt_v2_information *)hwmgr->pptable;
1598 struct phm_clock_and_voltage_limits *max_limits =
1599 &table_info->max_clock_voltage_on_ac;
1600
1601 info->engine_max_clock = max_limits->sclk;
1602 info->memory_max_clock = max_limits->mclk;
1603 #endif
1604 return 0;
1605 }
1606
1607 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1608 uint32_t *clock,
1609 PPCLK_e clock_select,
1610 bool max)
1611 {
1612 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1613
1614 if (max)
1615 *clock = data->clk_range[clock_select].ACMax;
1616 else
1617 *clock = data->clk_range[clock_select].ACMin;
1618
1619 return 0;
1620 }
1621
1622 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1623 struct pp_clock_levels_with_latency *clocks)
1624 {
1625 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1626 uint32_t ucount;
1627 int i;
1628 struct vega12_single_dpm_table *dpm_table;
1629
1630 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1631 return -1;
1632
1633 dpm_table = &(data->dpm_table.gfx_table);
1634 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1635 MAX_NUM_CLOCKS : dpm_table->count;
1636
1637 for (i = 0; i < ucount; i++) {
1638 clocks->data[i].clocks_in_khz =
1639 dpm_table->dpm_levels[i].value * 1000;
1640
1641 clocks->data[i].latency_in_us = 0;
1642 }
1643
1644 clocks->num_levels = ucount;
1645
1646 return 0;
1647 }
1648
1649 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1650 uint32_t clock)
1651 {
1652 return 25;
1653 }
1654
1655 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1656 struct pp_clock_levels_with_latency *clocks)
1657 {
1658 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1659 uint32_t ucount;
1660 int i;
1661 struct vega12_single_dpm_table *dpm_table;
1662 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1663 return -1;
1664
1665 dpm_table = &(data->dpm_table.mem_table);
1666 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1667 MAX_NUM_CLOCKS : dpm_table->count;
1668
1669 for (i = 0; i < ucount; i++) {
1670 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1671 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1672 clocks->data[i].latency_in_us =
1673 data->mclk_latency_table.entries[i].latency =
1674 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1675 }
1676
1677 clocks->num_levels = data->mclk_latency_table.count = ucount;
1678
1679 return 0;
1680 }
1681
1682 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1683 struct pp_clock_levels_with_latency *clocks)
1684 {
1685 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1686 uint32_t ucount;
1687 int i;
1688 struct vega12_single_dpm_table *dpm_table;
1689
1690 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1691 return -1;
1692
1693
1694 dpm_table = &(data->dpm_table.dcef_table);
1695 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1696 MAX_NUM_CLOCKS : dpm_table->count;
1697
1698 for (i = 0; i < ucount; i++) {
1699 clocks->data[i].clocks_in_khz =
1700 dpm_table->dpm_levels[i].value * 1000;
1701
1702 clocks->data[i].latency_in_us = 0;
1703 }
1704
1705 clocks->num_levels = ucount;
1706
1707 return 0;
1708 }
1709
1710 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1711 struct pp_clock_levels_with_latency *clocks)
1712 {
1713 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1714 uint32_t ucount;
1715 int i;
1716 struct vega12_single_dpm_table *dpm_table;
1717
1718 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1719 return -1;
1720
1721
1722 dpm_table = &(data->dpm_table.soc_table);
1723 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1724 MAX_NUM_CLOCKS : dpm_table->count;
1725
1726 for (i = 0; i < ucount; i++) {
1727 clocks->data[i].clocks_in_khz =
1728 dpm_table->dpm_levels[i].value * 1000;
1729
1730 clocks->data[i].latency_in_us = 0;
1731 }
1732
1733 clocks->num_levels = ucount;
1734
1735 return 0;
1736
1737 }
1738
1739 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1740 enum amd_pp_clock_type type,
1741 struct pp_clock_levels_with_latency *clocks)
1742 {
1743 int ret;
1744
1745 switch (type) {
1746 case amd_pp_sys_clock:
1747 ret = vega12_get_sclks(hwmgr, clocks);
1748 break;
1749 case amd_pp_mem_clock:
1750 ret = vega12_get_memclocks(hwmgr, clocks);
1751 break;
1752 case amd_pp_dcef_clock:
1753 ret = vega12_get_dcefclocks(hwmgr, clocks);
1754 break;
1755 case amd_pp_soc_clock:
1756 ret = vega12_get_socclocks(hwmgr, clocks);
1757 break;
1758 default:
1759 return -EINVAL;
1760 }
1761
1762 return ret;
1763 }
1764
1765 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1766 enum amd_pp_clock_type type,
1767 struct pp_clock_levels_with_voltage *clocks)
1768 {
1769 clocks->num_levels = 0;
1770
1771 return 0;
1772 }
1773
1774 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1775 void *clock_ranges)
1776 {
1777 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1778 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1779 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1780
1781 if (!data->registry_data.disable_water_mark &&
1782 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1783 data->smu_features[GNLD_DPM_SOCCLK].supported) {
1784 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1785 data->water_marks_bitmap |= WaterMarksExist;
1786 data->water_marks_bitmap &= ~WaterMarksLoaded;
1787 }
1788
1789 return 0;
1790 }
1791
1792 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1793 enum pp_clock_type type, uint32_t mask)
1794 {
1795 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1796 uint32_t soft_min_level, soft_max_level;
1797 int ret = 0;
1798
1799 switch (type) {
1800 case PP_SCLK:
1801 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1802 soft_max_level = mask ? (fls(mask) - 1) : 0;
1803
1804 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1805 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
1806 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1807 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
1808
1809 ret = vega12_upload_dpm_min_level(hwmgr);
1810 PP_ASSERT_WITH_CODE(!ret,
1811 "Failed to upload boot level to lowest!",
1812 return ret);
1813
1814 ret = vega12_upload_dpm_max_level(hwmgr);
1815 PP_ASSERT_WITH_CODE(!ret,
1816 "Failed to upload dpm max level to highest!",
1817 return ret);
1818 break;
1819
1820 case PP_MCLK:
1821 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1822 soft_max_level = mask ? (fls(mask) - 1) : 0;
1823
1824 data->dpm_table.mem_table.dpm_state.soft_min_level =
1825 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
1826 data->dpm_table.mem_table.dpm_state.soft_max_level =
1827 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
1828
1829 ret = vega12_upload_dpm_min_level(hwmgr);
1830 PP_ASSERT_WITH_CODE(!ret,
1831 "Failed to upload boot level to lowest!",
1832 return ret);
1833
1834 ret = vega12_upload_dpm_max_level(hwmgr);
1835 PP_ASSERT_WITH_CODE(!ret,
1836 "Failed to upload dpm max level to highest!",
1837 return ret);
1838
1839 break;
1840
1841 case PP_PCIE:
1842 break;
1843
1844 default:
1845 break;
1846 }
1847
1848 return 0;
1849 }
1850
1851 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
1852 enum pp_clock_type type, char *buf)
1853 {
1854 int i, now, size = 0;
1855 struct pp_clock_levels_with_latency clocks;
1856
1857 switch (type) {
1858 case PP_SCLK:
1859 PP_ASSERT_WITH_CODE(
1860 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
1861 "Attempt to get current gfx clk Failed!",
1862 return -1);
1863
1864 PP_ASSERT_WITH_CODE(
1865 vega12_get_sclks(hwmgr, &clocks) == 0,
1866 "Attempt to get gfx clk levels Failed!",
1867 return -1);
1868 for (i = 0; i < clocks.num_levels; i++)
1869 size += sprintf(buf + size, "%d: %uMhz %s\n",
1870 i, clocks.data[i].clocks_in_khz / 1000,
1871 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
1872 break;
1873
1874 case PP_MCLK:
1875 PP_ASSERT_WITH_CODE(
1876 vega12_get_current_mclk_freq(hwmgr, &now) == 0,
1877 "Attempt to get current mclk freq Failed!",
1878 return -1);
1879
1880 PP_ASSERT_WITH_CODE(
1881 vega12_get_memclocks(hwmgr, &clocks) == 0,
1882 "Attempt to get memory clk levels Failed!",
1883 return -1);
1884 for (i = 0; i < clocks.num_levels; i++)
1885 size += sprintf(buf + size, "%d: %uMhz %s\n",
1886 i, clocks.data[i].clocks_in_khz / 1000,
1887 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
1888 break;
1889
1890 case PP_PCIE:
1891 break;
1892
1893 default:
1894 break;
1895 }
1896 return size;
1897 }
1898
1899 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
1900 {
1901 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1902 struct vega12_single_dpm_table *dpm_table;
1903 bool vblank_too_short = false;
1904 bool disable_mclk_switching;
1905 uint32_t i, latency;
1906
1907 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
1908 !hwmgr->display_config->multi_monitor_in_sync) ||
1909 vblank_too_short;
1910 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
1911
1912 /* gfxclk */
1913 dpm_table = &(data->dpm_table.gfx_table);
1914 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1915 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1916 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1917 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1918
1919 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
1920 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
1921 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
1922 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
1923 }
1924
1925 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1926 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1927 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
1928 }
1929
1930 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1931 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1932 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1933 }
1934 }
1935
1936 /* memclk */
1937 dpm_table = &(data->dpm_table.mem_table);
1938 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1939 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1940 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1941 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1942
1943 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
1944 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
1945 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
1946 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
1947 }
1948
1949 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1950 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1951 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
1952 }
1953
1954 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1955 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1956 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1957 }
1958 }
1959
1960 /* honour DAL's UCLK Hardmin */
1961 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
1962 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
1963
1964 /* Hardmin is dependent on displayconfig */
1965 if (disable_mclk_switching) {
1966 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1967 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
1968 if (data->mclk_latency_table.entries[i].latency <= latency) {
1969 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
1970 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
1971 break;
1972 }
1973 }
1974 }
1975 }
1976
1977 if (hwmgr->display_config->nb_pstate_switch_disable)
1978 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1979
1980 /* vclk */
1981 dpm_table = &(data->dpm_table.vclk_table);
1982 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
1983 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1984 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
1985 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1986
1987 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
1988 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
1989 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
1990 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
1991 }
1992
1993 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1994 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1995 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1996 }
1997 }
1998
1999 /* dclk */
2000 dpm_table = &(data->dpm_table.dclk_table);
2001 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2002 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2003 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2004 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2005
2006 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2007 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2008 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2009 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2010 }
2011
2012 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2013 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2014 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2015 }
2016 }
2017
2018 /* socclk */
2019 dpm_table = &(data->dpm_table.soc_table);
2020 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2021 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2022 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2023 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2024
2025 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2026 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2027 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2028 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2029 }
2030
2031 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2032 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2033 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2034 }
2035 }
2036
2037 /* eclk */
2038 dpm_table = &(data->dpm_table.eclk_table);
2039 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2040 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2041 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2042 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2043
2044 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2045 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2046 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2047 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2048 }
2049
2050 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2051 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2052 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2053 }
2054 }
2055
2056 return 0;
2057 }
2058
2059 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2060 struct vega12_single_dpm_table *dpm_table)
2061 {
2062 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2063 int ret = 0;
2064
2065 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2066 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2067 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2068 return -EINVAL);
2069 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2070 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2071 return -EINVAL);
2072
2073 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2074 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2075 PPSMC_MSG_SetHardMinByFreq,
2076 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2077 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2078 return ret);
2079 }
2080
2081 return ret;
2082 }
2083
2084 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2085 {
2086 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2087 int ret = 0;
2088
2089 smum_send_msg_to_smc_with_parameter(hwmgr,
2090 PPSMC_MSG_NumOfDisplays, 0);
2091
2092 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2093 &data->dpm_table.mem_table);
2094
2095 return ret;
2096 }
2097
2098 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2099 {
2100 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2101 int result = 0;
2102 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2103
2104 if ((data->water_marks_bitmap & WaterMarksExist) &&
2105 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2106 result = vega12_copy_table_to_smc(hwmgr,
2107 (uint8_t *)wm_table, TABLE_WATERMARKS);
2108 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
2109 data->water_marks_bitmap |= WaterMarksLoaded;
2110 }
2111
2112 if ((data->water_marks_bitmap & WaterMarksExist) &&
2113 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2114 data->smu_features[GNLD_DPM_SOCCLK].supported)
2115 smum_send_msg_to_smc_with_parameter(hwmgr,
2116 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
2117
2118 return result;
2119 }
2120
2121 int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2122 {
2123 struct vega12_hwmgr *data =
2124 (struct vega12_hwmgr *)(hwmgr->backend);
2125
2126 if (data->smu_features[GNLD_DPM_UVD].supported) {
2127 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2128 enable,
2129 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2130 "Attempt to Enable/Disable DPM UVD Failed!",
2131 return -1);
2132 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2133 }
2134
2135 return 0;
2136 }
2137
2138 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2139 {
2140 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2141
2142 if (data->vce_power_gated == bgate)
2143 return;
2144
2145 data->vce_power_gated = bgate;
2146 vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2147 }
2148
2149 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2150 {
2151 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2152
2153 if (data->uvd_power_gated == bgate)
2154 return;
2155
2156 data->uvd_power_gated = bgate;
2157 vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2158 }
2159
2160 static bool
2161 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2162 {
2163 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2164 bool is_update_required = false;
2165
2166 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2167 is_update_required = true;
2168
2169 if (data->registry_data.gfx_clk_deep_sleep_support) {
2170 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2171 is_update_required = true;
2172 }
2173
2174 return is_update_required;
2175 }
2176
2177 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2178 {
2179 int tmp_result, result = 0;
2180
2181 tmp_result = vega12_disable_all_smu_features(hwmgr);
2182 PP_ASSERT_WITH_CODE((tmp_result == 0),
2183 "Failed to disable all smu features!", result = tmp_result);
2184
2185 return result;
2186 }
2187
2188 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2189 {
2190 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2191 int result;
2192
2193 result = vega12_disable_dpm_tasks(hwmgr);
2194 PP_ASSERT_WITH_CODE((0 == result),
2195 "[disable_dpm_tasks] Failed to disable DPM!",
2196 );
2197 data->water_marks_bitmap &= ~(WaterMarksLoaded);
2198
2199 return result;
2200 }
2201
2202 #if 0
2203 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2204 uint32_t *sclk_idx, uint32_t *mclk_idx,
2205 uint32_t min_sclk, uint32_t min_mclk)
2206 {
2207 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2208 struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2209 uint32_t i;
2210
2211 for (i = 0; i < dpm_table->gfx_table.count; i++) {
2212 if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2213 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2214 *sclk_idx = i;
2215 break;
2216 }
2217 }
2218
2219 for (i = 0; i < dpm_table->mem_table.count; i++) {
2220 if (dpm_table->mem_table.dpm_levels[i].enabled &&
2221 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2222 *mclk_idx = i;
2223 break;
2224 }
2225 }
2226 }
2227 #endif
2228
2229 #if 0
2230 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2231 struct amd_pp_profile *request)
2232 {
2233 return 0;
2234 }
2235
2236 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2237 {
2238 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2239 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2240 struct vega12_single_dpm_table *golden_sclk_table =
2241 &(data->golden_dpm_table.gfx_table);
2242 int value;
2243
2244 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
2245 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
2246 100 /
2247 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
2248
2249 return value;
2250 }
2251
2252 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2253 {
2254 return 0;
2255 }
2256
2257 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2258 {
2259 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2260 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2261 struct vega12_single_dpm_table *golden_mclk_table =
2262 &(data->golden_dpm_table.mem_table);
2263 int value;
2264
2265 value = (mclk_table->dpm_levels
2266 [mclk_table->count - 1].value -
2267 golden_mclk_table->dpm_levels
2268 [golden_mclk_table->count - 1].value) *
2269 100 /
2270 golden_mclk_table->dpm_levels
2271 [golden_mclk_table->count - 1].value;
2272
2273 return value;
2274 }
2275
2276 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2277 {
2278 return 0;
2279 }
2280 #endif
2281
2282 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2283 uint32_t virtual_addr_low,
2284 uint32_t virtual_addr_hi,
2285 uint32_t mc_addr_low,
2286 uint32_t mc_addr_hi,
2287 uint32_t size)
2288 {
2289 smum_send_msg_to_smc_with_parameter(hwmgr,
2290 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2291 virtual_addr_hi);
2292 smum_send_msg_to_smc_with_parameter(hwmgr,
2293 PPSMC_MSG_SetSystemVirtualDramAddrLow,
2294 virtual_addr_low);
2295 smum_send_msg_to_smc_with_parameter(hwmgr,
2296 PPSMC_MSG_DramLogSetDramAddrHigh,
2297 mc_addr_hi);
2298
2299 smum_send_msg_to_smc_with_parameter(hwmgr,
2300 PPSMC_MSG_DramLogSetDramAddrLow,
2301 mc_addr_low);
2302
2303 smum_send_msg_to_smc_with_parameter(hwmgr,
2304 PPSMC_MSG_DramLogSetDramSize,
2305 size);
2306 return 0;
2307 }
2308
2309 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2310 struct PP_TemperatureRange *thermal_data)
2311 {
2312 struct phm_ppt_v3_information *pptable_information =
2313 (struct phm_ppt_v3_information *)hwmgr->pptable;
2314
2315 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2316
2317 thermal_data->max = pptable_information->us_software_shutdown_temp *
2318 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2319
2320 return 0;
2321 }
2322
2323 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2324 {
2325 struct vega12_hwmgr *data =
2326 (struct vega12_hwmgr *)(hwmgr->backend);
2327 int ret = 0;
2328
2329 if (data->gfxoff_controlled_by_driver)
2330 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
2331
2332 return ret;
2333 }
2334
2335 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2336 {
2337 struct vega12_hwmgr *data =
2338 (struct vega12_hwmgr *)(hwmgr->backend);
2339 int ret = 0;
2340
2341 if (data->gfxoff_controlled_by_driver)
2342 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
2343
2344 return ret;
2345 }
2346
2347 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2348 {
2349 if (enable)
2350 return vega12_enable_gfx_off(hwmgr);
2351 else
2352 return vega12_disable_gfx_off(hwmgr);
2353 }
2354
2355 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2356 .backend_init = vega12_hwmgr_backend_init,
2357 .backend_fini = vega12_hwmgr_backend_fini,
2358 .asic_setup = vega12_setup_asic_task,
2359 .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2360 .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2361 .patch_boot_state = vega12_patch_boot_state,
2362 .get_sclk = vega12_dpm_get_sclk,
2363 .get_mclk = vega12_dpm_get_mclk,
2364 .notify_smc_display_config_after_ps_adjustment =
2365 vega12_notify_smc_display_config_after_ps_adjustment,
2366 .force_dpm_level = vega12_dpm_force_dpm_level,
2367 .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2368 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2369 .reset_fan_speed_to_default =
2370 vega12_fan_ctrl_reset_fan_speed_to_default,
2371 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2372 .set_fan_control_mode = vega12_set_fan_control_mode,
2373 .get_fan_control_mode = vega12_get_fan_control_mode,
2374 .read_sensor = vega12_read_sensor,
2375 .get_dal_power_level = vega12_get_dal_power_level,
2376 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2377 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2378 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2379 .display_clock_voltage_request = vega12_display_clock_voltage_request,
2380 .force_clock_level = vega12_force_clock_level,
2381 .print_clock_levels = vega12_print_clock_levels,
2382 .apply_clocks_adjust_rules =
2383 vega12_apply_clocks_adjust_rules,
2384 .pre_display_config_changed =
2385 vega12_pre_display_configuration_changed_task,
2386 .display_config_changed = vega12_display_configuration_changed_task,
2387 .powergate_uvd = vega12_power_gate_uvd,
2388 .powergate_vce = vega12_power_gate_vce,
2389 .check_smc_update_required_for_display_configuration =
2390 vega12_check_smc_update_required_for_display_configuration,
2391 .power_off_asic = vega12_power_off_asic,
2392 .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2393 #if 0
2394 .set_power_profile_state = vega12_set_power_profile_state,
2395 .get_sclk_od = vega12_get_sclk_od,
2396 .set_sclk_od = vega12_set_sclk_od,
2397 .get_mclk_od = vega12_get_mclk_od,
2398 .set_mclk_od = vega12_set_mclk_od,
2399 #endif
2400 .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2401 .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2402 .register_irq_handlers = smu9_register_irq_handlers,
2403 .start_thermal_controller = vega12_start_thermal_controller,
2404 .powergate_gfx = vega12_gfx_off_control,
2405 };
2406
2407 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2408 {
2409 hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2410 hwmgr->pptable_func = &vega12_pptable_funcs;
2411
2412 return 0;
2413 }
Linux with added FPC-III support