drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "smumgr.h"
  25 #include "vega10_inc.h"
  26 #include "soc15_common.h"
  27 #include "pp_debug.h"
  28
  29
  30 /* MP Apertures */
  31 #define MP0_Public                  0x03800000
  32 #define MP0_SRAM                    0x03900000
  33 #define MP1_Public                  0x03b00000
  34 #define MP1_SRAM                    0x03c00004
  35
  36 #define smnMP1_FIRMWARE_FLAGS                                                                           0x3010028
  37
  38 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr)
  39 {
  40         struct amdgpu_device *adev = hwmgr->adev;
  41         uint32_t mp1_fw_flags;
  42
  43         WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
  44                         (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
  45
  46         mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
  47
  48         if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
  49                 return true;
  50
  51         return false;
  52 }
  53
  54 /*
  55  * Check if SMC has responded to previous message.
  56  *
  57  * @param    smumgr  the address of the powerplay hardware manager.
  58  * @return   TRUE    SMC has responded, FALSE otherwise.
  59  */
  60 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)
  61 {
  62         struct amdgpu_device *adev = hwmgr->adev;
  63         uint32_t reg;
  64         uint32_t ret;
  65
  66         reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
  67
  68         ret = phm_wait_for_register_unequal(hwmgr, reg,
  69                         0, MP1_C2PMSG_90__CONTENT_MASK);
  70
  71         if (ret)
  72                 pr_err("No response from smu\n");
  73
  74         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  75 }
  76
  77 /*
  78  * Send a message to the SMC, and do not wait for its response.
  79  * @param    smumgr  the address of the powerplay hardware manager.
  80  * @param    msg the message to send.
  81  * @return   Always return 0.
  82  */
  83 static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  84                                                 uint16_t msg)
  85 {
  86         struct amdgpu_device *adev = hwmgr->adev;
  87
  88         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  89
  90         return 0;
  91 }
  92
  93 /*
  94  * Send a message to the SMC, and wait for its response.
  95  * @param    hwmgr  the address of the powerplay hardware manager.
  96  * @param    msg the message to send.
  97  * @return   Always return 0.
  98  */
  99 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
 100 {
 101         struct amdgpu_device *adev = hwmgr->adev;
 102         uint32_t ret;
 103
 104         smu9_wait_for_response(hwmgr);
 105
 106         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 107
 108         smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
 109
 110         ret = smu9_wait_for_response(hwmgr);
 111         if (ret != 1)
 112                 pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret);
 113
 114         return 0;
 115 }
 116
 117 /*
 118  * Send a message to the SMC with parameter
 119  * @param    hwmgr:  the address of the powerplay hardware manager.
 120  * @param    msg: the message to send.
 121  * @param    parameter: the parameter to send
 122  * @return   Always return 0.
 123  */
 124 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
 125                                         uint16_t msg, uint32_t parameter)
 126 {
 127         struct amdgpu_device *adev = hwmgr->adev;
 128         uint32_t ret;
 129
 130         smu9_wait_for_response(hwmgr);
 131
 132         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 133
 134         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 135
 136         smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
 137
 138         ret = smu9_wait_for_response(hwmgr);
 139         if (ret != 1)
 140                 pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret);
 141
 142         return 0;
 143 }
 144
 145 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)
 146 {
 147         struct amdgpu_device *adev = hwmgr->adev;
 148
 149         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 150 }