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drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / gma500 / psb_intel_sdvo.c
blobdd3cec0e3190c835e04c8313410b8bfc88c8eb32
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/module.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "psb_intel_drv.h"
36 #include <drm/gma_drm.h>
37 #include "psb_drv.h"
38 #include "psb_intel_sdvo_regs.h"
39 #include "psb_intel_reg.h"
40 #include <linux/kernel.h>
41
42 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
43 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
44 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
45 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
46
47 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
48 SDVO_TV_MASK)
49
50 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
51 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
52 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
53 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
54
55
56 static const char *tv_format_names[] = {
57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64 };
65
66 struct psb_intel_sdvo {
67 struct gma_encoder base;
68
69 struct i2c_adapter *i2c;
70 u8 slave_addr;
71
72 struct i2c_adapter ddc;
73
74 /* Register for the SDVO device: SDVOB or SDVOC */
75 int sdvo_reg;
76
77 /* Active outputs controlled by this SDVO output */
78 uint16_t controlled_output;
79
80 /*
81 * Capabilities of the SDVO device returned by
82 * i830_sdvo_get_capabilities()
83 */
84 struct psb_intel_sdvo_caps caps;
85
86 /* Pixel clock limitations reported by the SDVO device, in kHz */
87 int pixel_clock_min, pixel_clock_max;
88
89 /*
90 * For multiple function SDVO device,
91 * this is for current attached outputs.
92 */
93 uint16_t attached_output;
94
95 /**
96 * This is used to select the color range of RBG outputs in HDMI mode.
97 * It is only valid when using TMDS encoding and 8 bit per color mode.
98 */
99 uint32_t color_range;
100
101 /**
102 * This is set if we're going to treat the device as TV-out.
103 *
104 * While we have these nice friendly flags for output types that ought
105 * to decide this for us, the S-Video output on our HDMI+S-Video card
106 * shows up as RGB1 (VGA).
107 */
108 bool is_tv;
109
110 /* This is for current tv format name */
111 int tv_format_index;
112
113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
119
120 /**
121 * This is set if we detect output of sdvo device as LVDS and
122 * have a valid fixed mode to use with the panel.
123 */
124 bool is_lvds;
125
126 /**
127 * This is sdvo fixed pannel mode pointer
128 */
129 struct drm_display_mode *sdvo_lvds_fixed_mode;
130
131 /* DDC bus used by this SDVO encoder */
132 uint8_t ddc_bus;
133
134 /* Input timings for adjusted_mode */
135 struct psb_intel_sdvo_dtd input_dtd;
136
137 /* Saved SDVO output states */
138 uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */
139 };
140
141 struct psb_intel_sdvo_connector {
142 struct gma_connector base;
143
144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 int force_audio;
148
149 /* This contains all current supported TV format */
150 u8 tv_format_supported[ARRAY_SIZE(tv_format_names)];
151 int format_supported_num;
152 struct drm_property *tv_format;
153
154 /* add the property for the SDVO-TV */
155 struct drm_property *left;
156 struct drm_property *right;
157 struct drm_property *top;
158 struct drm_property *bottom;
159 struct drm_property *hpos;
160 struct drm_property *vpos;
161 struct drm_property *contrast;
162 struct drm_property *saturation;
163 struct drm_property *hue;
164 struct drm_property *sharpness;
165 struct drm_property *flicker_filter;
166 struct drm_property *flicker_filter_adaptive;
167 struct drm_property *flicker_filter_2d;
168 struct drm_property *tv_chroma_filter;
169 struct drm_property *tv_luma_filter;
170 struct drm_property *dot_crawl;
171
172 /* add the property for the SDVO-TV/LVDS */
173 struct drm_property *brightness;
174
175 /* Add variable to record current setting for the above property */
176 u32 left_margin, right_margin, top_margin, bottom_margin;
177
178 /* this is to get the range of margin.*/
179 u32 max_hscan, max_vscan;
180 u32 max_hpos, cur_hpos;
181 u32 max_vpos, cur_vpos;
182 u32 cur_brightness, max_brightness;
183 u32 cur_contrast, max_contrast;
184 u32 cur_saturation, max_saturation;
185 u32 cur_hue, max_hue;
186 u32 cur_sharpness, max_sharpness;
187 u32 cur_flicker_filter, max_flicker_filter;
188 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
189 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
190 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
191 u32 cur_tv_luma_filter, max_tv_luma_filter;
192 u32 cur_dot_crawl, max_dot_crawl;
193 };
194
195 static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
196 {
197 return container_of(encoder, struct psb_intel_sdvo, base.base);
198 }
199
200 static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
201 {
202 return container_of(gma_attached_encoder(connector),
203 struct psb_intel_sdvo, base);
204 }
205
206 static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
207 {
208 return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base);
209 }
210
211 static bool
212 psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
213 static bool
214 psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
215 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
216 int type);
217 static bool
218 psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
219 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
220
221 /**
222 * Writes the SDVOB or SDVOC with the given value, but always writes both
223 * SDVOB and SDVOC to work around apparent hardware issues (according to
224 * comments in the BIOS).
225 */
226 static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
227 {
228 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
229 u32 bval = val, cval = val;
230 int i, j;
231 int need_aux = IS_MRST(dev) ? 1 : 0;
232
233 for (j = 0; j <= need_aux; j++) {
234 if (psb_intel_sdvo->sdvo_reg == SDVOB)
235 cval = REG_READ_WITH_AUX(SDVOC, j);
236 else
237 bval = REG_READ_WITH_AUX(SDVOB, j);
238
239 /*
240 * Write the registers twice for luck. Sometimes,
241 * writing them only once doesn't appear to 'stick'.
242 * The BIOS does this too. Yay, magic
243 */
244 for (i = 0; i < 2; i++) {
245 REG_WRITE_WITH_AUX(SDVOB, bval, j);
246 REG_READ_WITH_AUX(SDVOB, j);
247 REG_WRITE_WITH_AUX(SDVOC, cval, j);
248 REG_READ_WITH_AUX(SDVOC, j);
249 }
250 }
251 }
252
253 static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
254 {
255 struct i2c_msg msgs[] = {
256 {
257 .addr = psb_intel_sdvo->slave_addr,
258 .flags = 0,
259 .len = 1,
260 .buf = &addr,
261 },
262 {
263 .addr = psb_intel_sdvo->slave_addr,
264 .flags = I2C_M_RD,
265 .len = 1,
266 .buf = ch,
267 }
268 };
269 int ret;
270
271 if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
272 return true;
273
274 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
275 return false;
276 }
277
278 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
279 /** Mapping of command numbers to names, for debug output */
280 static const struct _sdvo_cmd_name {
281 u8 cmd;
282 const char *name;
283 } sdvo_cmd_names[] = {
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
327
328 /* Add the op code for SDVO enhancements */
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
373
374 /* HDMI op code */
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
395 };
396
397 #define IS_SDVOB(reg) (reg == SDVOB)
398 #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
399
400 static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
401 const void *args, int args_len)
402 {
403 int i;
404
405 DRM_DEBUG_KMS("%s: W: %02X ",
406 SDVO_NAME(psb_intel_sdvo), cmd);
407 for (i = 0; i < args_len; i++)
408 DRM_DEBUG_KMS("%02X ", ((u8 *)args)[i]);
409 for (; i < 8; i++)
410 DRM_DEBUG_KMS(" ");
411 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
412 if (cmd == sdvo_cmd_names[i].cmd) {
413 DRM_DEBUG_KMS("(%s)", sdvo_cmd_names[i].name);
414 break;
415 }
416 }
417 if (i == ARRAY_SIZE(sdvo_cmd_names))
418 DRM_DEBUG_KMS("(%02X)", cmd);
419 DRM_DEBUG_KMS("\n");
420 }
421
422 static const char *cmd_status_names[] = {
423 "Power on",
424 "Success",
425 "Not supported",
426 "Invalid arg",
427 "Pending",
428 "Target not specified",
429 "Scaling not supported"
430 };
431
432 #define MAX_ARG_LEN 32
433
434 static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
435 const void *args, int args_len)
436 {
437 u8 buf[MAX_ARG_LEN*2 + 2], status;
438 struct i2c_msg msgs[MAX_ARG_LEN + 3];
439 int i, ret;
440
441 if (args_len > MAX_ARG_LEN) {
442 DRM_ERROR("Need to increase arg length\n");
443 return false;
444 }
445
446 psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
447
448 for (i = 0; i < args_len; i++) {
449 msgs[i].addr = psb_intel_sdvo->slave_addr;
450 msgs[i].flags = 0;
451 msgs[i].len = 2;
452 msgs[i].buf = buf + 2 *i;
453 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
454 buf[2*i + 1] = ((u8*)args)[i];
455 }
456 msgs[i].addr = psb_intel_sdvo->slave_addr;
457 msgs[i].flags = 0;
458 msgs[i].len = 2;
459 msgs[i].buf = buf + 2*i;
460 buf[2*i + 0] = SDVO_I2C_OPCODE;
461 buf[2*i + 1] = cmd;
462
463 /* the following two are to read the response */
464 status = SDVO_I2C_CMD_STATUS;
465 msgs[i+1].addr = psb_intel_sdvo->slave_addr;
466 msgs[i+1].flags = 0;
467 msgs[i+1].len = 1;
468 msgs[i+1].buf = &status;
469
470 msgs[i+2].addr = psb_intel_sdvo->slave_addr;
471 msgs[i+2].flags = I2C_M_RD;
472 msgs[i+2].len = 1;
473 msgs[i+2].buf = &status;
474
475 ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
476 if (ret < 0) {
477 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
478 return false;
479 }
480 if (ret != i+3) {
481 /* failure in I2C transfer */
482 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
483 return false;
484 }
485
486 return true;
487 }
488
489 static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
490 void *response, int response_len)
491 {
492 u8 retry = 5;
493 u8 status;
494 int i;
495
496 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
497
498 /*
499 * The documentation states that all commands will be
500 * processed within 15µs, and that we need only poll
501 * the status byte a maximum of 3 times in order for the
502 * command to be complete.
503 *
504 * Check 5 times in case the hardware failed to read the docs.
505 */
506 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
507 SDVO_I2C_CMD_STATUS,
508 &status))
509 goto log_fail;
510
511 while ((status == SDVO_CMD_STATUS_PENDING ||
512 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) {
513 udelay(15);
514 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
515 SDVO_I2C_CMD_STATUS,
516 &status))
517 goto log_fail;
518 }
519
520 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
521 DRM_DEBUG_KMS("(%s)", cmd_status_names[status]);
522 else
523 DRM_DEBUG_KMS("(??? %d)", status);
524
525 if (status != SDVO_CMD_STATUS_SUCCESS)
526 goto log_fail;
527
528 /* Read the command response */
529 for (i = 0; i < response_len; i++) {
530 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
531 SDVO_I2C_RETURN_0 + i,
532 &((u8 *)response)[i]))
533 goto log_fail;
534 DRM_DEBUG_KMS(" %02X", ((u8 *)response)[i]);
535 }
536 DRM_DEBUG_KMS("\n");
537 return true;
538
539 log_fail:
540 DRM_DEBUG_KMS("... failed\n");
541 return false;
542 }
543
544 static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
545 {
546 if (mode->clock >= 100000)
547 return 1;
548 else if (mode->clock >= 50000)
549 return 2;
550 else
551 return 4;
552 }
553
554 static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
555 u8 ddc_bus)
556 {
557 /* This must be the immediately preceding write before the i2c xfer */
558 return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
559 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
560 &ddc_bus, 1);
561 }
562
563 static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
564 {
565 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
566 return false;
567
568 return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
569 }
570
571 static bool
572 psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
573 {
574 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
575 return false;
576
577 return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
578 }
579
580 static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
581 {
582 struct psb_intel_sdvo_set_target_input_args targets = {0};
583 return psb_intel_sdvo_set_value(psb_intel_sdvo,
584 SDVO_CMD_SET_TARGET_INPUT,
585 &targets, sizeof(targets));
586 }
587
588 /**
589 * Return whether each input is trained.
590 *
591 * This function is making an assumption about the layout of the response,
592 * which should be checked against the docs.
593 */
594 static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
595 {
596 struct psb_intel_sdvo_get_trained_inputs_response response;
597
598 BUILD_BUG_ON(sizeof(response) != 1);
599 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
600 &response, sizeof(response)))
601 return false;
602
603 *input_1 = response.input0_trained;
604 *input_2 = response.input1_trained;
605 return true;
606 }
607
608 static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
609 u16 outputs)
610 {
611 return psb_intel_sdvo_set_value(psb_intel_sdvo,
612 SDVO_CMD_SET_ACTIVE_OUTPUTS,
613 &outputs, sizeof(outputs));
614 }
615
616 static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
617 int mode)
618 {
619 u8 state = SDVO_ENCODER_STATE_ON;
620
621 switch (mode) {
622 case DRM_MODE_DPMS_ON:
623 state = SDVO_ENCODER_STATE_ON;
624 break;
625 case DRM_MODE_DPMS_STANDBY:
626 state = SDVO_ENCODER_STATE_STANDBY;
627 break;
628 case DRM_MODE_DPMS_SUSPEND:
629 state = SDVO_ENCODER_STATE_SUSPEND;
630 break;
631 case DRM_MODE_DPMS_OFF:
632 state = SDVO_ENCODER_STATE_OFF;
633 break;
634 }
635
636 return psb_intel_sdvo_set_value(psb_intel_sdvo,
637 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
638 }
639
640 static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
641 int *clock_min,
642 int *clock_max)
643 {
644 struct psb_intel_sdvo_pixel_clock_range clocks;
645
646 BUILD_BUG_ON(sizeof(clocks) != 4);
647 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
648 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
649 &clocks, sizeof(clocks)))
650 return false;
651
652 /* Convert the values from units of 10 kHz to kHz. */
653 *clock_min = clocks.min * 10;
654 *clock_max = clocks.max * 10;
655 return true;
656 }
657
658 static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
659 u16 outputs)
660 {
661 return psb_intel_sdvo_set_value(psb_intel_sdvo,
662 SDVO_CMD_SET_TARGET_OUTPUT,
663 &outputs, sizeof(outputs));
664 }
665
666 static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
667 struct psb_intel_sdvo_dtd *dtd)
668 {
669 return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
670 psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
671 }
672
673 static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
674 struct psb_intel_sdvo_dtd *dtd)
675 {
676 return psb_intel_sdvo_set_timing(psb_intel_sdvo,
677 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
678 }
679
680 static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
681 struct psb_intel_sdvo_dtd *dtd)
682 {
683 return psb_intel_sdvo_set_timing(psb_intel_sdvo,
684 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
685 }
686
687 static bool
688 psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
689 uint16_t clock,
690 uint16_t width,
691 uint16_t height)
692 {
693 struct psb_intel_sdvo_preferred_input_timing_args args;
694
695 memset(&args, 0, sizeof(args));
696 args.clock = clock;
697 args.width = width;
698 args.height = height;
699 args.interlace = 0;
700
701 if (psb_intel_sdvo->is_lvds &&
702 (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
703 psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
704 args.scaled = 1;
705
706 return psb_intel_sdvo_set_value(psb_intel_sdvo,
707 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
708 &args, sizeof(args));
709 }
710
711 static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
712 struct psb_intel_sdvo_dtd *dtd)
713 {
714 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
715 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
716 return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
717 &dtd->part1, sizeof(dtd->part1)) &&
718 psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
719 &dtd->part2, sizeof(dtd->part2));
720 }
721
722 static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
723 {
724 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
725 }
726
727 static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
728 const struct drm_display_mode *mode)
729 {
730 uint16_t width, height;
731 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
732 uint16_t h_sync_offset, v_sync_offset;
733
734 width = mode->crtc_hdisplay;
735 height = mode->crtc_vdisplay;
736
737 /* do some mode translations */
738 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
739 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
740
741 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
742 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
743
744 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
745 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
746
747 dtd->part1.clock = mode->clock / 10;
748 dtd->part1.h_active = width & 0xff;
749 dtd->part1.h_blank = h_blank_len & 0xff;
750 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
751 ((h_blank_len >> 8) & 0xf);
752 dtd->part1.v_active = height & 0xff;
753 dtd->part1.v_blank = v_blank_len & 0xff;
754 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
755 ((v_blank_len >> 8) & 0xf);
756
757 dtd->part2.h_sync_off = h_sync_offset & 0xff;
758 dtd->part2.h_sync_width = h_sync_len & 0xff;
759 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
760 (v_sync_len & 0xf);
761 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
762 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
763 ((v_sync_len & 0x30) >> 4);
764
765 dtd->part2.dtd_flags = 0x18;
766 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
767 dtd->part2.dtd_flags |= 0x2;
768 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
769 dtd->part2.dtd_flags |= 0x4;
770
771 dtd->part2.sdvo_flags = 0;
772 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
773 dtd->part2.reserved = 0;
774 }
775
776 static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
777 const struct psb_intel_sdvo_dtd *dtd)
778 {
779 mode->hdisplay = dtd->part1.h_active;
780 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
781 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
782 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
783 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
784 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
785 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
786 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
787
788 mode->vdisplay = dtd->part1.v_active;
789 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
790 mode->vsync_start = mode->vdisplay;
791 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
792 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
793 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
794 mode->vsync_end = mode->vsync_start +
795 (dtd->part2.v_sync_off_width & 0xf);
796 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
797 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
798 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
799
800 mode->clock = dtd->part1.clock * 10;
801
802 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
803 if (dtd->part2.dtd_flags & 0x2)
804 mode->flags |= DRM_MODE_FLAG_PHSYNC;
805 if (dtd->part2.dtd_flags & 0x4)
806 mode->flags |= DRM_MODE_FLAG_PVSYNC;
807 }
808
809 static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
810 {
811 struct psb_intel_sdvo_encode encode;
812
813 BUILD_BUG_ON(sizeof(encode) != 2);
814 return psb_intel_sdvo_get_value(psb_intel_sdvo,
815 SDVO_CMD_GET_SUPP_ENCODE,
816 &encode, sizeof(encode));
817 }
818
819 static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
820 uint8_t mode)
821 {
822 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
823 }
824
825 static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
826 uint8_t mode)
827 {
828 return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
829 }
830
831 #if 0
832 static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
833 {
834 int i, j;
835 uint8_t set_buf_index[2];
836 uint8_t av_split;
837 uint8_t buf_size;
838 uint8_t buf[48];
839 uint8_t *pos;
840
841 psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
842
843 for (i = 0; i <= av_split; i++) {
844 set_buf_index[0] = i; set_buf_index[1] = 0;
845 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
846 set_buf_index, 2);
847 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
848 psb_intel_sdvo_read_response(encoder, &buf_size, 1);
849
850 pos = buf;
851 for (j = 0; j <= buf_size; j += 8) {
852 psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
853 NULL, 0);
854 psb_intel_sdvo_read_response(encoder, pos, 8);
855 pos += 8;
856 }
857 }
858 }
859 #endif
860
861 static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
862 {
863 DRM_INFO("HDMI is not supported yet");
864
865 return false;
866 #if 0
867 struct dip_infoframe avi_if = {
868 .type = DIP_TYPE_AVI,
869 .ver = DIP_VERSION_AVI,
870 .len = DIP_LEN_AVI,
871 };
872 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
873 uint8_t set_buf_index[2] = { 1, 0 };
874 uint64_t *data = (uint64_t *)&avi_if;
875 unsigned i;
876
877 intel_dip_infoframe_csum(&avi_if);
878
879 if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
880 SDVO_CMD_SET_HBUF_INDEX,
881 set_buf_index, 2))
882 return false;
883
884 for (i = 0; i < sizeof(avi_if); i += 8) {
885 if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
886 SDVO_CMD_SET_HBUF_DATA,
887 data, 8))
888 return false;
889 data++;
890 }
891
892 return psb_intel_sdvo_set_value(psb_intel_sdvo,
893 SDVO_CMD_SET_HBUF_TXRATE,
894 &tx_rate, 1);
895 #endif
896 }
897
898 static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
899 {
900 struct psb_intel_sdvo_tv_format format;
901 uint32_t format_map;
902
903 format_map = 1 << psb_intel_sdvo->tv_format_index;
904 memset(&format, 0, sizeof(format));
905 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
906
907 BUILD_BUG_ON(sizeof(format) != 6);
908 return psb_intel_sdvo_set_value(psb_intel_sdvo,
909 SDVO_CMD_SET_TV_FORMAT,
910 &format, sizeof(format));
911 }
912
913 static bool
914 psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
915 const struct drm_display_mode *mode)
916 {
917 struct psb_intel_sdvo_dtd output_dtd;
918
919 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
920 psb_intel_sdvo->attached_output))
921 return false;
922
923 psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
924 if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
925 return false;
926
927 return true;
928 }
929
930 static bool
931 psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
932 const struct drm_display_mode *mode,
933 struct drm_display_mode *adjusted_mode)
934 {
935 /* Reset the input timing to the screen. Assume always input 0. */
936 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
937 return false;
938
939 if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
940 mode->clock / 10,
941 mode->hdisplay,
942 mode->vdisplay))
943 return false;
944
945 if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
946 &psb_intel_sdvo->input_dtd))
947 return false;
948
949 psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
950
951 drm_mode_set_crtcinfo(adjusted_mode, 0);
952 return true;
953 }
954
955 static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
956 const struct drm_display_mode *mode,
957 struct drm_display_mode *adjusted_mode)
958 {
959 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
960 int multiplier;
961
962 /* We need to construct preferred input timings based on our
963 * output timings. To do that, we have to set the output
964 * timings, even though this isn't really the right place in
965 * the sequence to do it. Oh well.
966 */
967 if (psb_intel_sdvo->is_tv) {
968 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
969 return false;
970
971 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
972 mode,
973 adjusted_mode);
974 } else if (psb_intel_sdvo->is_lvds) {
975 if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
976 psb_intel_sdvo->sdvo_lvds_fixed_mode))
977 return false;
978
979 (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
980 mode,
981 adjusted_mode);
982 }
983
984 /* Make the CRTC code factor in the SDVO pixel multiplier. The
985 * SDVO device will factor out the multiplier during mode_set.
986 */
987 multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
988 psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
989
990 return true;
991 }
992
993 static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
994 struct drm_display_mode *mode,
995 struct drm_display_mode *adjusted_mode)
996 {
997 struct drm_device *dev = encoder->dev;
998 struct drm_crtc *crtc = encoder->crtc;
999 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
1000 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
1001 u32 sdvox;
1002 struct psb_intel_sdvo_in_out_map in_out;
1003 struct psb_intel_sdvo_dtd input_dtd;
1004 int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
1005 int rate;
1006 int need_aux = IS_MRST(dev) ? 1 : 0;
1007
1008 if (!mode)
1009 return;
1010
1011 /* First, set the input mapping for the first input to our controlled
1012 * output. This is only correct if we're a single-input device, in
1013 * which case the first input is the output from the appropriate SDVO
1014 * channel on the motherboard. In a two-input device, the first input
1015 * will be SDVOB and the second SDVOC.
1016 */
1017 in_out.in0 = psb_intel_sdvo->attached_output;
1018 in_out.in1 = 0;
1019
1020 psb_intel_sdvo_set_value(psb_intel_sdvo,
1021 SDVO_CMD_SET_IN_OUT_MAP,
1022 &in_out, sizeof(in_out));
1023
1024 /* Set the output timings to the screen */
1025 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
1026 psb_intel_sdvo->attached_output))
1027 return;
1028
1029 /* We have tried to get input timing in mode_fixup, and filled into
1030 * adjusted_mode.
1031 */
1032 if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
1033 input_dtd = psb_intel_sdvo->input_dtd;
1034 } else {
1035 /* Set the output timing to the screen */
1036 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
1037 psb_intel_sdvo->attached_output))
1038 return;
1039
1040 psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1041 (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
1042 }
1043
1044 /* Set the input timing to the screen. Assume always input 0. */
1045 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
1046 return;
1047
1048 if (psb_intel_sdvo->has_hdmi_monitor) {
1049 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
1050 psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
1051 SDVO_COLORIMETRY_RGB256);
1052 psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
1053 } else
1054 psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
1055
1056 if (psb_intel_sdvo->is_tv &&
1057 !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
1058 return;
1059
1060 (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
1061
1062 switch (pixel_multiplier) {
1063 default:
1064 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1065 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1066 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1067 }
1068 if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
1069 return;
1070
1071 /* Set the SDVO control regs. */
1072 if (need_aux)
1073 sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
1074 else
1075 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
1076
1077 switch (psb_intel_sdvo->sdvo_reg) {
1078 case SDVOB:
1079 sdvox &= SDVOB_PRESERVE_MASK;
1080 break;
1081 case SDVOC:
1082 sdvox &= SDVOC_PRESERVE_MASK;
1083 break;
1084 }
1085 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1086
1087 if (gma_crtc->pipe == 1)
1088 sdvox |= SDVO_PIPE_B_SELECT;
1089 if (psb_intel_sdvo->has_hdmi_audio)
1090 sdvox |= SDVO_AUDIO_ENABLE;
1091
1092 /* FIXME: Check if this is needed for PSB
1093 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1094 */
1095
1096 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
1097 sdvox |= SDVO_STALL_SELECT;
1098 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
1099 }
1100
1101 static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1102 {
1103 struct drm_device *dev = encoder->dev;
1104 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
1105 u32 temp;
1106 int i;
1107 int need_aux = IS_MRST(dev) ? 1 : 0;
1108
1109 switch (mode) {
1110 case DRM_MODE_DPMS_ON:
1111 DRM_DEBUG("DPMS_ON");
1112 break;
1113 case DRM_MODE_DPMS_OFF:
1114 DRM_DEBUG("DPMS_OFF");
1115 break;
1116 default:
1117 DRM_DEBUG("DPMS: %d", mode);
1118 }
1119
1120 if (mode != DRM_MODE_DPMS_ON) {
1121 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
1122 if (0)
1123 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
1124
1125 if (mode == DRM_MODE_DPMS_OFF) {
1126 if (need_aux)
1127 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
1128 else
1129 temp = REG_READ(psb_intel_sdvo->sdvo_reg);
1130
1131 if ((temp & SDVO_ENABLE) != 0) {
1132 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
1133 }
1134 }
1135 } else {
1136 bool input1, input2;
1137 u8 status;
1138
1139 if (need_aux)
1140 temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
1141 else
1142 temp = REG_READ(psb_intel_sdvo->sdvo_reg);
1143
1144 if ((temp & SDVO_ENABLE) == 0)
1145 psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
1146
1147 for (i = 0; i < 2; i++)
1148 gma_wait_for_vblank(dev);
1149
1150 status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
1151 /* Warn if the device reported failure to sync.
1152 * A lot of SDVO devices fail to notify of sync, but it's
1153 * a given it the status is a success, we succeeded.
1154 */
1155 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1156 DRM_DEBUG_KMS("First %s output reported failure to "
1157 "sync\n", SDVO_NAME(psb_intel_sdvo));
1158 }
1159
1160 if (0)
1161 psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
1162 psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
1163 }
1164 return;
1165 }
1166
1167 static enum drm_mode_status psb_intel_sdvo_mode_valid(struct drm_connector *connector,
1168 struct drm_display_mode *mode)
1169 {
1170 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1171
1172 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1173 return MODE_NO_DBLESCAN;
1174
1175 if (psb_intel_sdvo->pixel_clock_min > mode->clock)
1176 return MODE_CLOCK_LOW;
1177
1178 if (psb_intel_sdvo->pixel_clock_max < mode->clock)
1179 return MODE_CLOCK_HIGH;
1180
1181 if (psb_intel_sdvo->is_lvds) {
1182 if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1183 return MODE_PANEL;
1184
1185 if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1186 return MODE_PANEL;
1187 }
1188
1189 return MODE_OK;
1190 }
1191
1192 static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
1193 {
1194 BUILD_BUG_ON(sizeof(*caps) != 8);
1195 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
1196 SDVO_CMD_GET_DEVICE_CAPS,
1197 caps, sizeof(*caps)))
1198 return false;
1199
1200 DRM_DEBUG_KMS("SDVO capabilities:\n"
1201 " vendor_id: %d\n"
1202 " device_id: %d\n"
1203 " device_rev_id: %d\n"
1204 " sdvo_version_major: %d\n"
1205 " sdvo_version_minor: %d\n"
1206 " sdvo_inputs_mask: %d\n"
1207 " smooth_scaling: %d\n"
1208 " sharp_scaling: %d\n"
1209 " up_scaling: %d\n"
1210 " down_scaling: %d\n"
1211 " stall_support: %d\n"
1212 " output_flags: %d\n",
1213 caps->vendor_id,
1214 caps->device_id,
1215 caps->device_rev_id,
1216 caps->sdvo_version_major,
1217 caps->sdvo_version_minor,
1218 caps->sdvo_inputs_mask,
1219 caps->smooth_scaling,
1220 caps->sharp_scaling,
1221 caps->up_scaling,
1222 caps->down_scaling,
1223 caps->stall_support,
1224 caps->output_flags);
1225
1226 return true;
1227 }
1228
1229 /* No use! */
1230 #if 0
1231 struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
1232 {
1233 struct drm_connector *connector = NULL;
1234 struct psb_intel_sdvo *iout = NULL;
1235 struct psb_intel_sdvo *sdvo;
1236
1237 /* find the sdvo connector */
1238 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1239 iout = to_psb_intel_sdvo(connector);
1240
1241 if (iout->type != INTEL_OUTPUT_SDVO)
1242 continue;
1243
1244 sdvo = iout->dev_priv;
1245
1246 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1247 return connector;
1248
1249 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1250 return connector;
1251
1252 }
1253
1254 return NULL;
1255 }
1256
1257 int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
1258 {
1259 u8 response[2];
1260 u8 status;
1261 struct psb_intel_sdvo *psb_intel_sdvo;
1262 DRM_DEBUG_KMS("\n");
1263
1264 if (!connector)
1265 return 0;
1266
1267 psb_intel_sdvo = to_psb_intel_sdvo(connector);
1268
1269 return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1270 &response, 2) && response[0];
1271 }
1272
1273 void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1274 {
1275 u8 response[2];
1276 u8 status;
1277 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
1278
1279 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1280 psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
1281
1282 if (on) {
1283 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1284 status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
1285
1286 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1287 } else {
1288 response[0] = 0;
1289 response[1] = 0;
1290 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1291 }
1292
1293 psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1294 psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
1295 }
1296 #endif
1297
1298 static bool
1299 psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
1300 {
1301 /* Is there more than one type of output? */
1302 int caps = psb_intel_sdvo->caps.output_flags & 0xf;
1303 return caps & -caps;
1304 }
1305
1306 static struct edid *
1307 psb_intel_sdvo_get_edid(struct drm_connector *connector)
1308 {
1309 struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
1310 return drm_get_edid(connector, &sdvo->ddc);
1311 }
1312
1313 /* Mac mini hack -- use the same DDC as the analog connector */
1314 static struct edid *
1315 psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
1316 {
1317 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1318
1319 return drm_get_edid(connector,
1320 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
1321 }
1322
1323 static enum drm_connector_status
1324 psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1325 {
1326 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1327 enum drm_connector_status status;
1328 struct edid *edid;
1329
1330 edid = psb_intel_sdvo_get_edid(connector);
1331
1332 if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
1333 u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
1334
1335 /*
1336 * Don't use the 1 as the argument of DDC bus switch to get
1337 * the EDID. It is used for SDVO SPD ROM.
1338 */
1339 for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1340 psb_intel_sdvo->ddc_bus = ddc;
1341 edid = psb_intel_sdvo_get_edid(connector);
1342 if (edid)
1343 break;
1344 }
1345 /*
1346 * If we found the EDID on the other bus,
1347 * assume that is the correct DDC bus.
1348 */
1349 if (edid == NULL)
1350 psb_intel_sdvo->ddc_bus = saved_ddc;
1351 }
1352
1353 /*
1354 * When there is no edid and no monitor is connected with VGA
1355 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1356 */
1357 if (edid == NULL)
1358 edid = psb_intel_sdvo_get_analog_edid(connector);
1359
1360 status = connector_status_unknown;
1361 if (edid != NULL) {
1362 /* DDC bus is shared, match EDID to connector type */
1363 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1364 status = connector_status_connected;
1365 if (psb_intel_sdvo->is_hdmi) {
1366 psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1367 psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1368 }
1369 } else
1370 status = connector_status_disconnected;
1371 kfree(edid);
1372 }
1373
1374 if (status == connector_status_connected) {
1375 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1376 if (psb_intel_sdvo_connector->force_audio)
1377 psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
1378 }
1379
1380 return status;
1381 }
1382
1383 static enum drm_connector_status
1384 psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
1385 {
1386 uint16_t response;
1387 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1388 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1389 enum drm_connector_status ret;
1390
1391 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
1392 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1393 return connector_status_unknown;
1394
1395 /* add 30ms delay when the output type might be TV */
1396 if (psb_intel_sdvo->caps.output_flags &
1397 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
1398 mdelay(30);
1399
1400 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
1401 return connector_status_unknown;
1402
1403 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1404 response & 0xff, response >> 8,
1405 psb_intel_sdvo_connector->output_flag);
1406
1407 if (response == 0)
1408 return connector_status_disconnected;
1409
1410 psb_intel_sdvo->attached_output = response;
1411
1412 psb_intel_sdvo->has_hdmi_monitor = false;
1413 psb_intel_sdvo->has_hdmi_audio = false;
1414
1415 if ((psb_intel_sdvo_connector->output_flag & response) == 0)
1416 ret = connector_status_disconnected;
1417 else if (IS_TMDS(psb_intel_sdvo_connector))
1418 ret = psb_intel_sdvo_hdmi_sink_detect(connector);
1419 else {
1420 struct edid *edid;
1421
1422 /* if we have an edid check it matches the connection */
1423 edid = psb_intel_sdvo_get_edid(connector);
1424 if (edid == NULL)
1425 edid = psb_intel_sdvo_get_analog_edid(connector);
1426 if (edid != NULL) {
1427 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1428 ret = connector_status_disconnected;
1429 else
1430 ret = connector_status_connected;
1431 kfree(edid);
1432 } else
1433 ret = connector_status_connected;
1434 }
1435
1436 /* May update encoder flag for like clock for SDVO TV, etc.*/
1437 if (ret == connector_status_connected) {
1438 psb_intel_sdvo->is_tv = false;
1439 psb_intel_sdvo->is_lvds = false;
1440 psb_intel_sdvo->base.needs_tv_clock = false;
1441
1442 if (response & SDVO_TV_MASK) {
1443 psb_intel_sdvo->is_tv = true;
1444 psb_intel_sdvo->base.needs_tv_clock = true;
1445 }
1446 if (response & SDVO_LVDS_MASK)
1447 psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1448 }
1449
1450 return ret;
1451 }
1452
1453 static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1454 {
1455 struct edid *edid;
1456
1457 /* set the bus switch and get the modes */
1458 edid = psb_intel_sdvo_get_edid(connector);
1459
1460 /*
1461 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1462 * link between analog and digital outputs. So, if the regular SDVO
1463 * DDC fails, check to see if the analog output is disconnected, in
1464 * which case we'll look there for the digital DDC data.
1465 */
1466 if (edid == NULL)
1467 edid = psb_intel_sdvo_get_analog_edid(connector);
1468
1469 if (edid != NULL) {
1470 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1471 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1472 bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
1473
1474 if (connector_is_digital == monitor_is_digital) {
1475 drm_connector_update_edid_property(connector, edid);
1476 drm_add_edid_modes(connector, edid);
1477 }
1478
1479 kfree(edid);
1480 }
1481 }
1482
1483 /*
1484 * Set of SDVO TV modes.
1485 * Note! This is in reply order (see loop in get_tv_modes).
1486 * XXX: all 60Hz refresh?
1487 */
1488 static const struct drm_display_mode sdvo_tv_modes[] = {
1489 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1490 416, 0, 200, 201, 232, 233, 0,
1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1492 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1493 416, 0, 240, 241, 272, 273, 0,
1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1495 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1496 496, 0, 300, 301, 332, 333, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1498 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1499 736, 0, 350, 351, 382, 383, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1501 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1502 736, 0, 400, 401, 432, 433, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1504 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1505 736, 0, 480, 481, 512, 513, 0,
1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1507 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1508 800, 0, 480, 481, 512, 513, 0,
1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1510 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1511 800, 0, 576, 577, 608, 609, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1513 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1514 816, 0, 350, 351, 382, 383, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1516 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1517 816, 0, 400, 401, 432, 433, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1519 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1520 816, 0, 480, 481, 512, 513, 0,
1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1522 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1523 816, 0, 540, 541, 572, 573, 0,
1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1525 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1526 816, 0, 576, 577, 608, 609, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1528 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1529 864, 0, 576, 577, 608, 609, 0,
1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1531 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1532 896, 0, 600, 601, 632, 633, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1534 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1535 928, 0, 624, 625, 656, 657, 0,
1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1537 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1538 1016, 0, 766, 767, 798, 799, 0,
1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1540 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1541 1120, 0, 768, 769, 800, 801, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1543 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1544 1376, 0, 1024, 1025, 1056, 1057, 0,
1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1546 };
1547
1548 static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
1549 {
1550 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1551 struct psb_intel_sdvo_sdtv_resolution_request tv_res;
1552 uint32_t reply = 0, format_map = 0;
1553 int i;
1554
1555 /* Read the list of supported input resolutions for the selected TV
1556 * format.
1557 */
1558 format_map = 1 << psb_intel_sdvo->tv_format_index;
1559 memcpy(&tv_res, &format_map,
1560 min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
1561
1562 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
1563 return;
1564
1565 BUILD_BUG_ON(sizeof(tv_res) != 3);
1566 if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
1567 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1568 &tv_res, sizeof(tv_res)))
1569 return;
1570 if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
1571 return;
1572
1573 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1574 if (reply & (1 << i)) {
1575 struct drm_display_mode *nmode;
1576 nmode = drm_mode_duplicate(connector->dev,
1577 &sdvo_tv_modes[i]);
1578 if (nmode)
1579 drm_mode_probed_add(connector, nmode);
1580 }
1581 }
1582
1583 static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1584 {
1585 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1586 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1587 struct drm_display_mode *newmode;
1588
1589 /*
1590 * Attempt to get the mode list from DDC.
1591 * Assume that the preferred modes are
1592 * arranged in priority order.
1593 */
1594 psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
1595 if (list_empty(&connector->probed_modes) == false)
1596 goto end;
1597
1598 /* Fetch modes from VBT */
1599 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1600 newmode = drm_mode_duplicate(connector->dev,
1601 dev_priv->sdvo_lvds_vbt_mode);
1602 if (newmode != NULL) {
1603 /* Guarantee the mode is preferred */
1604 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1605 DRM_MODE_TYPE_DRIVER);
1606 drm_mode_probed_add(connector, newmode);
1607 }
1608 }
1609
1610 end:
1611 list_for_each_entry(newmode, &connector->probed_modes, head) {
1612 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1613 psb_intel_sdvo->sdvo_lvds_fixed_mode =
1614 drm_mode_duplicate(connector->dev, newmode);
1615
1616 drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
1617 0);
1618
1619 psb_intel_sdvo->is_lvds = true;
1620 break;
1621 }
1622 }
1623
1624 }
1625
1626 static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
1627 {
1628 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1629
1630 if (IS_TV(psb_intel_sdvo_connector))
1631 psb_intel_sdvo_get_tv_modes(connector);
1632 else if (IS_LVDS(psb_intel_sdvo_connector))
1633 psb_intel_sdvo_get_lvds_modes(connector);
1634 else
1635 psb_intel_sdvo_get_ddc_modes(connector);
1636
1637 return !list_empty(&connector->probed_modes);
1638 }
1639
1640 static void psb_intel_sdvo_destroy(struct drm_connector *connector)
1641 {
1642 drm_connector_unregister(connector);
1643 drm_connector_cleanup(connector);
1644 kfree(connector);
1645 }
1646
1647 static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1648 {
1649 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1650 struct edid *edid;
1651 bool has_audio = false;
1652
1653 if (!psb_intel_sdvo->is_hdmi)
1654 return false;
1655
1656 edid = psb_intel_sdvo_get_edid(connector);
1657 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1658 has_audio = drm_detect_monitor_audio(edid);
1659
1660 return has_audio;
1661 }
1662
1663 static int
1664 psb_intel_sdvo_set_property(struct drm_connector *connector,
1665 struct drm_property *property,
1666 uint64_t val)
1667 {
1668 struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
1669 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
1670 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1671 uint16_t temp_value;
1672 uint8_t cmd;
1673 int ret;
1674
1675 ret = drm_object_property_set_value(&connector->base, property, val);
1676 if (ret)
1677 return ret;
1678
1679 if (property == dev_priv->force_audio_property) {
1680 int i = val;
1681 bool has_audio;
1682
1683 if (i == psb_intel_sdvo_connector->force_audio)
1684 return 0;
1685
1686 psb_intel_sdvo_connector->force_audio = i;
1687
1688 if (i == 0)
1689 has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
1690 else
1691 has_audio = i > 0;
1692
1693 if (has_audio == psb_intel_sdvo->has_hdmi_audio)
1694 return 0;
1695
1696 psb_intel_sdvo->has_hdmi_audio = has_audio;
1697 goto done;
1698 }
1699
1700 if (property == dev_priv->broadcast_rgb_property) {
1701 if (val == !!psb_intel_sdvo->color_range)
1702 return 0;
1703
1704 psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
1705 goto done;
1706 }
1707
1708 #define CHECK_PROPERTY(name, NAME) \
1709 if (psb_intel_sdvo_connector->name == property) { \
1710 if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
1711 if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1712 cmd = SDVO_CMD_SET_##NAME; \
1713 psb_intel_sdvo_connector->cur_##name = temp_value; \
1714 goto set_value; \
1715 }
1716
1717 if (property == psb_intel_sdvo_connector->tv_format) {
1718 if (val >= ARRAY_SIZE(tv_format_names))
1719 return -EINVAL;
1720
1721 if (psb_intel_sdvo->tv_format_index ==
1722 psb_intel_sdvo_connector->tv_format_supported[val])
1723 return 0;
1724
1725 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
1726 goto done;
1727 } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
1728 temp_value = val;
1729 if (psb_intel_sdvo_connector->left == property) {
1730 drm_object_property_set_value(&connector->base,
1731 psb_intel_sdvo_connector->right, val);
1732 if (psb_intel_sdvo_connector->left_margin == temp_value)
1733 return 0;
1734
1735 psb_intel_sdvo_connector->left_margin = temp_value;
1736 psb_intel_sdvo_connector->right_margin = temp_value;
1737 temp_value = psb_intel_sdvo_connector->max_hscan -
1738 psb_intel_sdvo_connector->left_margin;
1739 cmd = SDVO_CMD_SET_OVERSCAN_H;
1740 goto set_value;
1741 } else if (psb_intel_sdvo_connector->right == property) {
1742 drm_object_property_set_value(&connector->base,
1743 psb_intel_sdvo_connector->left, val);
1744 if (psb_intel_sdvo_connector->right_margin == temp_value)
1745 return 0;
1746
1747 psb_intel_sdvo_connector->left_margin = temp_value;
1748 psb_intel_sdvo_connector->right_margin = temp_value;
1749 temp_value = psb_intel_sdvo_connector->max_hscan -
1750 psb_intel_sdvo_connector->left_margin;
1751 cmd = SDVO_CMD_SET_OVERSCAN_H;
1752 goto set_value;
1753 } else if (psb_intel_sdvo_connector->top == property) {
1754 drm_object_property_set_value(&connector->base,
1755 psb_intel_sdvo_connector->bottom, val);
1756 if (psb_intel_sdvo_connector->top_margin == temp_value)
1757 return 0;
1758
1759 psb_intel_sdvo_connector->top_margin = temp_value;
1760 psb_intel_sdvo_connector->bottom_margin = temp_value;
1761 temp_value = psb_intel_sdvo_connector->max_vscan -
1762 psb_intel_sdvo_connector->top_margin;
1763 cmd = SDVO_CMD_SET_OVERSCAN_V;
1764 goto set_value;
1765 } else if (psb_intel_sdvo_connector->bottom == property) {
1766 drm_object_property_set_value(&connector->base,
1767 psb_intel_sdvo_connector->top, val);
1768 if (psb_intel_sdvo_connector->bottom_margin == temp_value)
1769 return 0;
1770
1771 psb_intel_sdvo_connector->top_margin = temp_value;
1772 psb_intel_sdvo_connector->bottom_margin = temp_value;
1773 temp_value = psb_intel_sdvo_connector->max_vscan -
1774 psb_intel_sdvo_connector->top_margin;
1775 cmd = SDVO_CMD_SET_OVERSCAN_V;
1776 goto set_value;
1777 }
1778 CHECK_PROPERTY(hpos, HPOS)
1779 CHECK_PROPERTY(vpos, VPOS)
1780 CHECK_PROPERTY(saturation, SATURATION)
1781 CHECK_PROPERTY(contrast, CONTRAST)
1782 CHECK_PROPERTY(hue, HUE)
1783 CHECK_PROPERTY(brightness, BRIGHTNESS)
1784 CHECK_PROPERTY(sharpness, SHARPNESS)
1785 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1786 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1787 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1788 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1789 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
1790 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
1791 }
1792
1793 return -EINVAL; /* unknown property */
1794
1795 set_value:
1796 if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
1797 return -EIO;
1798
1799
1800 done:
1801 if (psb_intel_sdvo->base.base.crtc) {
1802 struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
1803 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1804 crtc->y, crtc->primary->fb);
1805 }
1806
1807 return 0;
1808 #undef CHECK_PROPERTY
1809 }
1810
1811 static void psb_intel_sdvo_save(struct drm_connector *connector)
1812 {
1813 struct drm_device *dev = connector->dev;
1814 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
1815 struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base);
1816
1817 sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg);
1818 }
1819
1820 static void psb_intel_sdvo_restore(struct drm_connector *connector)
1821 {
1822 struct drm_device *dev = connector->dev;
1823 struct drm_encoder *encoder = &gma_attached_encoder(connector)->base;
1824 struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder);
1825 struct drm_crtc *crtc = encoder->crtc;
1826
1827 REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO);
1828
1829 /* Force a full mode set on the crtc. We're supposed to have the
1830 mode_config lock already. */
1831 if (connector->status == connector_status_connected)
1832 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
1833 NULL);
1834 }
1835
1836 static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
1837 .dpms = psb_intel_sdvo_dpms,
1838 .mode_fixup = psb_intel_sdvo_mode_fixup,
1839 .prepare = gma_encoder_prepare,
1840 .mode_set = psb_intel_sdvo_mode_set,
1841 .commit = gma_encoder_commit,
1842 };
1843
1844 static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
1845 .dpms = drm_helper_connector_dpms,
1846 .detect = psb_intel_sdvo_detect,
1847 .fill_modes = drm_helper_probe_single_connector_modes,
1848 .set_property = psb_intel_sdvo_set_property,
1849 .destroy = psb_intel_sdvo_destroy,
1850 };
1851
1852 static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
1853 .get_modes = psb_intel_sdvo_get_modes,
1854 .mode_valid = psb_intel_sdvo_mode_valid,
1855 .best_encoder = gma_best_encoder,
1856 };
1857
1858 static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1859 {
1860 struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
1861
1862 if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
1863 drm_mode_destroy(encoder->dev,
1864 psb_intel_sdvo->sdvo_lvds_fixed_mode);
1865
1866 i2c_del_adapter(&psb_intel_sdvo->ddc);
1867 gma_encoder_destroy(encoder);
1868 }
1869
1870 static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
1871 .destroy = psb_intel_sdvo_enc_destroy,
1872 };
1873
1874 static void
1875 psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
1876 {
1877 /* FIXME: At the moment, ddc_bus = 2 is the only thing that works.
1878 * We need to figure out if this is true for all available poulsbo
1879 * hardware, or if we need to fiddle with the guessing code above.
1880 * The problem might go away if we can parse sdvo mappings from bios */
1881 sdvo->ddc_bus = 2;
1882
1883 #if 0
1884 uint16_t mask = 0;
1885 unsigned int num_bits;
1886
1887 /* Make a mask of outputs less than or equal to our own priority in the
1888 * list.
1889 */
1890 switch (sdvo->controlled_output) {
1891 case SDVO_OUTPUT_LVDS1:
1892 mask |= SDVO_OUTPUT_LVDS1;
1893 case SDVO_OUTPUT_LVDS0:
1894 mask |= SDVO_OUTPUT_LVDS0;
1895 case SDVO_OUTPUT_TMDS1:
1896 mask |= SDVO_OUTPUT_TMDS1;
1897 case SDVO_OUTPUT_TMDS0:
1898 mask |= SDVO_OUTPUT_TMDS0;
1899 case SDVO_OUTPUT_RGB1:
1900 mask |= SDVO_OUTPUT_RGB1;
1901 case SDVO_OUTPUT_RGB0:
1902 mask |= SDVO_OUTPUT_RGB0;
1903 break;
1904 }
1905
1906 /* Count bits to find what number we are in the priority list. */
1907 mask &= sdvo->caps.output_flags;
1908 num_bits = hweight16(mask);
1909 /* If more than 3 outputs, default to DDC bus 3 for now. */
1910 if (num_bits > 3)
1911 num_bits = 3;
1912
1913 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1914 sdvo->ddc_bus = 1 << num_bits;
1915 #endif
1916 }
1917
1918 /**
1919 * Choose the appropriate DDC bus for control bus switch command for this
1920 * SDVO output based on the controlled output.
1921 *
1922 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1923 * outputs, then LVDS outputs.
1924 */
1925 static void
1926 psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
1927 struct psb_intel_sdvo *sdvo, u32 reg)
1928 {
1929 struct sdvo_device_mapping *mapping;
1930
1931 if (IS_SDVOB(reg))
1932 mapping = &(dev_priv->sdvo_mappings[0]);
1933 else
1934 mapping = &(dev_priv->sdvo_mappings[1]);
1935
1936 if (mapping->initialized)
1937 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1938 else
1939 psb_intel_sdvo_guess_ddc_bus(sdvo);
1940 }
1941
1942 static void
1943 psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
1944 struct psb_intel_sdvo *sdvo, u32 reg)
1945 {
1946 struct sdvo_device_mapping *mapping;
1947 u8 pin, speed;
1948
1949 if (IS_SDVOB(reg))
1950 mapping = &dev_priv->sdvo_mappings[0];
1951 else
1952 mapping = &dev_priv->sdvo_mappings[1];
1953
1954 pin = GMBUS_PORT_DPB;
1955 speed = GMBUS_RATE_1MHZ >> 8;
1956 if (mapping->initialized) {
1957 pin = mapping->i2c_pin;
1958 speed = mapping->i2c_speed;
1959 }
1960
1961 if (pin < GMBUS_NUM_PORTS) {
1962 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
1963 gma_intel_gmbus_set_speed(sdvo->i2c, speed);
1964 gma_intel_gmbus_force_bit(sdvo->i2c, true);
1965 } else
1966 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
1967 }
1968
1969 static bool
1970 psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
1971 {
1972 return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
1973 }
1974
1975 static u8
1976 psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
1977 {
1978 struct drm_psb_private *dev_priv = dev->dev_private;
1979 struct sdvo_device_mapping *my_mapping, *other_mapping;
1980
1981 if (IS_SDVOB(sdvo_reg)) {
1982 my_mapping = &dev_priv->sdvo_mappings[0];
1983 other_mapping = &dev_priv->sdvo_mappings[1];
1984 } else {
1985 my_mapping = &dev_priv->sdvo_mappings[1];
1986 other_mapping = &dev_priv->sdvo_mappings[0];
1987 }
1988
1989 /* If the BIOS described our SDVO device, take advantage of it. */
1990 if (my_mapping->slave_addr)
1991 return my_mapping->slave_addr;
1992
1993 /* If the BIOS only described a different SDVO device, use the
1994 * address that it isn't using.
1995 */
1996 if (other_mapping->slave_addr) {
1997 if (other_mapping->slave_addr == 0x70)
1998 return 0x72;
1999 else
2000 return 0x70;
2001 }
2002
2003 /* No SDVO device info is found for another DVO port,
2004 * so use mapping assumption we had before BIOS parsing.
2005 */
2006 if (IS_SDVOB(sdvo_reg))
2007 return 0x70;
2008 else
2009 return 0x72;
2010 }
2011
2012 static void
2013 psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
2014 struct psb_intel_sdvo *encoder)
2015 {
2016 drm_connector_init(encoder->base.base.dev,
2017 &connector->base.base,
2018 &psb_intel_sdvo_connector_funcs,
2019 connector->base.base.connector_type);
2020
2021 drm_connector_helper_add(&connector->base.base,
2022 &psb_intel_sdvo_connector_helper_funcs);
2023
2024 connector->base.base.interlace_allowed = 0;
2025 connector->base.base.doublescan_allowed = 0;
2026 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2027
2028 connector->base.save = psb_intel_sdvo_save;
2029 connector->base.restore = psb_intel_sdvo_restore;
2030
2031 gma_connector_attach_encoder(&connector->base, &encoder->base);
2032 drm_connector_register(&connector->base.base);
2033 }
2034
2035 static void
2036 psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
2037 {
2038 /* FIXME: We don't support HDMI at the moment
2039 struct drm_device *dev = connector->base.base.dev;
2040
2041 intel_attach_force_audio_property(&connector->base.base);
2042 intel_attach_broadcast_rgb_property(&connector->base.base);
2043 */
2044 }
2045
2046 static bool
2047 psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
2048 {
2049 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2050 struct drm_connector *connector;
2051 struct gma_connector *intel_connector;
2052 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2053
2054 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2055 if (!psb_intel_sdvo_connector)
2056 return false;
2057
2058 if (device == 0) {
2059 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2060 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2061 } else if (device == 1) {
2062 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2063 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2064 }
2065
2066 intel_connector = &psb_intel_sdvo_connector->base;
2067 connector = &intel_connector->base;
2068 // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2069 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2070 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2071
2072 if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
2073 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2074 psb_intel_sdvo->is_hdmi = true;
2075 }
2076 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2077 (1 << INTEL_ANALOG_CLONE_BIT));
2078
2079 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
2080 if (psb_intel_sdvo->is_hdmi)
2081 psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
2082
2083 return true;
2084 }
2085
2086 static bool
2087 psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
2088 {
2089 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2090 struct drm_connector *connector;
2091 struct gma_connector *intel_connector;
2092 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2093
2094 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2095 if (!psb_intel_sdvo_connector)
2096 return false;
2097
2098 intel_connector = &psb_intel_sdvo_connector->base;
2099 connector = &intel_connector->base;
2100 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2101 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2102
2103 psb_intel_sdvo->controlled_output |= type;
2104 psb_intel_sdvo_connector->output_flag = type;
2105
2106 psb_intel_sdvo->is_tv = true;
2107 psb_intel_sdvo->base.needs_tv_clock = true;
2108 psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2109
2110 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
2111
2112 if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
2113 goto err;
2114
2115 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
2116 goto err;
2117
2118 return true;
2119
2120 err:
2121 psb_intel_sdvo_destroy(connector);
2122 return false;
2123 }
2124
2125 static bool
2126 psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
2127 {
2128 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2129 struct drm_connector *connector;
2130 struct gma_connector *intel_connector;
2131 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2132
2133 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2134 if (!psb_intel_sdvo_connector)
2135 return false;
2136
2137 intel_connector = &psb_intel_sdvo_connector->base;
2138 connector = &intel_connector->base;
2139 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2140 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2141 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2142
2143 if (device == 0) {
2144 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2145 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2146 } else if (device == 1) {
2147 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2148 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2149 }
2150
2151 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2152 (1 << INTEL_ANALOG_CLONE_BIT));
2153
2154 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
2155 psb_intel_sdvo);
2156 return true;
2157 }
2158
2159 static bool
2160 psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
2161 {
2162 struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
2163 struct drm_connector *connector;
2164 struct gma_connector *intel_connector;
2165 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
2166
2167 psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
2168 if (!psb_intel_sdvo_connector)
2169 return false;
2170
2171 intel_connector = &psb_intel_sdvo_connector->base;
2172 connector = &intel_connector->base;
2173 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2174 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2175
2176 if (device == 0) {
2177 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2178 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2179 } else if (device == 1) {
2180 psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2181 psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2182 }
2183
2184 psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2185 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
2186
2187 psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
2188 if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
2189 goto err;
2190
2191 return true;
2192
2193 err:
2194 psb_intel_sdvo_destroy(connector);
2195 return false;
2196 }
2197
2198 static bool
2199 psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
2200 {
2201 psb_intel_sdvo->is_tv = false;
2202 psb_intel_sdvo->base.needs_tv_clock = false;
2203 psb_intel_sdvo->is_lvds = false;
2204
2205 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2206
2207 if (flags & SDVO_OUTPUT_TMDS0)
2208 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
2209 return false;
2210
2211 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2212 if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
2213 return false;
2214
2215 /* TV has no XXX1 function block */
2216 if (flags & SDVO_OUTPUT_SVID0)
2217 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
2218 return false;
2219
2220 if (flags & SDVO_OUTPUT_CVBS0)
2221 if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
2222 return false;
2223
2224 if (flags & SDVO_OUTPUT_RGB0)
2225 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
2226 return false;
2227
2228 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2229 if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
2230 return false;
2231
2232 if (flags & SDVO_OUTPUT_LVDS0)
2233 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
2234 return false;
2235
2236 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2237 if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
2238 return false;
2239
2240 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2241 unsigned char bytes[2];
2242
2243 psb_intel_sdvo->controlled_output = 0;
2244 memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
2245 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2246 SDVO_NAME(psb_intel_sdvo),
2247 bytes[0], bytes[1]);
2248 return false;
2249 }
2250 psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
2251
2252 return true;
2253 }
2254
2255 static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
2256 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
2257 int type)
2258 {
2259 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
2260 struct psb_intel_sdvo_tv_format format;
2261 uint32_t format_map, i;
2262
2263 if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
2264 return false;
2265
2266 BUILD_BUG_ON(sizeof(format) != 6);
2267 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2268 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2269 &format, sizeof(format)))
2270 return false;
2271
2272 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2273
2274 if (format_map == 0)
2275 return false;
2276
2277 psb_intel_sdvo_connector->format_supported_num = 0;
2278 for (i = 0 ; i < ARRAY_SIZE(tv_format_names); i++)
2279 if (format_map & (1 << i))
2280 psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
2281
2282
2283 psb_intel_sdvo_connector->tv_format =
2284 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2285 "mode", psb_intel_sdvo_connector->format_supported_num);
2286 if (!psb_intel_sdvo_connector->tv_format)
2287 return false;
2288
2289 for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
2290 drm_property_add_enum(
2291 psb_intel_sdvo_connector->tv_format,
2292 i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
2293
2294 psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
2295 drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base,
2296 psb_intel_sdvo_connector->tv_format, 0);
2297 return true;
2298
2299 }
2300
2301 #define ENHANCEMENT(name, NAME) do { \
2302 if (enhancements.name) { \
2303 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2304 !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2305 return false; \
2306 psb_intel_sdvo_connector->max_##name = data_value[0]; \
2307 psb_intel_sdvo_connector->cur_##name = response; \
2308 psb_intel_sdvo_connector->name = \
2309 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2310 if (!psb_intel_sdvo_connector->name) return false; \
2311 drm_object_attach_property(&connector->base, \
2312 psb_intel_sdvo_connector->name, \
2313 psb_intel_sdvo_connector->cur_##name); \
2314 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2315 data_value[0], data_value[1], response); \
2316 } \
2317 } while(0)
2318
2319 static bool
2320 psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
2321 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
2322 struct psb_intel_sdvo_enhancements_reply enhancements)
2323 {
2324 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
2325 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
2326 uint16_t response, data_value[2];
2327
2328 /* when horizontal overscan is supported, Add the left/right property */
2329 if (enhancements.overscan_h) {
2330 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2331 SDVO_CMD_GET_MAX_OVERSCAN_H,
2332 &data_value, 4))
2333 return false;
2334
2335 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2336 SDVO_CMD_GET_OVERSCAN_H,
2337 &response, 2))
2338 return false;
2339
2340 psb_intel_sdvo_connector->max_hscan = data_value[0];
2341 psb_intel_sdvo_connector->left_margin = data_value[0] - response;
2342 psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
2343 psb_intel_sdvo_connector->left =
2344 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2345 if (!psb_intel_sdvo_connector->left)
2346 return false;
2347
2348 drm_object_attach_property(&connector->base,
2349 psb_intel_sdvo_connector->left,
2350 psb_intel_sdvo_connector->left_margin);
2351
2352 psb_intel_sdvo_connector->right =
2353 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2354 if (!psb_intel_sdvo_connector->right)
2355 return false;
2356
2357 drm_object_attach_property(&connector->base,
2358 psb_intel_sdvo_connector->right,
2359 psb_intel_sdvo_connector->right_margin);
2360 DRM_DEBUG_KMS("h_overscan: max %d, "
2361 "default %d, current %d\n",
2362 data_value[0], data_value[1], response);
2363 }
2364
2365 if (enhancements.overscan_v) {
2366 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2367 SDVO_CMD_GET_MAX_OVERSCAN_V,
2368 &data_value, 4))
2369 return false;
2370
2371 if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
2372 SDVO_CMD_GET_OVERSCAN_V,
2373 &response, 2))
2374 return false;
2375
2376 psb_intel_sdvo_connector->max_vscan = data_value[0];
2377 psb_intel_sdvo_connector->top_margin = data_value[0] - response;
2378 psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
2379 psb_intel_sdvo_connector->top =
2380 drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]);
2381 if (!psb_intel_sdvo_connector->top)
2382 return false;
2383
2384 drm_object_attach_property(&connector->base,
2385 psb_intel_sdvo_connector->top,
2386 psb_intel_sdvo_connector->top_margin);
2387
2388 psb_intel_sdvo_connector->bottom =
2389 drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]);
2390 if (!psb_intel_sdvo_connector->bottom)
2391 return false;
2392
2393 drm_object_attach_property(&connector->base,
2394 psb_intel_sdvo_connector->bottom,
2395 psb_intel_sdvo_connector->bottom_margin);
2396 DRM_DEBUG_KMS("v_overscan: max %d, "
2397 "default %d, current %d\n",
2398 data_value[0], data_value[1], response);
2399 }
2400
2401 ENHANCEMENT(hpos, HPOS);
2402 ENHANCEMENT(vpos, VPOS);
2403 ENHANCEMENT(saturation, SATURATION);
2404 ENHANCEMENT(contrast, CONTRAST);
2405 ENHANCEMENT(hue, HUE);
2406 ENHANCEMENT(sharpness, SHARPNESS);
2407 ENHANCEMENT(brightness, BRIGHTNESS);
2408 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2409 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2410 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2411 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2412 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2413
2414 if (enhancements.dot_crawl) {
2415 if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2416 return false;
2417
2418 psb_intel_sdvo_connector->max_dot_crawl = 1;
2419 psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2420 psb_intel_sdvo_connector->dot_crawl =
2421 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2422 if (!psb_intel_sdvo_connector->dot_crawl)
2423 return false;
2424
2425 drm_object_attach_property(&connector->base,
2426 psb_intel_sdvo_connector->dot_crawl,
2427 psb_intel_sdvo_connector->cur_dot_crawl);
2428 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2429 }
2430
2431 return true;
2432 }
2433
2434 static bool
2435 psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
2436 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
2437 struct psb_intel_sdvo_enhancements_reply enhancements)
2438 {
2439 struct drm_device *dev = psb_intel_sdvo->base.base.dev;
2440 struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
2441 uint16_t response, data_value[2];
2442
2443 ENHANCEMENT(brightness, BRIGHTNESS);
2444
2445 return true;
2446 }
2447 #undef ENHANCEMENT
2448
2449 static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
2450 struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
2451 {
2452 union {
2453 struct psb_intel_sdvo_enhancements_reply reply;
2454 uint16_t response;
2455 } enhancements;
2456
2457 BUILD_BUG_ON(sizeof(enhancements) != 2);
2458
2459 enhancements.response = 0;
2460 psb_intel_sdvo_get_value(psb_intel_sdvo,
2461 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2462 &enhancements, sizeof(enhancements));
2463 if (enhancements.response == 0) {
2464 DRM_DEBUG_KMS("No enhancement is supported\n");
2465 return true;
2466 }
2467
2468 if (IS_TV(psb_intel_sdvo_connector))
2469 return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
2470 else if(IS_LVDS(psb_intel_sdvo_connector))
2471 return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
2472 else
2473 return true;
2474 }
2475
2476 static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2477 struct i2c_msg *msgs,
2478 int num)
2479 {
2480 struct psb_intel_sdvo *sdvo = adapter->algo_data;
2481
2482 if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2483 return -EIO;
2484
2485 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2486 }
2487
2488 static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2489 {
2490 struct psb_intel_sdvo *sdvo = adapter->algo_data;
2491 return sdvo->i2c->algo->functionality(sdvo->i2c);
2492 }
2493
2494 static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
2495 .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
2496 .functionality = psb_intel_sdvo_ddc_proxy_func
2497 };
2498
2499 static bool
2500 psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
2501 struct drm_device *dev)
2502 {
2503 sdvo->ddc.owner = THIS_MODULE;
2504 sdvo->ddc.class = I2C_CLASS_DDC;
2505 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2506 sdvo->ddc.dev.parent = &dev->pdev->dev;
2507 sdvo->ddc.algo_data = sdvo;
2508 sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
2509
2510 return i2c_add_adapter(&sdvo->ddc) == 0;
2511 }
2512
2513 bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2514 {
2515 struct drm_psb_private *dev_priv = dev->dev_private;
2516 struct gma_encoder *gma_encoder;
2517 struct psb_intel_sdvo *psb_intel_sdvo;
2518 int i;
2519
2520 psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
2521 if (!psb_intel_sdvo)
2522 return false;
2523
2524 psb_intel_sdvo->sdvo_reg = sdvo_reg;
2525 psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2526 psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
2527 if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
2528 kfree(psb_intel_sdvo);
2529 return false;
2530 }
2531
2532 /* encoder type will be decided later */
2533 gma_encoder = &psb_intel_sdvo->base;
2534 gma_encoder->type = INTEL_OUTPUT_SDVO;
2535 drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs,
2536 0, NULL);
2537
2538 /* Read the regs to test if we can talk to the device */
2539 for (i = 0; i < 0x40; i++) {
2540 u8 byte;
2541
2542 if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
2543 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2544 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2545 goto err;
2546 }
2547 }
2548
2549 if (IS_SDVOB(sdvo_reg))
2550 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2551 else
2552 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2553
2554 drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs);
2555
2556 /* In default case sdvo lvds is false */
2557 if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
2558 goto err;
2559
2560 if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
2561 psb_intel_sdvo->caps.output_flags) != true) {
2562 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2563 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2564 goto err;
2565 }
2566
2567 psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
2568
2569 /* Set the input timing to the screen. Assume always input 0. */
2570 if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
2571 goto err;
2572
2573 if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
2574 &psb_intel_sdvo->pixel_clock_min,
2575 &psb_intel_sdvo->pixel_clock_max))
2576 goto err;
2577
2578 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2579 "clock range %dMHz - %dMHz, "
2580 "input 1: %c, input 2: %c, "
2581 "output 1: %c, output 2: %c\n",
2582 SDVO_NAME(psb_intel_sdvo),
2583 psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
2584 psb_intel_sdvo->caps.device_rev_id,
2585 psb_intel_sdvo->pixel_clock_min / 1000,
2586 psb_intel_sdvo->pixel_clock_max / 1000,
2587 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2588 (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2589 /* check currently supported outputs */
2590 psb_intel_sdvo->caps.output_flags &
2591 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2592 psb_intel_sdvo->caps.output_flags &
2593 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2594 return true;
2595
2596 err:
2597 drm_encoder_cleanup(&gma_encoder->base);
2598 i2c_del_adapter(&psb_intel_sdvo->ddc);
2599 kfree(psb_intel_sdvo);
2600
2601 return false;
2602 }
Linux with added FPC-III support