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drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_dpll_mgr.c
blobb51ad2917dbef4528d9a7c528e603f9602cd39fd
1 /*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "intel_drv.h"
25
26 /**
27 * DOC: Display PLLs
28 *
29 * Display PLLs used for driving outputs vary by platform. While some have
30 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
31 * from a pool. In the latter scenario, it is possible that multiple pipes
32 * share a PLL if their configurations match.
33 *
34 * This file provides an abstraction over display PLLs. The function
35 * intel_shared_dpll_init() initializes the PLLs for the given platform. The
36 * users of a PLL are tracked and that tracking is integrated with the atomic
37 * modest interface. During an atomic operation, a PLL can be requested for a
38 * given CRTC and encoder configuration by calling intel_get_shared_dpll() and
39 * a previously used PLL can be released with intel_release_shared_dpll().
40 * Changes to the users are first staged in the atomic state, and then made
41 * effective by calling intel_shared_dpll_swap_state() during the atomic
42 * commit phase.
43 */
44
45 static void
46 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
47 struct intel_shared_dpll_state *shared_dpll)
48 {
49 enum intel_dpll_id i;
50
51 /* Copy shared dpll state */
52 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
53 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
54
55 shared_dpll[i] = pll->state;
56 }
57 }
58
59 static struct intel_shared_dpll_state *
60 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
61 {
62 struct intel_atomic_state *state = to_intel_atomic_state(s);
63
64 WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
65
66 if (!state->dpll_set) {
67 state->dpll_set = true;
68
69 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
70 state->shared_dpll);
71 }
72
73 return state->shared_dpll;
74 }
75
76 /**
77 * intel_get_shared_dpll_by_id - get a DPLL given its id
78 * @dev_priv: i915 device instance
79 * @id: pll id
80 *
81 * Returns:
82 * A pointer to the DPLL with @id
83 */
84 struct intel_shared_dpll *
85 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
86 enum intel_dpll_id id)
87 {
88 return &dev_priv->shared_dplls[id];
89 }
90
91 /**
92 * intel_get_shared_dpll_id - get the id of a DPLL
93 * @dev_priv: i915 device instance
94 * @pll: the DPLL
95 *
96 * Returns:
97 * The id of @pll
98 */
99 enum intel_dpll_id
100 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
101 struct intel_shared_dpll *pll)
102 {
103 if (WARN_ON(pll < dev_priv->shared_dplls||
104 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
105 return -1;
106
107 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
108 }
109
110 /* For ILK+ */
111 void assert_shared_dpll(struct drm_i915_private *dev_priv,
112 struct intel_shared_dpll *pll,
113 bool state)
114 {
115 bool cur_state;
116 struct intel_dpll_hw_state hw_state;
117
118 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
119 return;
120
121 cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
122 I915_STATE_WARN(cur_state != state,
123 "%s assertion failure (expected %s, current %s)\n",
124 pll->info->name, onoff(state), onoff(cur_state));
125 }
126
127 /**
128 * intel_prepare_shared_dpll - call a dpll's prepare hook
129 * @crtc: CRTC which has a shared dpll
130 *
131 * This calls the PLL's prepare hook if it has one and if the PLL is not
132 * already enabled. The prepare hook is platform specific.
133 */
134 void intel_prepare_shared_dpll(struct intel_crtc *crtc)
135 {
136 struct drm_device *dev = crtc->base.dev;
137 struct drm_i915_private *dev_priv = to_i915(dev);
138 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
139
140 if (WARN_ON(pll == NULL))
141 return;
142
143 mutex_lock(&dev_priv->dpll_lock);
144 WARN_ON(!pll->state.crtc_mask);
145 if (!pll->active_mask) {
146 DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);
147 WARN_ON(pll->on);
148 assert_shared_dpll_disabled(dev_priv, pll);
149
150 pll->info->funcs->prepare(dev_priv, pll);
151 }
152 mutex_unlock(&dev_priv->dpll_lock);
153 }
154
155 /**
156 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
157 * @crtc: CRTC which has a shared DPLL
158 *
159 * Enable the shared DPLL used by @crtc.
160 */
161 void intel_enable_shared_dpll(struct intel_crtc *crtc)
162 {
163 struct drm_device *dev = crtc->base.dev;
164 struct drm_i915_private *dev_priv = to_i915(dev);
165 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
166 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
167 unsigned int old_mask;
168
169 if (WARN_ON(pll == NULL))
170 return;
171
172 mutex_lock(&dev_priv->dpll_lock);
173 old_mask = pll->active_mask;
174
175 if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) ||
176 WARN_ON(pll->active_mask & crtc_mask))
177 goto out;
178
179 pll->active_mask |= crtc_mask;
180
181 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
182 pll->info->name, pll->active_mask, pll->on,
183 crtc->base.base.id);
184
185 if (old_mask) {
186 WARN_ON(!pll->on);
187 assert_shared_dpll_enabled(dev_priv, pll);
188 goto out;
189 }
190 WARN_ON(pll->on);
191
192 DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
193 pll->info->funcs->enable(dev_priv, pll);
194 pll->on = true;
195
196 out:
197 mutex_unlock(&dev_priv->dpll_lock);
198 }
199
200 /**
201 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
202 * @crtc: CRTC which has a shared DPLL
203 *
204 * Disable the shared DPLL used by @crtc.
205 */
206 void intel_disable_shared_dpll(struct intel_crtc *crtc)
207 {
208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
209 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
210 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
211
212 /* PCH only available on ILK+ */
213 if (INTEL_GEN(dev_priv) < 5)
214 return;
215
216 if (pll == NULL)
217 return;
218
219 mutex_lock(&dev_priv->dpll_lock);
220 if (WARN_ON(!(pll->active_mask & crtc_mask)))
221 goto out;
222
223 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
224 pll->info->name, pll->active_mask, pll->on,
225 crtc->base.base.id);
226
227 assert_shared_dpll_enabled(dev_priv, pll);
228 WARN_ON(!pll->on);
229
230 pll->active_mask &= ~crtc_mask;
231 if (pll->active_mask)
232 goto out;
233
234 DRM_DEBUG_KMS("disabling %s\n", pll->info->name);
235 pll->info->funcs->disable(dev_priv, pll);
236 pll->on = false;
237
238 out:
239 mutex_unlock(&dev_priv->dpll_lock);
240 }
241
242 static struct intel_shared_dpll *
243 intel_find_shared_dpll(struct intel_crtc *crtc,
244 struct intel_crtc_state *crtc_state,
245 enum intel_dpll_id range_min,
246 enum intel_dpll_id range_max)
247 {
248 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
249 struct intel_shared_dpll *pll;
250 struct intel_shared_dpll_state *shared_dpll;
251 enum intel_dpll_id i;
252
253 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
254
255 for (i = range_min; i <= range_max; i++) {
256 pll = &dev_priv->shared_dplls[i];
257
258 /* Only want to check enabled timings first */
259 if (shared_dpll[i].crtc_mask == 0)
260 continue;
261
262 if (memcmp(&crtc_state->dpll_hw_state,
263 &shared_dpll[i].hw_state,
264 sizeof(crtc_state->dpll_hw_state)) == 0) {
265 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
266 crtc->base.base.id, crtc->base.name,
267 pll->info->name,
268 shared_dpll[i].crtc_mask,
269 pll->active_mask);
270 return pll;
271 }
272 }
273
274 /* Ok no matching timings, maybe there's a free one? */
275 for (i = range_min; i <= range_max; i++) {
276 pll = &dev_priv->shared_dplls[i];
277 if (shared_dpll[i].crtc_mask == 0) {
278 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
279 crtc->base.base.id, crtc->base.name,
280 pll->info->name);
281 return pll;
282 }
283 }
284
285 return NULL;
286 }
287
288 static void
289 intel_reference_shared_dpll(struct intel_shared_dpll *pll,
290 struct intel_crtc_state *crtc_state)
291 {
292 struct intel_shared_dpll_state *shared_dpll;
293 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
294 const enum intel_dpll_id id = pll->info->id;
295
296 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
297
298 if (shared_dpll[id].crtc_mask == 0)
299 shared_dpll[id].hw_state =
300 crtc_state->dpll_hw_state;
301
302 crtc_state->shared_dpll = pll;
303 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
304 pipe_name(crtc->pipe));
305
306 shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
307 }
308
309 /**
310 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
311 * @state: atomic state
312 *
313 * This is the dpll version of drm_atomic_helper_swap_state() since the
314 * helper does not handle driver-specific global state.
315 *
316 * For consistency with atomic helpers this function does a complete swap,
317 * i.e. it also puts the current state into @state, even though there is no
318 * need for that at this moment.
319 */
320 void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
321 {
322 struct drm_i915_private *dev_priv = to_i915(state->dev);
323 struct intel_shared_dpll_state *shared_dpll;
324 struct intel_shared_dpll *pll;
325 enum intel_dpll_id i;
326
327 if (!to_intel_atomic_state(state)->dpll_set)
328 return;
329
330 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
331 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
332 struct intel_shared_dpll_state tmp;
333
334 pll = &dev_priv->shared_dplls[i];
335
336 tmp = pll->state;
337 pll->state = shared_dpll[i];
338 shared_dpll[i] = tmp;
339 }
340 }
341
342 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
343 struct intel_shared_dpll *pll,
344 struct intel_dpll_hw_state *hw_state)
345 {
346 const enum intel_dpll_id id = pll->info->id;
347 uint32_t val;
348
349 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
350 return false;
351
352 val = I915_READ(PCH_DPLL(id));
353 hw_state->dpll = val;
354 hw_state->fp0 = I915_READ(PCH_FP0(id));
355 hw_state->fp1 = I915_READ(PCH_FP1(id));
356
357 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
358
359 return val & DPLL_VCO_ENABLE;
360 }
361
362 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
363 struct intel_shared_dpll *pll)
364 {
365 const enum intel_dpll_id id = pll->info->id;
366
367 I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
368 I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
369 }
370
371 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
372 {
373 u32 val;
374 bool enabled;
375
376 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
377
378 val = I915_READ(PCH_DREF_CONTROL);
379 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
380 DREF_SUPERSPREAD_SOURCE_MASK));
381 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
382 }
383
384 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
385 struct intel_shared_dpll *pll)
386 {
387 const enum intel_dpll_id id = pll->info->id;
388
389 /* PCH refclock must be enabled first */
390 ibx_assert_pch_refclk_enabled(dev_priv);
391
392 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
393
394 /* Wait for the clocks to stabilize. */
395 POSTING_READ(PCH_DPLL(id));
396 udelay(150);
397
398 /* The pixel multiplier can only be updated once the
399 * DPLL is enabled and the clocks are stable.
400 *
401 * So write it again.
402 */
403 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
404 POSTING_READ(PCH_DPLL(id));
405 udelay(200);
406 }
407
408 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
409 struct intel_shared_dpll *pll)
410 {
411 const enum intel_dpll_id id = pll->info->id;
412 struct drm_device *dev = &dev_priv->drm;
413 struct intel_crtc *crtc;
414
415 /* Make sure no transcoder isn't still depending on us. */
416 for_each_intel_crtc(dev, crtc) {
417 if (crtc->config->shared_dpll == pll)
418 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
419 }
420
421 I915_WRITE(PCH_DPLL(id), 0);
422 POSTING_READ(PCH_DPLL(id));
423 udelay(200);
424 }
425
426 static struct intel_shared_dpll *
427 ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
428 struct intel_encoder *encoder)
429 {
430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
431 struct intel_shared_dpll *pll;
432 enum intel_dpll_id i;
433
434 if (HAS_PCH_IBX(dev_priv)) {
435 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
436 i = (enum intel_dpll_id) crtc->pipe;
437 pll = &dev_priv->shared_dplls[i];
438
439 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
440 crtc->base.base.id, crtc->base.name,
441 pll->info->name);
442 } else {
443 pll = intel_find_shared_dpll(crtc, crtc_state,
444 DPLL_ID_PCH_PLL_A,
445 DPLL_ID_PCH_PLL_B);
446 }
447
448 if (!pll)
449 return NULL;
450
451 /* reference the pll */
452 intel_reference_shared_dpll(pll, crtc_state);
453
454 return pll;
455 }
456
457 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
458 struct intel_dpll_hw_state *hw_state)
459 {
460 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
461 "fp0: 0x%x, fp1: 0x%x\n",
462 hw_state->dpll,
463 hw_state->dpll_md,
464 hw_state->fp0,
465 hw_state->fp1);
466 }
467
468 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
469 .prepare = ibx_pch_dpll_prepare,
470 .enable = ibx_pch_dpll_enable,
471 .disable = ibx_pch_dpll_disable,
472 .get_hw_state = ibx_pch_dpll_get_hw_state,
473 };
474
475 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
476 struct intel_shared_dpll *pll)
477 {
478 const enum intel_dpll_id id = pll->info->id;
479
480 I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
481 POSTING_READ(WRPLL_CTL(id));
482 udelay(20);
483 }
484
485 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
486 struct intel_shared_dpll *pll)
487 {
488 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
489 POSTING_READ(SPLL_CTL);
490 udelay(20);
491 }
492
493 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
494 struct intel_shared_dpll *pll)
495 {
496 const enum intel_dpll_id id = pll->info->id;
497 uint32_t val;
498
499 val = I915_READ(WRPLL_CTL(id));
500 I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
501 POSTING_READ(WRPLL_CTL(id));
502 }
503
504 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
505 struct intel_shared_dpll *pll)
506 {
507 uint32_t val;
508
509 val = I915_READ(SPLL_CTL);
510 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
511 POSTING_READ(SPLL_CTL);
512 }
513
514 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
515 struct intel_shared_dpll *pll,
516 struct intel_dpll_hw_state *hw_state)
517 {
518 const enum intel_dpll_id id = pll->info->id;
519 uint32_t val;
520
521 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
522 return false;
523
524 val = I915_READ(WRPLL_CTL(id));
525 hw_state->wrpll = val;
526
527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
528
529 return val & WRPLL_PLL_ENABLE;
530 }
531
532 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
533 struct intel_shared_dpll *pll,
534 struct intel_dpll_hw_state *hw_state)
535 {
536 uint32_t val;
537
538 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
539 return false;
540
541 val = I915_READ(SPLL_CTL);
542 hw_state->spll = val;
543
544 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
545
546 return val & SPLL_PLL_ENABLE;
547 }
548
549 #define LC_FREQ 2700
550 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
551
552 #define P_MIN 2
553 #define P_MAX 64
554 #define P_INC 2
555
556 /* Constraints for PLL good behavior */
557 #define REF_MIN 48
558 #define REF_MAX 400
559 #define VCO_MIN 2400
560 #define VCO_MAX 4800
561
562 struct hsw_wrpll_rnp {
563 unsigned p, n2, r2;
564 };
565
566 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
567 {
568 unsigned budget;
569
570 switch (clock) {
571 case 25175000:
572 case 25200000:
573 case 27000000:
574 case 27027000:
575 case 37762500:
576 case 37800000:
577 case 40500000:
578 case 40541000:
579 case 54000000:
580 case 54054000:
581 case 59341000:
582 case 59400000:
583 case 72000000:
584 case 74176000:
585 case 74250000:
586 case 81000000:
587 case 81081000:
588 case 89012000:
589 case 89100000:
590 case 108000000:
591 case 108108000:
592 case 111264000:
593 case 111375000:
594 case 148352000:
595 case 148500000:
596 case 162000000:
597 case 162162000:
598 case 222525000:
599 case 222750000:
600 case 296703000:
601 case 297000000:
602 budget = 0;
603 break;
604 case 233500000:
605 case 245250000:
606 case 247750000:
607 case 253250000:
608 case 298000000:
609 budget = 1500;
610 break;
611 case 169128000:
612 case 169500000:
613 case 179500000:
614 case 202000000:
615 budget = 2000;
616 break;
617 case 256250000:
618 case 262500000:
619 case 270000000:
620 case 272500000:
621 case 273750000:
622 case 280750000:
623 case 281250000:
624 case 286000000:
625 case 291750000:
626 budget = 4000;
627 break;
628 case 267250000:
629 case 268500000:
630 budget = 5000;
631 break;
632 default:
633 budget = 1000;
634 break;
635 }
636
637 return budget;
638 }
639
640 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
641 unsigned r2, unsigned n2, unsigned p,
642 struct hsw_wrpll_rnp *best)
643 {
644 uint64_t a, b, c, d, diff, diff_best;
645
646 /* No best (r,n,p) yet */
647 if (best->p == 0) {
648 best->p = p;
649 best->n2 = n2;
650 best->r2 = r2;
651 return;
652 }
653
654 /*
655 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
656 * freq2k.
657 *
658 * delta = 1e6 *
659 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
660 * freq2k;
661 *
662 * and we would like delta <= budget.
663 *
664 * If the discrepancy is above the PPM-based budget, always prefer to
665 * improve upon the previous solution. However, if you're within the
666 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
667 */
668 a = freq2k * budget * p * r2;
669 b = freq2k * budget * best->p * best->r2;
670 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
671 diff_best = abs_diff(freq2k * best->p * best->r2,
672 LC_FREQ_2K * best->n2);
673 c = 1000000 * diff;
674 d = 1000000 * diff_best;
675
676 if (a < c && b < d) {
677 /* If both are above the budget, pick the closer */
678 if (best->p * best->r2 * diff < p * r2 * diff_best) {
679 best->p = p;
680 best->n2 = n2;
681 best->r2 = r2;
682 }
683 } else if (a >= c && b < d) {
684 /* If A is below the threshold but B is above it? Update. */
685 best->p = p;
686 best->n2 = n2;
687 best->r2 = r2;
688 } else if (a >= c && b >= d) {
689 /* Both are below the limit, so pick the higher n2/(r2*r2) */
690 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
691 best->p = p;
692 best->n2 = n2;
693 best->r2 = r2;
694 }
695 }
696 /* Otherwise a < c && b >= d, do nothing */
697 }
698
699 static void
700 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
701 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
702 {
703 uint64_t freq2k;
704 unsigned p, n2, r2;
705 struct hsw_wrpll_rnp best = { 0, 0, 0 };
706 unsigned budget;
707
708 freq2k = clock / 100;
709
710 budget = hsw_wrpll_get_budget_for_freq(clock);
711
712 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
713 * and directly pass the LC PLL to it. */
714 if (freq2k == 5400000) {
715 *n2_out = 2;
716 *p_out = 1;
717 *r2_out = 2;
718 return;
719 }
720
721 /*
722 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
723 * the WR PLL.
724 *
725 * We want R so that REF_MIN <= Ref <= REF_MAX.
726 * Injecting R2 = 2 * R gives:
727 * REF_MAX * r2 > LC_FREQ * 2 and
728 * REF_MIN * r2 < LC_FREQ * 2
729 *
730 * Which means the desired boundaries for r2 are:
731 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
732 *
733 */
734 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
735 r2 <= LC_FREQ * 2 / REF_MIN;
736 r2++) {
737
738 /*
739 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
740 *
741 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
742 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
743 * VCO_MAX * r2 > n2 * LC_FREQ and
744 * VCO_MIN * r2 < n2 * LC_FREQ)
745 *
746 * Which means the desired boundaries for n2 are:
747 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
748 */
749 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
750 n2 <= VCO_MAX * r2 / LC_FREQ;
751 n2++) {
752
753 for (p = P_MIN; p <= P_MAX; p += P_INC)
754 hsw_wrpll_update_rnp(freq2k, budget,
755 r2, n2, p, &best);
756 }
757 }
758
759 *n2_out = best.n2;
760 *p_out = best.p;
761 *r2_out = best.r2;
762 }
763
764 static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
765 struct intel_crtc *crtc,
766 struct intel_crtc_state *crtc_state)
767 {
768 struct intel_shared_dpll *pll;
769 uint32_t val;
770 unsigned int p, n2, r2;
771
772 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
773
774 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
775 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
776 WRPLL_DIVIDER_POST(p);
777
778 crtc_state->dpll_hw_state.wrpll = val;
779
780 pll = intel_find_shared_dpll(crtc, crtc_state,
781 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
782
783 if (!pll)
784 return NULL;
785
786 return pll;
787 }
788
789 static struct intel_shared_dpll *
790 hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock)
791 {
792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
793 struct intel_shared_dpll *pll;
794 enum intel_dpll_id pll_id;
795
796 switch (clock / 2) {
797 case 81000:
798 pll_id = DPLL_ID_LCPLL_810;
799 break;
800 case 135000:
801 pll_id = DPLL_ID_LCPLL_1350;
802 break;
803 case 270000:
804 pll_id = DPLL_ID_LCPLL_2700;
805 break;
806 default:
807 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
808 return NULL;
809 }
810
811 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
812
813 if (!pll)
814 return NULL;
815
816 return pll;
817 }
818
819 static struct intel_shared_dpll *
820 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
821 struct intel_encoder *encoder)
822 {
823 struct intel_shared_dpll *pll;
824 int clock = crtc_state->port_clock;
825
826 memset(&crtc_state->dpll_hw_state, 0,
827 sizeof(crtc_state->dpll_hw_state));
828
829 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
830 pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);
831 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
832 pll = hsw_ddi_dp_get_dpll(encoder, clock);
833 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
834 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
835 return NULL;
836
837 crtc_state->dpll_hw_state.spll =
838 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
839
840 pll = intel_find_shared_dpll(crtc, crtc_state,
841 DPLL_ID_SPLL, DPLL_ID_SPLL);
842 } else {
843 return NULL;
844 }
845
846 if (!pll)
847 return NULL;
848
849 intel_reference_shared_dpll(pll, crtc_state);
850
851 return pll;
852 }
853
854 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
855 struct intel_dpll_hw_state *hw_state)
856 {
857 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
858 hw_state->wrpll, hw_state->spll);
859 }
860
861 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
862 .enable = hsw_ddi_wrpll_enable,
863 .disable = hsw_ddi_wrpll_disable,
864 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
865 };
866
867 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
868 .enable = hsw_ddi_spll_enable,
869 .disable = hsw_ddi_spll_disable,
870 .get_hw_state = hsw_ddi_spll_get_hw_state,
871 };
872
873 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
874 struct intel_shared_dpll *pll)
875 {
876 }
877
878 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
879 struct intel_shared_dpll *pll)
880 {
881 }
882
883 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
884 struct intel_shared_dpll *pll,
885 struct intel_dpll_hw_state *hw_state)
886 {
887 return true;
888 }
889
890 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
891 .enable = hsw_ddi_lcpll_enable,
892 .disable = hsw_ddi_lcpll_disable,
893 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
894 };
895
896 struct skl_dpll_regs {
897 i915_reg_t ctl, cfgcr1, cfgcr2;
898 };
899
900 /* this array is indexed by the *shared* pll id */
901 static const struct skl_dpll_regs skl_dpll_regs[4] = {
902 {
903 /* DPLL 0 */
904 .ctl = LCPLL1_CTL,
905 /* DPLL 0 doesn't support HDMI mode */
906 },
907 {
908 /* DPLL 1 */
909 .ctl = LCPLL2_CTL,
910 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
911 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
912 },
913 {
914 /* DPLL 2 */
915 .ctl = WRPLL_CTL(0),
916 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
917 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
918 },
919 {
920 /* DPLL 3 */
921 .ctl = WRPLL_CTL(1),
922 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
923 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
924 },
925 };
926
927 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll)
929 {
930 const enum intel_dpll_id id = pll->info->id;
931 uint32_t val;
932
933 val = I915_READ(DPLL_CTRL1);
934
935 val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
936 DPLL_CTRL1_SSC(id) |
937 DPLL_CTRL1_LINK_RATE_MASK(id));
938 val |= pll->state.hw_state.ctrl1 << (id * 6);
939
940 I915_WRITE(DPLL_CTRL1, val);
941 POSTING_READ(DPLL_CTRL1);
942 }
943
944 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll)
946 {
947 const struct skl_dpll_regs *regs = skl_dpll_regs;
948 const enum intel_dpll_id id = pll->info->id;
949
950 skl_ddi_pll_write_ctrl1(dev_priv, pll);
951
952 I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
953 I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
954 POSTING_READ(regs[id].cfgcr1);
955 POSTING_READ(regs[id].cfgcr2);
956
957 /* the enable bit is always bit 31 */
958 I915_WRITE(regs[id].ctl,
959 I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
960
961 if (intel_wait_for_register(dev_priv,
962 DPLL_STATUS,
963 DPLL_LOCK(id),
964 DPLL_LOCK(id),
965 5))
966 DRM_ERROR("DPLL %d not locked\n", id);
967 }
968
969 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
970 struct intel_shared_dpll *pll)
971 {
972 skl_ddi_pll_write_ctrl1(dev_priv, pll);
973 }
974
975 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
976 struct intel_shared_dpll *pll)
977 {
978 const struct skl_dpll_regs *regs = skl_dpll_regs;
979 const enum intel_dpll_id id = pll->info->id;
980
981 /* the enable bit is always bit 31 */
982 I915_WRITE(regs[id].ctl,
983 I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
984 POSTING_READ(regs[id].ctl);
985 }
986
987 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
988 struct intel_shared_dpll *pll)
989 {
990 }
991
992 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
993 struct intel_shared_dpll *pll,
994 struct intel_dpll_hw_state *hw_state)
995 {
996 uint32_t val;
997 const struct skl_dpll_regs *regs = skl_dpll_regs;
998 const enum intel_dpll_id id = pll->info->id;
999 bool ret;
1000
1001 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1002 return false;
1003
1004 ret = false;
1005
1006 val = I915_READ(regs[id].ctl);
1007 if (!(val & LCPLL_PLL_ENABLE))
1008 goto out;
1009
1010 val = I915_READ(DPLL_CTRL1);
1011 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1012
1013 /* avoid reading back stale values if HDMI mode is not enabled */
1014 if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1015 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
1016 hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
1017 }
1018 ret = true;
1019
1020 out:
1021 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1022
1023 return ret;
1024 }
1025
1026 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1027 struct intel_shared_dpll *pll,
1028 struct intel_dpll_hw_state *hw_state)
1029 {
1030 uint32_t val;
1031 const struct skl_dpll_regs *regs = skl_dpll_regs;
1032 const enum intel_dpll_id id = pll->info->id;
1033 bool ret;
1034
1035 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1036 return false;
1037
1038 ret = false;
1039
1040 /* DPLL0 is always enabled since it drives CDCLK */
1041 val = I915_READ(regs[id].ctl);
1042 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
1043 goto out;
1044
1045 val = I915_READ(DPLL_CTRL1);
1046 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1047
1048 ret = true;
1049
1050 out:
1051 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1052
1053 return ret;
1054 }
1055
1056 struct skl_wrpll_context {
1057 uint64_t min_deviation; /* current minimal deviation */
1058 uint64_t central_freq; /* chosen central freq */
1059 uint64_t dco_freq; /* chosen dco freq */
1060 unsigned int p; /* chosen divider */
1061 };
1062
1063 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1064 {
1065 memset(ctx, 0, sizeof(*ctx));
1066
1067 ctx->min_deviation = U64_MAX;
1068 }
1069
1070 /* DCO freq must be within +1%/-6% of the DCO central freq */
1071 #define SKL_DCO_MAX_PDEVIATION 100
1072 #define SKL_DCO_MAX_NDEVIATION 600
1073
1074 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1075 uint64_t central_freq,
1076 uint64_t dco_freq,
1077 unsigned int divider)
1078 {
1079 uint64_t deviation;
1080
1081 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1082 central_freq);
1083
1084 /* positive deviation */
1085 if (dco_freq >= central_freq) {
1086 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1087 deviation < ctx->min_deviation) {
1088 ctx->min_deviation = deviation;
1089 ctx->central_freq = central_freq;
1090 ctx->dco_freq = dco_freq;
1091 ctx->p = divider;
1092 }
1093 /* negative deviation */
1094 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1095 deviation < ctx->min_deviation) {
1096 ctx->min_deviation = deviation;
1097 ctx->central_freq = central_freq;
1098 ctx->dco_freq = dco_freq;
1099 ctx->p = divider;
1100 }
1101 }
1102
1103 static void skl_wrpll_get_multipliers(unsigned int p,
1104 unsigned int *p0 /* out */,
1105 unsigned int *p1 /* out */,
1106 unsigned int *p2 /* out */)
1107 {
1108 /* even dividers */
1109 if (p % 2 == 0) {
1110 unsigned int half = p / 2;
1111
1112 if (half == 1 || half == 2 || half == 3 || half == 5) {
1113 *p0 = 2;
1114 *p1 = 1;
1115 *p2 = half;
1116 } else if (half % 2 == 0) {
1117 *p0 = 2;
1118 *p1 = half / 2;
1119 *p2 = 2;
1120 } else if (half % 3 == 0) {
1121 *p0 = 3;
1122 *p1 = half / 3;
1123 *p2 = 2;
1124 } else if (half % 7 == 0) {
1125 *p0 = 7;
1126 *p1 = half / 7;
1127 *p2 = 2;
1128 }
1129 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1130 *p0 = 3;
1131 *p1 = 1;
1132 *p2 = p / 3;
1133 } else if (p == 5 || p == 7) {
1134 *p0 = p;
1135 *p1 = 1;
1136 *p2 = 1;
1137 } else if (p == 15) {
1138 *p0 = 3;
1139 *p1 = 1;
1140 *p2 = 5;
1141 } else if (p == 21) {
1142 *p0 = 7;
1143 *p1 = 1;
1144 *p2 = 3;
1145 } else if (p == 35) {
1146 *p0 = 7;
1147 *p1 = 1;
1148 *p2 = 5;
1149 }
1150 }
1151
1152 struct skl_wrpll_params {
1153 uint32_t dco_fraction;
1154 uint32_t dco_integer;
1155 uint32_t qdiv_ratio;
1156 uint32_t qdiv_mode;
1157 uint32_t kdiv;
1158 uint32_t pdiv;
1159 uint32_t central_freq;
1160 };
1161
1162 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1163 uint64_t afe_clock,
1164 uint64_t central_freq,
1165 uint32_t p0, uint32_t p1, uint32_t p2)
1166 {
1167 uint64_t dco_freq;
1168
1169 switch (central_freq) {
1170 case 9600000000ULL:
1171 params->central_freq = 0;
1172 break;
1173 case 9000000000ULL:
1174 params->central_freq = 1;
1175 break;
1176 case 8400000000ULL:
1177 params->central_freq = 3;
1178 }
1179
1180 switch (p0) {
1181 case 1:
1182 params->pdiv = 0;
1183 break;
1184 case 2:
1185 params->pdiv = 1;
1186 break;
1187 case 3:
1188 params->pdiv = 2;
1189 break;
1190 case 7:
1191 params->pdiv = 4;
1192 break;
1193 default:
1194 WARN(1, "Incorrect PDiv\n");
1195 }
1196
1197 switch (p2) {
1198 case 5:
1199 params->kdiv = 0;
1200 break;
1201 case 2:
1202 params->kdiv = 1;
1203 break;
1204 case 3:
1205 params->kdiv = 2;
1206 break;
1207 case 1:
1208 params->kdiv = 3;
1209 break;
1210 default:
1211 WARN(1, "Incorrect KDiv\n");
1212 }
1213
1214 params->qdiv_ratio = p1;
1215 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1216
1217 dco_freq = p0 * p1 * p2 * afe_clock;
1218
1219 /*
1220 * Intermediate values are in Hz.
1221 * Divide by MHz to match bsepc
1222 */
1223 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1224 params->dco_fraction =
1225 div_u64((div_u64(dco_freq, 24) -
1226 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1227 }
1228
1229 static bool
1230 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1231 struct skl_wrpll_params *wrpll_params)
1232 {
1233 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1234 uint64_t dco_central_freq[3] = {8400000000ULL,
1235 9000000000ULL,
1236 9600000000ULL};
1237 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1238 24, 28, 30, 32, 36, 40, 42, 44,
1239 48, 52, 54, 56, 60, 64, 66, 68,
1240 70, 72, 76, 78, 80, 84, 88, 90,
1241 92, 96, 98 };
1242 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1243 static const struct {
1244 const int *list;
1245 int n_dividers;
1246 } dividers[] = {
1247 { even_dividers, ARRAY_SIZE(even_dividers) },
1248 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1249 };
1250 struct skl_wrpll_context ctx;
1251 unsigned int dco, d, i;
1252 unsigned int p0, p1, p2;
1253
1254 skl_wrpll_context_init(&ctx);
1255
1256 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1257 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1258 for (i = 0; i < dividers[d].n_dividers; i++) {
1259 unsigned int p = dividers[d].list[i];
1260 uint64_t dco_freq = p * afe_clock;
1261
1262 skl_wrpll_try_divider(&ctx,
1263 dco_central_freq[dco],
1264 dco_freq,
1265 p);
1266 /*
1267 * Skip the remaining dividers if we're sure to
1268 * have found the definitive divider, we can't
1269 * improve a 0 deviation.
1270 */
1271 if (ctx.min_deviation == 0)
1272 goto skip_remaining_dividers;
1273 }
1274 }
1275
1276 skip_remaining_dividers:
1277 /*
1278 * If a solution is found with an even divider, prefer
1279 * this one.
1280 */
1281 if (d == 0 && ctx.p)
1282 break;
1283 }
1284
1285 if (!ctx.p) {
1286 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1287 return false;
1288 }
1289
1290 /*
1291 * gcc incorrectly analyses that these can be used without being
1292 * initialized. To be fair, it's hard to guess.
1293 */
1294 p0 = p1 = p2 = 0;
1295 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1296 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1297 p0, p1, p2);
1298
1299 return true;
1300 }
1301
1302 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
1303 struct intel_crtc_state *crtc_state,
1304 int clock)
1305 {
1306 uint32_t ctrl1, cfgcr1, cfgcr2;
1307 struct skl_wrpll_params wrpll_params = { 0, };
1308
1309 /*
1310 * See comment in intel_dpll_hw_state to understand why we always use 0
1311 * as the DPLL id in this function.
1312 */
1313 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1314
1315 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1316
1317 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1318 return false;
1319
1320 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1321 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1322 wrpll_params.dco_integer;
1323
1324 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1325 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1326 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1327 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1328 wrpll_params.central_freq;
1329
1330 memset(&crtc_state->dpll_hw_state, 0,
1331 sizeof(crtc_state->dpll_hw_state));
1332
1333 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1334 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1335 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1336 return true;
1337 }
1338
1339 static bool
1340 skl_ddi_dp_set_dpll_hw_state(int clock,
1341 struct intel_dpll_hw_state *dpll_hw_state)
1342 {
1343 uint32_t ctrl1;
1344
1345 /*
1346 * See comment in intel_dpll_hw_state to understand why we always use 0
1347 * as the DPLL id in this function.
1348 */
1349 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1350 switch (clock / 2) {
1351 case 81000:
1352 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1353 break;
1354 case 135000:
1355 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1356 break;
1357 case 270000:
1358 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1359 break;
1360 /* eDP 1.4 rates */
1361 case 162000:
1362 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1363 break;
1364 case 108000:
1365 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1366 break;
1367 case 216000:
1368 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1369 break;
1370 }
1371
1372 dpll_hw_state->ctrl1 = ctrl1;
1373 return true;
1374 }
1375
1376 static struct intel_shared_dpll *
1377 skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1378 struct intel_encoder *encoder)
1379 {
1380 struct intel_shared_dpll *pll;
1381 int clock = crtc_state->port_clock;
1382 bool bret;
1383 struct intel_dpll_hw_state dpll_hw_state;
1384
1385 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
1386
1387 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1388 bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
1389 if (!bret) {
1390 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1391 return NULL;
1392 }
1393 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1394 bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
1395 if (!bret) {
1396 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1397 return NULL;
1398 }
1399 crtc_state->dpll_hw_state = dpll_hw_state;
1400 } else {
1401 return NULL;
1402 }
1403
1404 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1405 pll = intel_find_shared_dpll(crtc, crtc_state,
1406 DPLL_ID_SKL_DPLL0,
1407 DPLL_ID_SKL_DPLL0);
1408 else
1409 pll = intel_find_shared_dpll(crtc, crtc_state,
1410 DPLL_ID_SKL_DPLL1,
1411 DPLL_ID_SKL_DPLL3);
1412 if (!pll)
1413 return NULL;
1414
1415 intel_reference_shared_dpll(pll, crtc_state);
1416
1417 return pll;
1418 }
1419
1420 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1421 struct intel_dpll_hw_state *hw_state)
1422 {
1423 DRM_DEBUG_KMS("dpll_hw_state: "
1424 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1425 hw_state->ctrl1,
1426 hw_state->cfgcr1,
1427 hw_state->cfgcr2);
1428 }
1429
1430 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1431 .enable = skl_ddi_pll_enable,
1432 .disable = skl_ddi_pll_disable,
1433 .get_hw_state = skl_ddi_pll_get_hw_state,
1434 };
1435
1436 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1437 .enable = skl_ddi_dpll0_enable,
1438 .disable = skl_ddi_dpll0_disable,
1439 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1440 };
1441
1442 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1443 struct intel_shared_dpll *pll)
1444 {
1445 uint32_t temp;
1446 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1447 enum dpio_phy phy;
1448 enum dpio_channel ch;
1449
1450 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1451
1452 /* Non-SSC reference */
1453 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1454 temp |= PORT_PLL_REF_SEL;
1455 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1456
1457 if (IS_GEMINILAKE(dev_priv)) {
1458 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1459 temp |= PORT_PLL_POWER_ENABLE;
1460 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1461
1462 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1463 PORT_PLL_POWER_STATE), 200))
1464 DRM_ERROR("Power state not set for PLL:%d\n", port);
1465 }
1466
1467 /* Disable 10 bit clock */
1468 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1469 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1470 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1471
1472 /* Write P1 & P2 */
1473 temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1474 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1475 temp |= pll->state.hw_state.ebb0;
1476 I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
1477
1478 /* Write M2 integer */
1479 temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1480 temp &= ~PORT_PLL_M2_MASK;
1481 temp |= pll->state.hw_state.pll0;
1482 I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
1483
1484 /* Write N */
1485 temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1486 temp &= ~PORT_PLL_N_MASK;
1487 temp |= pll->state.hw_state.pll1;
1488 I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
1489
1490 /* Write M2 fraction */
1491 temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1492 temp &= ~PORT_PLL_M2_FRAC_MASK;
1493 temp |= pll->state.hw_state.pll2;
1494 I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
1495
1496 /* Write M2 fraction enable */
1497 temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1498 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1499 temp |= pll->state.hw_state.pll3;
1500 I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
1501
1502 /* Write coeff */
1503 temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1504 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1505 temp &= ~PORT_PLL_INT_COEFF_MASK;
1506 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1507 temp |= pll->state.hw_state.pll6;
1508 I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
1509
1510 /* Write calibration val */
1511 temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1512 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1513 temp |= pll->state.hw_state.pll8;
1514 I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
1515
1516 temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1517 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1518 temp |= pll->state.hw_state.pll9;
1519 I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
1520
1521 temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1522 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1523 temp &= ~PORT_PLL_DCO_AMP_MASK;
1524 temp |= pll->state.hw_state.pll10;
1525 I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
1526
1527 /* Recalibrate with new settings */
1528 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1529 temp |= PORT_PLL_RECALIBRATE;
1530 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1531 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1532 temp |= pll->state.hw_state.ebb4;
1533 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1534
1535 /* Enable PLL */
1536 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1537 temp |= PORT_PLL_ENABLE;
1538 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1539 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1540
1541 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1542 200))
1543 DRM_ERROR("PLL %d not locked\n", port);
1544
1545 if (IS_GEMINILAKE(dev_priv)) {
1546 temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
1547 temp |= DCC_DELAY_RANGE_2;
1548 I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
1549 }
1550
1551 /*
1552 * While we write to the group register to program all lanes at once we
1553 * can read only lane registers and we pick lanes 0/1 for that.
1554 */
1555 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1556 temp &= ~LANE_STAGGER_MASK;
1557 temp &= ~LANESTAGGER_STRAP_OVRD;
1558 temp |= pll->state.hw_state.pcsdw12;
1559 I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
1560 }
1561
1562 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1563 struct intel_shared_dpll *pll)
1564 {
1565 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1566 uint32_t temp;
1567
1568 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1569 temp &= ~PORT_PLL_ENABLE;
1570 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1571 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1572
1573 if (IS_GEMINILAKE(dev_priv)) {
1574 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1575 temp &= ~PORT_PLL_POWER_ENABLE;
1576 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1577
1578 if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1579 PORT_PLL_POWER_STATE), 200))
1580 DRM_ERROR("Power state not reset for PLL:%d\n", port);
1581 }
1582 }
1583
1584 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1585 struct intel_shared_dpll *pll,
1586 struct intel_dpll_hw_state *hw_state)
1587 {
1588 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1589 uint32_t val;
1590 bool ret;
1591 enum dpio_phy phy;
1592 enum dpio_channel ch;
1593
1594 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1595
1596 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1597 return false;
1598
1599 ret = false;
1600
1601 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1602 if (!(val & PORT_PLL_ENABLE))
1603 goto out;
1604
1605 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1606 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1607
1608 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1609 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1610
1611 hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1612 hw_state->pll0 &= PORT_PLL_M2_MASK;
1613
1614 hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1615 hw_state->pll1 &= PORT_PLL_N_MASK;
1616
1617 hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1618 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1619
1620 hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1621 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1622
1623 hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1624 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1625 PORT_PLL_INT_COEFF_MASK |
1626 PORT_PLL_GAIN_CTL_MASK;
1627
1628 hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1629 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1630
1631 hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1632 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1633
1634 hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1635 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1636 PORT_PLL_DCO_AMP_MASK;
1637
1638 /*
1639 * While we write to the group register to program all lanes at once we
1640 * can read only lane registers. We configure all lanes the same way, so
1641 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1642 */
1643 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1644 if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
1645 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1646 hw_state->pcsdw12,
1647 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
1648 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1649
1650 ret = true;
1651
1652 out:
1653 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1654
1655 return ret;
1656 }
1657
1658 /* bxt clock parameters */
1659 struct bxt_clk_div {
1660 int clock;
1661 uint32_t p1;
1662 uint32_t p2;
1663 uint32_t m2_int;
1664 uint32_t m2_frac;
1665 bool m2_frac_en;
1666 uint32_t n;
1667
1668 int vco;
1669 };
1670
1671 /* pre-calculated values for DP linkrates */
1672 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1673 {162000, 4, 2, 32, 1677722, 1, 1},
1674 {270000, 4, 1, 27, 0, 0, 1},
1675 {540000, 2, 1, 27, 0, 0, 1},
1676 {216000, 3, 2, 32, 1677722, 1, 1},
1677 {243000, 4, 1, 24, 1258291, 1, 1},
1678 {324000, 4, 1, 32, 1677722, 1, 1},
1679 {432000, 3, 1, 32, 1677722, 1, 1}
1680 };
1681
1682 static bool
1683 bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
1684 struct intel_crtc_state *crtc_state, int clock,
1685 struct bxt_clk_div *clk_div)
1686 {
1687 struct dpll best_clock;
1688
1689 /* Calculate HDMI div */
1690 /*
1691 * FIXME: tie the following calculation into
1692 * i9xx_crtc_compute_clock
1693 */
1694 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1695 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1696 clock, pipe_name(intel_crtc->pipe));
1697 return false;
1698 }
1699
1700 clk_div->p1 = best_clock.p1;
1701 clk_div->p2 = best_clock.p2;
1702 WARN_ON(best_clock.m1 != 2);
1703 clk_div->n = best_clock.n;
1704 clk_div->m2_int = best_clock.m2 >> 22;
1705 clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
1706 clk_div->m2_frac_en = clk_div->m2_frac != 0;
1707
1708 clk_div->vco = best_clock.vco;
1709
1710 return true;
1711 }
1712
1713 static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
1714 {
1715 int i;
1716
1717 *clk_div = bxt_dp_clk_val[0];
1718 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1719 if (bxt_dp_clk_val[i].clock == clock) {
1720 *clk_div = bxt_dp_clk_val[i];
1721 break;
1722 }
1723 }
1724
1725 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1726 }
1727
1728 static bool bxt_ddi_set_dpll_hw_state(int clock,
1729 struct bxt_clk_div *clk_div,
1730 struct intel_dpll_hw_state *dpll_hw_state)
1731 {
1732 int vco = clk_div->vco;
1733 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1734 uint32_t lanestagger;
1735
1736 if (vco >= 6200000 && vco <= 6700000) {
1737 prop_coef = 4;
1738 int_coef = 9;
1739 gain_ctl = 3;
1740 targ_cnt = 8;
1741 } else if ((vco > 5400000 && vco < 6200000) ||
1742 (vco >= 4800000 && vco < 5400000)) {
1743 prop_coef = 5;
1744 int_coef = 11;
1745 gain_ctl = 3;
1746 targ_cnt = 9;
1747 } else if (vco == 5400000) {
1748 prop_coef = 3;
1749 int_coef = 8;
1750 gain_ctl = 1;
1751 targ_cnt = 9;
1752 } else {
1753 DRM_ERROR("Invalid VCO\n");
1754 return false;
1755 }
1756
1757 if (clock > 270000)
1758 lanestagger = 0x18;
1759 else if (clock > 135000)
1760 lanestagger = 0x0d;
1761 else if (clock > 67000)
1762 lanestagger = 0x07;
1763 else if (clock > 33000)
1764 lanestagger = 0x04;
1765 else
1766 lanestagger = 0x02;
1767
1768 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
1769 dpll_hw_state->pll0 = clk_div->m2_int;
1770 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1771 dpll_hw_state->pll2 = clk_div->m2_frac;
1772
1773 if (clk_div->m2_frac_en)
1774 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
1775
1776 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
1777 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
1778
1779 dpll_hw_state->pll8 = targ_cnt;
1780
1781 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1782
1783 dpll_hw_state->pll10 =
1784 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1785 | PORT_PLL_DCO_AMP_OVR_EN_H;
1786
1787 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1788
1789 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
1790
1791 return true;
1792 }
1793
1794 static bool
1795 bxt_ddi_dp_set_dpll_hw_state(int clock,
1796 struct intel_dpll_hw_state *dpll_hw_state)
1797 {
1798 struct bxt_clk_div clk_div = {0};
1799
1800 bxt_ddi_dp_pll_dividers(clock, &clk_div);
1801
1802 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1803 }
1804
1805 static bool
1806 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc,
1807 struct intel_crtc_state *crtc_state, int clock,
1808 struct intel_dpll_hw_state *dpll_hw_state)
1809 {
1810 struct bxt_clk_div clk_div = { };
1811
1812 bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div);
1813
1814 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1815 }
1816
1817 static struct intel_shared_dpll *
1818 bxt_get_dpll(struct intel_crtc *crtc,
1819 struct intel_crtc_state *crtc_state,
1820 struct intel_encoder *encoder)
1821 {
1822 struct intel_dpll_hw_state dpll_hw_state = { };
1823 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1824 struct intel_shared_dpll *pll;
1825 int i, clock = crtc_state->port_clock;
1826
1827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1828 !bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock,
1829 &dpll_hw_state))
1830 return NULL;
1831
1832 if (intel_crtc_has_dp_encoder(crtc_state) &&
1833 !bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
1834 return NULL;
1835
1836 memset(&crtc_state->dpll_hw_state, 0,
1837 sizeof(crtc_state->dpll_hw_state));
1838
1839 crtc_state->dpll_hw_state = dpll_hw_state;
1840
1841 /* 1:1 mapping between ports and PLLs */
1842 i = (enum intel_dpll_id) encoder->port;
1843 pll = intel_get_shared_dpll_by_id(dev_priv, i);
1844
1845 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1846 crtc->base.base.id, crtc->base.name, pll->info->name);
1847
1848 intel_reference_shared_dpll(pll, crtc_state);
1849
1850 return pll;
1851 }
1852
1853 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
1854 struct intel_dpll_hw_state *hw_state)
1855 {
1856 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
1857 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1858 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1859 hw_state->ebb0,
1860 hw_state->ebb4,
1861 hw_state->pll0,
1862 hw_state->pll1,
1863 hw_state->pll2,
1864 hw_state->pll3,
1865 hw_state->pll6,
1866 hw_state->pll8,
1867 hw_state->pll9,
1868 hw_state->pll10,
1869 hw_state->pcsdw12);
1870 }
1871
1872 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1873 .enable = bxt_ddi_pll_enable,
1874 .disable = bxt_ddi_pll_disable,
1875 .get_hw_state = bxt_ddi_pll_get_hw_state,
1876 };
1877
1878 static void intel_ddi_pll_init(struct drm_device *dev)
1879 {
1880 struct drm_i915_private *dev_priv = to_i915(dev);
1881
1882 if (INTEL_GEN(dev_priv) < 9) {
1883 uint32_t val = I915_READ(LCPLL_CTL);
1884
1885 /*
1886 * The LCPLL register should be turned on by the BIOS. For now
1887 * let's just check its state and print errors in case
1888 * something is wrong. Don't even try to turn it on.
1889 */
1890
1891 if (val & LCPLL_CD_SOURCE_FCLK)
1892 DRM_ERROR("CDCLK source is not LCPLL\n");
1893
1894 if (val & LCPLL_PLL_DISABLE)
1895 DRM_ERROR("LCPLL is disabled\n");
1896 }
1897 }
1898
1899 struct intel_dpll_mgr {
1900 const struct dpll_info *dpll_info;
1901
1902 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
1903 struct intel_crtc_state *crtc_state,
1904 struct intel_encoder *encoder);
1905
1906 void (*dump_hw_state)(struct drm_i915_private *dev_priv,
1907 struct intel_dpll_hw_state *hw_state);
1908 };
1909
1910 static const struct dpll_info pch_plls[] = {
1911 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
1912 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
1913 { },
1914 };
1915
1916 static const struct intel_dpll_mgr pch_pll_mgr = {
1917 .dpll_info = pch_plls,
1918 .get_dpll = ibx_get_dpll,
1919 .dump_hw_state = ibx_dump_hw_state,
1920 };
1921
1922 static const struct dpll_info hsw_plls[] = {
1923 { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
1924 { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
1925 { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
1926 { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON },
1927 { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1928 { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1929 { },
1930 };
1931
1932 static const struct intel_dpll_mgr hsw_pll_mgr = {
1933 .dpll_info = hsw_plls,
1934 .get_dpll = hsw_get_dpll,
1935 .dump_hw_state = hsw_dump_hw_state,
1936 };
1937
1938 static const struct dpll_info skl_plls[] = {
1939 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1940 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1941 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1942 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
1943 { },
1944 };
1945
1946 static const struct intel_dpll_mgr skl_pll_mgr = {
1947 .dpll_info = skl_plls,
1948 .get_dpll = skl_get_dpll,
1949 .dump_hw_state = skl_dump_hw_state,
1950 };
1951
1952 static const struct dpll_info bxt_plls[] = {
1953 { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
1954 { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1955 { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1956 { },
1957 };
1958
1959 static const struct intel_dpll_mgr bxt_pll_mgr = {
1960 .dpll_info = bxt_plls,
1961 .get_dpll = bxt_get_dpll,
1962 .dump_hw_state = bxt_dump_hw_state,
1963 };
1964
1965 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1966 struct intel_shared_dpll *pll)
1967 {
1968 const enum intel_dpll_id id = pll->info->id;
1969 uint32_t val;
1970
1971 /* 1. Enable DPLL power in DPLL_ENABLE. */
1972 val = I915_READ(CNL_DPLL_ENABLE(id));
1973 val |= PLL_POWER_ENABLE;
1974 I915_WRITE(CNL_DPLL_ENABLE(id), val);
1975
1976 /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
1977 if (intel_wait_for_register(dev_priv,
1978 CNL_DPLL_ENABLE(id),
1979 PLL_POWER_STATE,
1980 PLL_POWER_STATE,
1981 5))
1982 DRM_ERROR("PLL %d Power not enabled\n", id);
1983
1984 /*
1985 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
1986 * select DP mode, and set DP link rate.
1987 */
1988 val = pll->state.hw_state.cfgcr0;
1989 I915_WRITE(CNL_DPLL_CFGCR0(id), val);
1990
1991 /* 4. Reab back to ensure writes completed */
1992 POSTING_READ(CNL_DPLL_CFGCR0(id));
1993
1994 /* 3. Configure DPLL_CFGCR0 */
1995 /* Avoid touch CFGCR1 if HDMI mode is not enabled */
1996 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1997 val = pll->state.hw_state.cfgcr1;
1998 I915_WRITE(CNL_DPLL_CFGCR1(id), val);
1999 /* 4. Reab back to ensure writes completed */
2000 POSTING_READ(CNL_DPLL_CFGCR1(id));
2001 }
2002
2003 /*
2004 * 5. If the frequency will result in a change to the voltage
2005 * requirement, follow the Display Voltage Frequency Switching
2006 * Sequence Before Frequency Change
2007 *
2008 * Note: DVFS is actually handled via the cdclk code paths,
2009 * hence we do nothing here.
2010 */
2011
2012 /* 6. Enable DPLL in DPLL_ENABLE. */
2013 val = I915_READ(CNL_DPLL_ENABLE(id));
2014 val |= PLL_ENABLE;
2015 I915_WRITE(CNL_DPLL_ENABLE(id), val);
2016
2017 /* 7. Wait for PLL lock status in DPLL_ENABLE. */
2018 if (intel_wait_for_register(dev_priv,
2019 CNL_DPLL_ENABLE(id),
2020 PLL_LOCK,
2021 PLL_LOCK,
2022 5))
2023 DRM_ERROR("PLL %d not locked\n", id);
2024
2025 /*
2026 * 8. If the frequency will result in a change to the voltage
2027 * requirement, follow the Display Voltage Frequency Switching
2028 * Sequence After Frequency Change
2029 *
2030 * Note: DVFS is actually handled via the cdclk code paths,
2031 * hence we do nothing here.
2032 */
2033
2034 /*
2035 * 9. turn on the clock for the DDI and map the DPLL to the DDI
2036 * Done at intel_ddi_clk_select
2037 */
2038 }
2039
2040 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2041 struct intel_shared_dpll *pll)
2042 {
2043 const enum intel_dpll_id id = pll->info->id;
2044 uint32_t val;
2045
2046 /*
2047 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
2048 * Done at intel_ddi_post_disable
2049 */
2050
2051 /*
2052 * 2. If the frequency will result in a change to the voltage
2053 * requirement, follow the Display Voltage Frequency Switching
2054 * Sequence Before Frequency Change
2055 *
2056 * Note: DVFS is actually handled via the cdclk code paths,
2057 * hence we do nothing here.
2058 */
2059
2060 /* 3. Disable DPLL through DPLL_ENABLE. */
2061 val = I915_READ(CNL_DPLL_ENABLE(id));
2062 val &= ~PLL_ENABLE;
2063 I915_WRITE(CNL_DPLL_ENABLE(id), val);
2064
2065 /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
2066 if (intel_wait_for_register(dev_priv,
2067 CNL_DPLL_ENABLE(id),
2068 PLL_LOCK,
2069 0,
2070 5))
2071 DRM_ERROR("PLL %d locked\n", id);
2072
2073 /*
2074 * 5. If the frequency will result in a change to the voltage
2075 * requirement, follow the Display Voltage Frequency Switching
2076 * Sequence After Frequency Change
2077 *
2078 * Note: DVFS is actually handled via the cdclk code paths,
2079 * hence we do nothing here.
2080 */
2081
2082 /* 6. Disable DPLL power in DPLL_ENABLE. */
2083 val = I915_READ(CNL_DPLL_ENABLE(id));
2084 val &= ~PLL_POWER_ENABLE;
2085 I915_WRITE(CNL_DPLL_ENABLE(id), val);
2086
2087 /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
2088 if (intel_wait_for_register(dev_priv,
2089 CNL_DPLL_ENABLE(id),
2090 PLL_POWER_STATE,
2091 0,
2092 5))
2093 DRM_ERROR("PLL %d Power not disabled\n", id);
2094 }
2095
2096 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2097 struct intel_shared_dpll *pll,
2098 struct intel_dpll_hw_state *hw_state)
2099 {
2100 const enum intel_dpll_id id = pll->info->id;
2101 uint32_t val;
2102 bool ret;
2103
2104 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
2105 return false;
2106
2107 ret = false;
2108
2109 val = I915_READ(CNL_DPLL_ENABLE(id));
2110 if (!(val & PLL_ENABLE))
2111 goto out;
2112
2113 val = I915_READ(CNL_DPLL_CFGCR0(id));
2114 hw_state->cfgcr0 = val;
2115
2116 /* avoid reading back stale values if HDMI mode is not enabled */
2117 if (val & DPLL_CFGCR0_HDMI_MODE) {
2118 hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
2119 }
2120 ret = true;
2121
2122 out:
2123 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2124
2125 return ret;
2126 }
2127
2128 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2129 int *qdiv, int *kdiv)
2130 {
2131 /* even dividers */
2132 if (bestdiv % 2 == 0) {
2133 if (bestdiv == 2) {
2134 *pdiv = 2;
2135 *qdiv = 1;
2136 *kdiv = 1;
2137 } else if (bestdiv % 4 == 0) {
2138 *pdiv = 2;
2139 *qdiv = bestdiv / 4;
2140 *kdiv = 2;
2141 } else if (bestdiv % 6 == 0) {
2142 *pdiv = 3;
2143 *qdiv = bestdiv / 6;
2144 *kdiv = 2;
2145 } else if (bestdiv % 5 == 0) {
2146 *pdiv = 5;
2147 *qdiv = bestdiv / 10;
2148 *kdiv = 2;
2149 } else if (bestdiv % 14 == 0) {
2150 *pdiv = 7;
2151 *qdiv = bestdiv / 14;
2152 *kdiv = 2;
2153 }
2154 } else {
2155 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2156 *pdiv = bestdiv;
2157 *qdiv = 1;
2158 *kdiv = 1;
2159 } else { /* 9, 15, 21 */
2160 *pdiv = bestdiv / 3;
2161 *qdiv = 1;
2162 *kdiv = 3;
2163 }
2164 }
2165 }
2166
2167 static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
2168 u32 dco_freq, u32 ref_freq,
2169 int pdiv, int qdiv, int kdiv)
2170 {
2171 u32 dco;
2172
2173 switch (kdiv) {
2174 case 1:
2175 params->kdiv = 1;
2176 break;
2177 case 2:
2178 params->kdiv = 2;
2179 break;
2180 case 3:
2181 params->kdiv = 4;
2182 break;
2183 default:
2184 WARN(1, "Incorrect KDiv\n");
2185 }
2186
2187 switch (pdiv) {
2188 case 2:
2189 params->pdiv = 1;
2190 break;
2191 case 3:
2192 params->pdiv = 2;
2193 break;
2194 case 5:
2195 params->pdiv = 4;
2196 break;
2197 case 7:
2198 params->pdiv = 8;
2199 break;
2200 default:
2201 WARN(1, "Incorrect PDiv\n");
2202 }
2203
2204 WARN_ON(kdiv != 2 && qdiv != 1);
2205
2206 params->qdiv_ratio = qdiv;
2207 params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2208
2209 dco = div_u64((u64)dco_freq << 15, ref_freq);
2210
2211 params->dco_integer = dco >> 15;
2212 params->dco_fraction = dco & 0x7fff;
2213 }
2214
2215 static bool
2216 cnl_ddi_calculate_wrpll(int clock,
2217 struct drm_i915_private *dev_priv,
2218 struct skl_wrpll_params *wrpll_params)
2219 {
2220 u32 afe_clock = clock * 5;
2221 uint32_t ref_clock;
2222 u32 dco_min = 7998000;
2223 u32 dco_max = 10000000;
2224 u32 dco_mid = (dco_min + dco_max) / 2;
2225 static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
2226 18, 20, 24, 28, 30, 32, 36, 40,
2227 42, 44, 48, 50, 52, 54, 56, 60,
2228 64, 66, 68, 70, 72, 76, 78, 80,
2229 84, 88, 90, 92, 96, 98, 100, 102,
2230 3, 5, 7, 9, 15, 21 };
2231 u32 dco, best_dco = 0, dco_centrality = 0;
2232 u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2233 int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2234
2235 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2236 dco = afe_clock * dividers[d];
2237
2238 if ((dco <= dco_max) && (dco >= dco_min)) {
2239 dco_centrality = abs(dco - dco_mid);
2240
2241 if (dco_centrality < best_dco_centrality) {
2242 best_dco_centrality = dco_centrality;
2243 best_div = dividers[d];
2244 best_dco = dco;
2245 }
2246 }
2247 }
2248
2249 if (best_div == 0)
2250 return false;
2251
2252 cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2253
2254 ref_clock = dev_priv->cdclk.hw.ref;
2255
2256 /*
2257 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
2258 * because the DPLL automatically divides that by 2.
2259 */
2260 if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
2261 ref_clock = 19200;
2262
2263 cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
2264 kdiv);
2265
2266 return true;
2267 }
2268
2269 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
2270 struct intel_crtc_state *crtc_state,
2271 int clock)
2272 {
2273 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2274 uint32_t cfgcr0, cfgcr1;
2275 struct skl_wrpll_params wrpll_params = { 0, };
2276
2277 cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2278
2279 if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
2280 return false;
2281
2282 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2283 wrpll_params.dco_integer;
2284
2285 cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
2286 DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
2287 DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
2288 DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
2289 DPLL_CFGCR1_CENTRAL_FREQ;
2290
2291 memset(&crtc_state->dpll_hw_state, 0,
2292 sizeof(crtc_state->dpll_hw_state));
2293
2294 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2295 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
2296 return true;
2297 }
2298
2299 static bool
2300 cnl_ddi_dp_set_dpll_hw_state(int clock,
2301 struct intel_dpll_hw_state *dpll_hw_state)
2302 {
2303 uint32_t cfgcr0;
2304
2305 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
2306
2307 switch (clock / 2) {
2308 case 81000:
2309 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
2310 break;
2311 case 135000:
2312 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
2313 break;
2314 case 270000:
2315 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
2316 break;
2317 /* eDP 1.4 rates */
2318 case 162000:
2319 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
2320 break;
2321 case 108000:
2322 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
2323 break;
2324 case 216000:
2325 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
2326 break;
2327 case 324000:
2328 /* Some SKUs may require elevated I/O voltage to support this */
2329 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
2330 break;
2331 case 405000:
2332 /* Some SKUs may require elevated I/O voltage to support this */
2333 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
2334 break;
2335 }
2336
2337 dpll_hw_state->cfgcr0 = cfgcr0;
2338 return true;
2339 }
2340
2341 static struct intel_shared_dpll *
2342 cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2343 struct intel_encoder *encoder)
2344 {
2345 struct intel_shared_dpll *pll;
2346 int clock = crtc_state->port_clock;
2347 bool bret;
2348 struct intel_dpll_hw_state dpll_hw_state;
2349
2350 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
2351
2352 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2353 bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
2354 if (!bret) {
2355 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
2356 return NULL;
2357 }
2358 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
2359 bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
2360 if (!bret) {
2361 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
2362 return NULL;
2363 }
2364 crtc_state->dpll_hw_state = dpll_hw_state;
2365 } else {
2366 DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
2367 crtc_state->output_types);
2368 return NULL;
2369 }
2370
2371 pll = intel_find_shared_dpll(crtc, crtc_state,
2372 DPLL_ID_SKL_DPLL0,
2373 DPLL_ID_SKL_DPLL2);
2374 if (!pll) {
2375 DRM_DEBUG_KMS("No PLL selected\n");
2376 return NULL;
2377 }
2378
2379 intel_reference_shared_dpll(pll, crtc_state);
2380
2381 return pll;
2382 }
2383
2384 static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
2385 struct intel_dpll_hw_state *hw_state)
2386 {
2387 DRM_DEBUG_KMS("dpll_hw_state: "
2388 "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
2389 hw_state->cfgcr0,
2390 hw_state->cfgcr1);
2391 }
2392
2393 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
2394 .enable = cnl_ddi_pll_enable,
2395 .disable = cnl_ddi_pll_disable,
2396 .get_hw_state = cnl_ddi_pll_get_hw_state,
2397 };
2398
2399 static const struct dpll_info cnl_plls[] = {
2400 { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2401 { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2402 { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2403 { },
2404 };
2405
2406 static const struct intel_dpll_mgr cnl_pll_mgr = {
2407 .dpll_info = cnl_plls,
2408 .get_dpll = cnl_get_dpll,
2409 .dump_hw_state = cnl_dump_hw_state,
2410 };
2411
2412 /*
2413 * These values alrea already adjusted: they're the bits we write to the
2414 * registers, not the logical values.
2415 */
2416 static const struct skl_wrpll_params icl_dp_combo_pll_24MHz_values[] = {
2417 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
2418 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2419 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
2420 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2421 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
2422 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2423 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
2424 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2425 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [4]: 2.16 */
2426 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
2427 { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [5]: 4.32 */
2428 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2429 { .dco_integer = 0x195, .dco_fraction = 0x0000, /* [6]: 6.48 */
2430 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2431 { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
2432 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2433 };
2434
2435 /* Also used for 38.4 MHz values. */
2436 static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
2437 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
2438 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2439 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
2440 .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2441 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
2442 .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2443 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
2444 .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2445 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [4]: 2.16 */
2446 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
2447 { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [5]: 4.32 */
2448 .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2449 { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
2450 .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2451 { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
2452 .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2453 };
2454
2455 static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
2456 struct skl_wrpll_params *pll_params)
2457 {
2458 const struct skl_wrpll_params *params;
2459
2460 params = dev_priv->cdclk.hw.ref == 24000 ?
2461 icl_dp_combo_pll_24MHz_values :
2462 icl_dp_combo_pll_19_2MHz_values;
2463
2464 switch (clock) {
2465 case 540000:
2466 *pll_params = params[0];
2467 break;
2468 case 270000:
2469 *pll_params = params[1];
2470 break;
2471 case 162000:
2472 *pll_params = params[2];
2473 break;
2474 case 324000:
2475 *pll_params = params[3];
2476 break;
2477 case 216000:
2478 *pll_params = params[4];
2479 break;
2480 case 432000:
2481 *pll_params = params[5];
2482 break;
2483 case 648000:
2484 *pll_params = params[6];
2485 break;
2486 case 810000:
2487 *pll_params = params[7];
2488 break;
2489 default:
2490 MISSING_CASE(clock);
2491 return false;
2492 }
2493
2494 return true;
2495 }
2496
2497 static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
2498 struct intel_encoder *encoder, int clock,
2499 struct intel_dpll_hw_state *pll_state)
2500 {
2501 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2502 uint32_t cfgcr0, cfgcr1;
2503 struct skl_wrpll_params pll_params = { 0 };
2504 bool ret;
2505
2506 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2507 ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
2508 else
2509 ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
2510
2511 if (!ret)
2512 return false;
2513
2514 cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
2515 pll_params.dco_integer;
2516
2517 cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
2518 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
2519 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
2520 DPLL_CFGCR1_PDIV(pll_params.pdiv) |
2521 DPLL_CFGCR1_CENTRAL_FREQ_8400;
2522
2523 pll_state->cfgcr0 = cfgcr0;
2524 pll_state->cfgcr1 = cfgcr1;
2525 return true;
2526 }
2527
2528 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
2529 uint32_t pll_id)
2530 {
2531 uint32_t cfgcr0, cfgcr1;
2532 uint32_t pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
2533 const struct skl_wrpll_params *params;
2534 int index, n_entries, link_clock;
2535
2536 /* Read back values from DPLL CFGCR registers */
2537 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
2538 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
2539
2540 dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
2541 dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2542 DPLL_CFGCR0_DCO_FRACTION_SHIFT;
2543 pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;
2544 kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;
2545 qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
2546 DPLL_CFGCR1_QDIV_MODE_SHIFT;
2547 qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2548 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2549
2550 params = dev_priv->cdclk.hw.ref == 24000 ?
2551 icl_dp_combo_pll_24MHz_values :
2552 icl_dp_combo_pll_19_2MHz_values;
2553 n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
2554
2555 for (index = 0; index < n_entries; index++) {
2556 if (dco_integer == params[index].dco_integer &&
2557 dco_fraction == params[index].dco_fraction &&
2558 pdiv == params[index].pdiv &&
2559 kdiv == params[index].kdiv &&
2560 qdiv_mode == params[index].qdiv_mode &&
2561 qdiv_ratio == params[index].qdiv_ratio)
2562 break;
2563 }
2564
2565 /* Map PLL Index to Link Clock */
2566 switch (index) {
2567 default:
2568 MISSING_CASE(index);
2569 /* fall through */
2570 case 0:
2571 link_clock = 540000;
2572 break;
2573 case 1:
2574 link_clock = 270000;
2575 break;
2576 case 2:
2577 link_clock = 162000;
2578 break;
2579 case 3:
2580 link_clock = 324000;
2581 break;
2582 case 4:
2583 link_clock = 216000;
2584 break;
2585 case 5:
2586 link_clock = 432000;
2587 break;
2588 case 6:
2589 link_clock = 648000;
2590 break;
2591 case 7:
2592 link_clock = 810000;
2593 break;
2594 }
2595
2596 return link_clock;
2597 }
2598
2599 static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
2600 {
2601 return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
2602 }
2603
2604 static enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
2605 {
2606 return port - PORT_C + DPLL_ID_ICL_MGPLL1;
2607 }
2608
2609 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2610 uint32_t *target_dco_khz,
2611 struct intel_dpll_hw_state *state)
2612 {
2613 uint32_t dco_min_freq, dco_max_freq;
2614 int div1_vals[] = {7, 5, 3, 2};
2615 unsigned int i;
2616 int div2;
2617
2618 dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2619 dco_max_freq = is_dp ? 8100000 : 10000000;
2620
2621 for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2622 int div1 = div1_vals[i];
2623
2624 for (div2 = 10; div2 > 0; div2--) {
2625 int dco = div1 * div2 * clock_khz * 5;
2626 int a_divratio, tlinedrv, inputsel, hsdiv;
2627
2628 if (dco < dco_min_freq || dco > dco_max_freq)
2629 continue;
2630
2631 if (div2 >= 2) {
2632 a_divratio = is_dp ? 10 : 5;
2633 tlinedrv = 2;
2634 } else {
2635 a_divratio = 5;
2636 tlinedrv = 0;
2637 }
2638 inputsel = is_dp ? 0 : 1;
2639
2640 switch (div1) {
2641 default:
2642 MISSING_CASE(div1);
2643 /* fall through */
2644 case 2:
2645 hsdiv = 0;
2646 break;
2647 case 3:
2648 hsdiv = 1;
2649 break;
2650 case 5:
2651 hsdiv = 2;
2652 break;
2653 case 7:
2654 hsdiv = 3;
2655 break;
2656 }
2657
2658 *target_dco_khz = dco;
2659
2660 state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2661
2662 state->mg_clktop2_coreclkctl1 =
2663 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2664
2665 state->mg_clktop2_hsclkctl =
2666 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2667 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2668 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |
2669 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2670
2671 return true;
2672 }
2673 }
2674
2675 return false;
2676 }
2677
2678 /*
2679 * The specification for this function uses real numbers, so the math had to be
2680 * adapted to integer-only calculation, that's why it looks so different.
2681 */
2682 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2683 struct intel_encoder *encoder, int clock,
2684 struct intel_dpll_hw_state *pll_state)
2685 {
2686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2687 int refclk_khz = dev_priv->cdclk.hw.ref;
2688 uint32_t dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
2689 uint32_t iref_ndiv, iref_trim, iref_pulse_w;
2690 uint32_t prop_coeff, int_coeff;
2691 uint32_t tdc_targetcnt, feedfwgain;
2692 uint64_t ssc_stepsize, ssc_steplen, ssc_steplog;
2693 uint64_t tmp;
2694 bool use_ssc = false;
2695 bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
2696
2697 if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
2698 pll_state)) {
2699 DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
2700 return false;
2701 }
2702
2703 m1div = 2;
2704 m2div_int = dco_khz / (refclk_khz * m1div);
2705 if (m2div_int > 255) {
2706 m1div = 4;
2707 m2div_int = dco_khz / (refclk_khz * m1div);
2708 if (m2div_int > 255) {
2709 DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
2710 clock);
2711 return false;
2712 }
2713 }
2714 m2div_rem = dco_khz % (refclk_khz * m1div);
2715
2716 tmp = (uint64_t)m2div_rem * (1 << 22);
2717 do_div(tmp, refclk_khz * m1div);
2718 m2div_frac = tmp;
2719
2720 switch (refclk_khz) {
2721 case 19200:
2722 iref_ndiv = 1;
2723 iref_trim = 28;
2724 iref_pulse_w = 1;
2725 break;
2726 case 24000:
2727 iref_ndiv = 1;
2728 iref_trim = 25;
2729 iref_pulse_w = 2;
2730 break;
2731 case 38400:
2732 iref_ndiv = 2;
2733 iref_trim = 28;
2734 iref_pulse_w = 1;
2735 break;
2736 default:
2737 MISSING_CASE(refclk_khz);
2738 return false;
2739 }
2740
2741 /*
2742 * tdc_res = 0.000003
2743 * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
2744 *
2745 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
2746 * was supposed to be a division, but we rearranged the operations of
2747 * the formula to avoid early divisions so we don't multiply the
2748 * rounding errors.
2749 *
2750 * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
2751 * we also rearrange to work with integers.
2752 *
2753 * The 0.5 transformed to 5 results in a multiplication by 10 and the
2754 * last division by 10.
2755 */
2756 tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
2757
2758 /*
2759 * Here we divide dco_khz by 10 in order to allow the dividend to fit in
2760 * 32 bits. That's not a problem since we round the division down
2761 * anyway.
2762 */
2763 feedfwgain = (use_ssc || m2div_rem > 0) ?
2764 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
2765
2766 if (dco_khz >= 9000000) {
2767 prop_coeff = 5;
2768 int_coeff = 10;
2769 } else {
2770 prop_coeff = 4;
2771 int_coeff = 8;
2772 }
2773
2774 if (use_ssc) {
2775 tmp = (uint64_t)dco_khz * 47 * 32;
2776 do_div(tmp, refclk_khz * m1div * 10000);
2777 ssc_stepsize = tmp;
2778
2779 tmp = (uint64_t)dco_khz * 1000;
2780 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
2781 } else {
2782 ssc_stepsize = 0;
2783 ssc_steplen = 0;
2784 }
2785 ssc_steplog = 4;
2786
2787 pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
2788 MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
2789 MG_PLL_DIV0_FBDIV_INT(m2div_int);
2790
2791 pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
2792 MG_PLL_DIV1_DITHER_DIV_2 |
2793 MG_PLL_DIV1_NDIVRATIO(1) |
2794 MG_PLL_DIV1_FBPREDIV(m1div);
2795
2796 pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
2797 MG_PLL_LF_AFCCNTSEL_512 |
2798 MG_PLL_LF_GAINCTRL(1) |
2799 MG_PLL_LF_INT_COEFF(int_coeff) |
2800 MG_PLL_LF_PROP_COEFF(prop_coeff);
2801
2802 pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
2803 MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
2804 MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
2805 MG_PLL_FRAC_LOCK_DCODITHEREN |
2806 MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
2807 if (use_ssc || m2div_rem > 0)
2808 pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
2809
2810 pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
2811 MG_PLL_SSC_TYPE(2) |
2812 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
2813 MG_PLL_SSC_STEPNUM(ssc_steplog) |
2814 MG_PLL_SSC_FLLEN |
2815 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
2816
2817 pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
2818 MG_PLL_TDC_COLDST_IREFINT_EN |
2819 MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
2820 MG_PLL_TDC_TDCOVCCORR_EN |
2821 MG_PLL_TDC_TDCSEL(3);
2822
2823 pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
2824 MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
2825 MG_PLL_BIAS_BIAS_BONUS(10) |
2826 MG_PLL_BIAS_BIASCAL_EN |
2827 MG_PLL_BIAS_CTRIM(12) |
2828 MG_PLL_BIAS_VREF_RDAC(4) |
2829 MG_PLL_BIAS_IREFTRIM(iref_trim);
2830
2831 if (refclk_khz == 38400) {
2832 pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
2833 pll_state->mg_pll_bias_mask = 0;
2834 } else {
2835 pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
2836 pll_state->mg_pll_bias_mask = -1U;
2837 }
2838
2839 pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
2840 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
2841
2842 return true;
2843 }
2844
2845 static struct intel_shared_dpll *
2846 icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2847 struct intel_encoder *encoder)
2848 {
2849 struct intel_shared_dpll *pll;
2850 struct intel_dpll_hw_state pll_state = {};
2851 enum port port = encoder->port;
2852 enum intel_dpll_id min, max;
2853 int clock = crtc_state->port_clock;
2854 bool ret;
2855
2856 switch (port) {
2857 case PORT_A:
2858 case PORT_B:
2859 min = DPLL_ID_ICL_DPLL0;
2860 max = DPLL_ID_ICL_DPLL1;
2861 ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2862 &pll_state);
2863 break;
2864 case PORT_C:
2865 case PORT_D:
2866 case PORT_E:
2867 case PORT_F:
2868 if (0 /* TODO: TBT PLLs */) {
2869 min = DPLL_ID_ICL_TBTPLL;
2870 max = min;
2871 ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2872 &pll_state);
2873 } else {
2874 min = icl_port_to_mg_pll_id(port);
2875 max = min;
2876 ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
2877 &pll_state);
2878 }
2879 break;
2880 default:
2881 MISSING_CASE(port);
2882 return NULL;
2883 }
2884
2885 if (!ret) {
2886 DRM_DEBUG_KMS("Could not calculate PLL state.\n");
2887 return NULL;
2888 }
2889
2890 crtc_state->dpll_hw_state = pll_state;
2891
2892 pll = intel_find_shared_dpll(crtc, crtc_state, min, max);
2893 if (!pll) {
2894 DRM_DEBUG_KMS("No PLL selected\n");
2895 return NULL;
2896 }
2897
2898 intel_reference_shared_dpll(pll, crtc_state);
2899
2900 return pll;
2901 }
2902
2903 static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
2904 {
2905 switch (id) {
2906 default:
2907 MISSING_CASE(id);
2908 /* fall through */
2909 case DPLL_ID_ICL_DPLL0:
2910 case DPLL_ID_ICL_DPLL1:
2911 return CNL_DPLL_ENABLE(id);
2912 case DPLL_ID_ICL_TBTPLL:
2913 return TBT_PLL_ENABLE;
2914 case DPLL_ID_ICL_MGPLL1:
2915 case DPLL_ID_ICL_MGPLL2:
2916 case DPLL_ID_ICL_MGPLL3:
2917 case DPLL_ID_ICL_MGPLL4:
2918 return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
2919 }
2920 }
2921
2922 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
2923 struct intel_shared_dpll *pll,
2924 struct intel_dpll_hw_state *hw_state)
2925 {
2926 const enum intel_dpll_id id = pll->info->id;
2927 uint32_t val;
2928 enum port port;
2929 bool ret = false;
2930
2931 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
2932 return false;
2933
2934 val = I915_READ(icl_pll_id_to_enable_reg(id));
2935 if (!(val & PLL_ENABLE))
2936 goto out;
2937
2938 switch (id) {
2939 case DPLL_ID_ICL_DPLL0:
2940 case DPLL_ID_ICL_DPLL1:
2941 case DPLL_ID_ICL_TBTPLL:
2942 hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
2943 hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
2944 break;
2945 case DPLL_ID_ICL_MGPLL1:
2946 case DPLL_ID_ICL_MGPLL2:
2947 case DPLL_ID_ICL_MGPLL3:
2948 case DPLL_ID_ICL_MGPLL4:
2949 port = icl_mg_pll_id_to_port(id);
2950 hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
2951 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
2952
2953 hw_state->mg_clktop2_coreclkctl1 =
2954 I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
2955 hw_state->mg_clktop2_coreclkctl1 &=
2956 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
2957
2958 hw_state->mg_clktop2_hsclkctl =
2959 I915_READ(MG_CLKTOP2_HSCLKCTL(port));
2960 hw_state->mg_clktop2_hsclkctl &=
2961 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
2962 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
2963 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
2964 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
2965
2966 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
2967 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));
2968 hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
2969 hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
2970 hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
2971
2972 hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
2973 hw_state->mg_pll_tdc_coldst_bias =
2974 I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
2975
2976 if (dev_priv->cdclk.hw.ref == 38400) {
2977 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
2978 hw_state->mg_pll_bias_mask = 0;
2979 } else {
2980 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
2981 hw_state->mg_pll_bias_mask = -1U;
2982 }
2983
2984 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
2985 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
2986 break;
2987 default:
2988 MISSING_CASE(id);
2989 }
2990
2991 ret = true;
2992 out:
2993 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2994 return ret;
2995 }
2996
2997 static void icl_dpll_write(struct drm_i915_private *dev_priv,
2998 struct intel_shared_dpll *pll)
2999 {
3000 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3001 const enum intel_dpll_id id = pll->info->id;
3002
3003 I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
3004 I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
3005 POSTING_READ(ICL_DPLL_CFGCR1(id));
3006 }
3007
3008 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
3009 struct intel_shared_dpll *pll)
3010 {
3011 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3012 enum port port = icl_mg_pll_id_to_port(pll->info->id);
3013 u32 val;
3014
3015 /*
3016 * Some of the following registers have reserved fields, so program
3017 * these with RMW based on a mask. The mask can be fixed or generated
3018 * during the calc/readout phase if the mask depends on some other HW
3019 * state like refclk, see icl_calc_mg_pll_state().
3020 */
3021 val = I915_READ(MG_REFCLKIN_CTL(port));
3022 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3023 val |= hw_state->mg_refclkin_ctl;
3024 I915_WRITE(MG_REFCLKIN_CTL(port), val);
3025
3026 val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
3027 val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3028 val |= hw_state->mg_clktop2_coreclkctl1;
3029 I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port), val);
3030
3031 val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
3032 val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3033 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3034 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3035 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3036 val |= hw_state->mg_clktop2_hsclkctl;
3037 I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), val);
3038
3039 I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0);
3040 I915_WRITE(MG_PLL_DIV1(port), hw_state->mg_pll_div1);
3041 I915_WRITE(MG_PLL_LF(port), hw_state->mg_pll_lf);
3042 I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->mg_pll_frac_lock);
3043 I915_WRITE(MG_PLL_SSC(port), hw_state->mg_pll_ssc);
3044
3045 val = I915_READ(MG_PLL_BIAS(port));
3046 val &= ~hw_state->mg_pll_bias_mask;
3047 val |= hw_state->mg_pll_bias;
3048 I915_WRITE(MG_PLL_BIAS(port), val);
3049
3050 val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
3051 val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
3052 val |= hw_state->mg_pll_tdc_coldst_bias;
3053 I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port), val);
3054
3055 POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));
3056 }
3057
3058 static void icl_pll_enable(struct drm_i915_private *dev_priv,
3059 struct intel_shared_dpll *pll)
3060 {
3061 const enum intel_dpll_id id = pll->info->id;
3062 i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
3063 uint32_t val;
3064
3065 val = I915_READ(enable_reg);
3066 val |= PLL_POWER_ENABLE;
3067 I915_WRITE(enable_reg, val);
3068
3069 /*
3070 * The spec says we need to "wait" but it also says it should be
3071 * immediate.
3072 */
3073 if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
3074 PLL_POWER_STATE, 1))
3075 DRM_ERROR("PLL %d Power not enabled\n", id);
3076
3077 switch (id) {
3078 case DPLL_ID_ICL_DPLL0:
3079 case DPLL_ID_ICL_DPLL1:
3080 case DPLL_ID_ICL_TBTPLL:
3081 icl_dpll_write(dev_priv, pll);
3082 break;
3083 case DPLL_ID_ICL_MGPLL1:
3084 case DPLL_ID_ICL_MGPLL2:
3085 case DPLL_ID_ICL_MGPLL3:
3086 case DPLL_ID_ICL_MGPLL4:
3087 icl_mg_pll_write(dev_priv, pll);
3088 break;
3089 default:
3090 MISSING_CASE(id);
3091 }
3092
3093 /*
3094 * DVFS pre sequence would be here, but in our driver the cdclk code
3095 * paths should already be setting the appropriate voltage, hence we do
3096 * nothign here.
3097 */
3098
3099 val = I915_READ(enable_reg);
3100 val |= PLL_ENABLE;
3101 I915_WRITE(enable_reg, val);
3102
3103 if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
3104 1)) /* 600us actually. */
3105 DRM_ERROR("PLL %d not locked\n", id);
3106
3107 /* DVFS post sequence would be here. See the comment above. */
3108 }
3109
3110 static void icl_pll_disable(struct drm_i915_private *dev_priv,
3111 struct intel_shared_dpll *pll)
3112 {
3113 const enum intel_dpll_id id = pll->info->id;
3114 i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
3115 uint32_t val;
3116
3117 /* The first steps are done by intel_ddi_post_disable(). */
3118
3119 /*
3120 * DVFS pre sequence would be here, but in our driver the cdclk code
3121 * paths should already be setting the appropriate voltage, hence we do
3122 * nothign here.
3123 */
3124
3125 val = I915_READ(enable_reg);
3126 val &= ~PLL_ENABLE;
3127 I915_WRITE(enable_reg, val);
3128
3129 /* Timeout is actually 1us. */
3130 if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
3131 DRM_ERROR("PLL %d locked\n", id);
3132
3133 /* DVFS post sequence would be here. See the comment above. */
3134
3135 val = I915_READ(enable_reg);
3136 val &= ~PLL_POWER_ENABLE;
3137 I915_WRITE(enable_reg, val);
3138
3139 /*
3140 * The spec says we need to "wait" but it also says it should be
3141 * immediate.
3142 */
3143 if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
3144 1))
3145 DRM_ERROR("PLL %d Power not disabled\n", id);
3146 }
3147
3148 static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
3149 struct intel_dpll_hw_state *hw_state)
3150 {
3151 DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
3152 "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
3153 "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
3154 "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
3155 "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
3156 "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
3157 hw_state->cfgcr0, hw_state->cfgcr1,
3158 hw_state->mg_refclkin_ctl,
3159 hw_state->mg_clktop2_coreclkctl1,
3160 hw_state->mg_clktop2_hsclkctl,
3161 hw_state->mg_pll_div0,
3162 hw_state->mg_pll_div1,
3163 hw_state->mg_pll_lf,
3164 hw_state->mg_pll_frac_lock,
3165 hw_state->mg_pll_ssc,
3166 hw_state->mg_pll_bias,
3167 hw_state->mg_pll_tdc_coldst_bias);
3168 }
3169
3170 static const struct intel_shared_dpll_funcs icl_pll_funcs = {
3171 .enable = icl_pll_enable,
3172 .disable = icl_pll_disable,
3173 .get_hw_state = icl_pll_get_hw_state,
3174 };
3175
3176 static const struct dpll_info icl_plls[] = {
3177 { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3178 { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
3179 { "TBT PLL", &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
3180 { "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
3181 { "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
3182 { "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
3183 { "MG PLL 4", &icl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
3184 { },
3185 };
3186
3187 static const struct intel_dpll_mgr icl_pll_mgr = {
3188 .dpll_info = icl_plls,
3189 .get_dpll = icl_get_dpll,
3190 .dump_hw_state = icl_dump_hw_state,
3191 };
3192
3193 /**
3194 * intel_shared_dpll_init - Initialize shared DPLLs
3195 * @dev: drm device
3196 *
3197 * Initialize shared DPLLs for @dev.
3198 */
3199 void intel_shared_dpll_init(struct drm_device *dev)
3200 {
3201 struct drm_i915_private *dev_priv = to_i915(dev);
3202 const struct intel_dpll_mgr *dpll_mgr = NULL;
3203 const struct dpll_info *dpll_info;
3204 int i;
3205
3206 if (IS_ICELAKE(dev_priv))
3207 dpll_mgr = &icl_pll_mgr;
3208 else if (IS_CANNONLAKE(dev_priv))
3209 dpll_mgr = &cnl_pll_mgr;
3210 else if (IS_GEN9_BC(dev_priv))
3211 dpll_mgr = &skl_pll_mgr;
3212 else if (IS_GEN9_LP(dev_priv))
3213 dpll_mgr = &bxt_pll_mgr;
3214 else if (HAS_DDI(dev_priv))
3215 dpll_mgr = &hsw_pll_mgr;
3216 else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
3217 dpll_mgr = &pch_pll_mgr;
3218
3219 if (!dpll_mgr) {
3220 dev_priv->num_shared_dpll = 0;
3221 return;
3222 }
3223
3224 dpll_info = dpll_mgr->dpll_info;
3225
3226 for (i = 0; dpll_info[i].name; i++) {
3227 WARN_ON(i != dpll_info[i].id);
3228 dev_priv->shared_dplls[i].info = &dpll_info[i];
3229 }
3230
3231 dev_priv->dpll_mgr = dpll_mgr;
3232 dev_priv->num_shared_dpll = i;
3233 mutex_init(&dev_priv->dpll_lock);
3234
3235 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
3236
3237 /* FIXME: Move this to a more suitable place */
3238 if (HAS_DDI(dev_priv))
3239 intel_ddi_pll_init(dev);
3240 }
3241
3242 /**
3243 * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination
3244 * @crtc: CRTC
3245 * @crtc_state: atomic state for @crtc
3246 * @encoder: encoder
3247 *
3248 * Find an appropriate DPLL for the given CRTC and encoder combination. A
3249 * reference from the @crtc to the returned pll is registered in the atomic
3250 * state. That configuration is made effective by calling
3251 * intel_shared_dpll_swap_state(). The reference should be released by calling
3252 * intel_release_shared_dpll().
3253 *
3254 * Returns:
3255 * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state.
3256 */
3257 struct intel_shared_dpll *
3258 intel_get_shared_dpll(struct intel_crtc *crtc,
3259 struct intel_crtc_state *crtc_state,
3260 struct intel_encoder *encoder)
3261 {
3262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3263 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3264
3265 if (WARN_ON(!dpll_mgr))
3266 return NULL;
3267
3268 return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
3269 }
3270
3271 /**
3272 * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
3273 * @dpll: dpll in use by @crtc
3274 * @crtc: crtc
3275 * @state: atomic state
3276 *
3277 * This function releases the reference from @crtc to @dpll from the
3278 * atomic @state. The new configuration is made effective by calling
3279 * intel_shared_dpll_swap_state().
3280 */
3281 void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
3282 struct intel_crtc *crtc,
3283 struct drm_atomic_state *state)
3284 {
3285 struct intel_shared_dpll_state *shared_dpll_state;
3286
3287 shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
3288 shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
3289 }
3290
3291 /**
3292 * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
3293 * @dev_priv: i915 drm device
3294 * @hw_state: hw state to be written to the log
3295 *
3296 * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.
3297 */
3298 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
3299 struct intel_dpll_hw_state *hw_state)
3300 {
3301 if (dev_priv->dpll_mgr) {
3302 dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);
3303 } else {
3304 /* fallback for platforms that don't use the shared dpll
3305 * infrastructure
3306 */
3307 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
3308 "fp0: 0x%x, fp1: 0x%x\n",
3309 hw_state->dpll,
3310 hw_state->dpll_md,
3311 hw_state->fp0,
3312 hw_state->fp1);
3313 }
3314 }
Linux with added FPC-III support