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drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_hdmi.c
blob192972a7d287e9fd5ff9aeb599d6730007383500
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include "intel_drv.h"
40 #include <drm/i915_drm.h>
41 #include <drm/intel_lpe_audio.h>
42 #include "i915_drv.h"
43
44 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
45 {
46 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 }
48
49 static void
50 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
51 {
52 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
53 struct drm_i915_private *dev_priv = to_i915(dev);
54 u32 enabled_bits;
55
56 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
57
58 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
59 "HDMI port enabled, expecting disabled\n");
60 }
61
62 static void
63 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
64 enum transcoder cpu_transcoder)
65 {
66 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
67 TRANS_DDI_FUNC_ENABLE,
68 "HDMI transcoder function enabled, expecting disabled\n");
69 }
70
71 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
72 {
73 struct intel_digital_port *intel_dig_port =
74 container_of(encoder, struct intel_digital_port, base.base);
75 return &intel_dig_port->hdmi;
76 }
77
78 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
79 {
80 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
81 }
82
83 static u32 g4x_infoframe_index(unsigned int type)
84 {
85 switch (type) {
86 case HDMI_INFOFRAME_TYPE_AVI:
87 return VIDEO_DIP_SELECT_AVI;
88 case HDMI_INFOFRAME_TYPE_SPD:
89 return VIDEO_DIP_SELECT_SPD;
90 case HDMI_INFOFRAME_TYPE_VENDOR:
91 return VIDEO_DIP_SELECT_VENDOR;
92 default:
93 MISSING_CASE(type);
94 return 0;
95 }
96 }
97
98 static u32 g4x_infoframe_enable(unsigned int type)
99 {
100 switch (type) {
101 case HDMI_INFOFRAME_TYPE_AVI:
102 return VIDEO_DIP_ENABLE_AVI;
103 case HDMI_INFOFRAME_TYPE_SPD:
104 return VIDEO_DIP_ENABLE_SPD;
105 case HDMI_INFOFRAME_TYPE_VENDOR:
106 return VIDEO_DIP_ENABLE_VENDOR;
107 default:
108 MISSING_CASE(type);
109 return 0;
110 }
111 }
112
113 static u32 hsw_infoframe_enable(unsigned int type)
114 {
115 switch (type) {
116 case DP_SDP_VSC:
117 return VIDEO_DIP_ENABLE_VSC_HSW;
118 case HDMI_INFOFRAME_TYPE_AVI:
119 return VIDEO_DIP_ENABLE_AVI_HSW;
120 case HDMI_INFOFRAME_TYPE_SPD:
121 return VIDEO_DIP_ENABLE_SPD_HSW;
122 case HDMI_INFOFRAME_TYPE_VENDOR:
123 return VIDEO_DIP_ENABLE_VS_HSW;
124 default:
125 MISSING_CASE(type);
126 return 0;
127 }
128 }
129
130 static i915_reg_t
131 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
132 enum transcoder cpu_transcoder,
133 unsigned int type,
134 int i)
135 {
136 switch (type) {
137 case DP_SDP_VSC:
138 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
139 case HDMI_INFOFRAME_TYPE_AVI:
140 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
141 case HDMI_INFOFRAME_TYPE_SPD:
142 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
143 case HDMI_INFOFRAME_TYPE_VENDOR:
144 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
145 default:
146 MISSING_CASE(type);
147 return INVALID_MMIO_REG;
148 }
149 }
150
151 static void g4x_write_infoframe(struct drm_encoder *encoder,
152 const struct intel_crtc_state *crtc_state,
153 unsigned int type,
154 const void *frame, ssize_t len)
155 {
156 const u32 *data = frame;
157 struct drm_device *dev = encoder->dev;
158 struct drm_i915_private *dev_priv = to_i915(dev);
159 u32 val = I915_READ(VIDEO_DIP_CTL);
160 int i;
161
162 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
163
164 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
165 val |= g4x_infoframe_index(type);
166
167 val &= ~g4x_infoframe_enable(type);
168
169 I915_WRITE(VIDEO_DIP_CTL, val);
170
171 mmiowb();
172 for (i = 0; i < len; i += 4) {
173 I915_WRITE(VIDEO_DIP_DATA, *data);
174 data++;
175 }
176 /* Write every possible data byte to force correct ECC calculation. */
177 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
178 I915_WRITE(VIDEO_DIP_DATA, 0);
179 mmiowb();
180
181 val |= g4x_infoframe_enable(type);
182 val &= ~VIDEO_DIP_FREQ_MASK;
183 val |= VIDEO_DIP_FREQ_VSYNC;
184
185 I915_WRITE(VIDEO_DIP_CTL, val);
186 POSTING_READ(VIDEO_DIP_CTL);
187 }
188
189 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
190 const struct intel_crtc_state *pipe_config)
191 {
192 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
193 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
194 u32 val = I915_READ(VIDEO_DIP_CTL);
195
196 if ((val & VIDEO_DIP_ENABLE) == 0)
197 return false;
198
199 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
200 return false;
201
202 return val & (VIDEO_DIP_ENABLE_AVI |
203 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
204 }
205
206 static void ibx_write_infoframe(struct drm_encoder *encoder,
207 const struct intel_crtc_state *crtc_state,
208 unsigned int type,
209 const void *frame, ssize_t len)
210 {
211 const u32 *data = frame;
212 struct drm_device *dev = encoder->dev;
213 struct drm_i915_private *dev_priv = to_i915(dev);
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
215 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
216 u32 val = I915_READ(reg);
217 int i;
218
219 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
220
221 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
222 val |= g4x_infoframe_index(type);
223
224 val &= ~g4x_infoframe_enable(type);
225
226 I915_WRITE(reg, val);
227
228 mmiowb();
229 for (i = 0; i < len; i += 4) {
230 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
231 data++;
232 }
233 /* Write every possible data byte to force correct ECC calculation. */
234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
235 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
236 mmiowb();
237
238 val |= g4x_infoframe_enable(type);
239 val &= ~VIDEO_DIP_FREQ_MASK;
240 val |= VIDEO_DIP_FREQ_VSYNC;
241
242 I915_WRITE(reg, val);
243 POSTING_READ(reg);
244 }
245
246 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
247 const struct intel_crtc_state *pipe_config)
248 {
249 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
250 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
251 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
252 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
253 u32 val = I915_READ(reg);
254
255 if ((val & VIDEO_DIP_ENABLE) == 0)
256 return false;
257
258 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
259 return false;
260
261 return val & (VIDEO_DIP_ENABLE_AVI |
262 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
263 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
264 }
265
266 static void cpt_write_infoframe(struct drm_encoder *encoder,
267 const struct intel_crtc_state *crtc_state,
268 unsigned int type,
269 const void *frame, ssize_t len)
270 {
271 const u32 *data = frame;
272 struct drm_device *dev = encoder->dev;
273 struct drm_i915_private *dev_priv = to_i915(dev);
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
275 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
276 u32 val = I915_READ(reg);
277 int i;
278
279 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
280
281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
282 val |= g4x_infoframe_index(type);
283
284 /* The DIP control register spec says that we need to update the AVI
285 * infoframe without clearing its enable bit */
286 if (type != HDMI_INFOFRAME_TYPE_AVI)
287 val &= ~g4x_infoframe_enable(type);
288
289 I915_WRITE(reg, val);
290
291 mmiowb();
292 for (i = 0; i < len; i += 4) {
293 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
294 data++;
295 }
296 /* Write every possible data byte to force correct ECC calculation. */
297 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
298 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
299 mmiowb();
300
301 val |= g4x_infoframe_enable(type);
302 val &= ~VIDEO_DIP_FREQ_MASK;
303 val |= VIDEO_DIP_FREQ_VSYNC;
304
305 I915_WRITE(reg, val);
306 POSTING_READ(reg);
307 }
308
309 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
310 const struct intel_crtc_state *pipe_config)
311 {
312 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
313 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
314 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
315
316 if ((val & VIDEO_DIP_ENABLE) == 0)
317 return false;
318
319 return val & (VIDEO_DIP_ENABLE_AVI |
320 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
321 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
322 }
323
324 static void vlv_write_infoframe(struct drm_encoder *encoder,
325 const struct intel_crtc_state *crtc_state,
326 unsigned int type,
327 const void *frame, ssize_t len)
328 {
329 const u32 *data = frame;
330 struct drm_device *dev = encoder->dev;
331 struct drm_i915_private *dev_priv = to_i915(dev);
332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
333 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
334 u32 val = I915_READ(reg);
335 int i;
336
337 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
338
339 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
340 val |= g4x_infoframe_index(type);
341
342 val &= ~g4x_infoframe_enable(type);
343
344 I915_WRITE(reg, val);
345
346 mmiowb();
347 for (i = 0; i < len; i += 4) {
348 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
349 data++;
350 }
351 /* Write every possible data byte to force correct ECC calculation. */
352 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
353 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
354 mmiowb();
355
356 val |= g4x_infoframe_enable(type);
357 val &= ~VIDEO_DIP_FREQ_MASK;
358 val |= VIDEO_DIP_FREQ_VSYNC;
359
360 I915_WRITE(reg, val);
361 POSTING_READ(reg);
362 }
363
364 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
365 const struct intel_crtc_state *pipe_config)
366 {
367 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
368 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
369 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
370 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
371
372 if ((val & VIDEO_DIP_ENABLE) == 0)
373 return false;
374
375 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
376 return false;
377
378 return val & (VIDEO_DIP_ENABLE_AVI |
379 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
380 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
381 }
382
383 static void hsw_write_infoframe(struct drm_encoder *encoder,
384 const struct intel_crtc_state *crtc_state,
385 unsigned int type,
386 const void *frame, ssize_t len)
387 {
388 const u32 *data = frame;
389 struct drm_device *dev = encoder->dev;
390 struct drm_i915_private *dev_priv = to_i915(dev);
391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
392 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
393 int data_size = type == DP_SDP_VSC ?
394 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
395 int i;
396 u32 val = I915_READ(ctl_reg);
397
398 val &= ~hsw_infoframe_enable(type);
399 I915_WRITE(ctl_reg, val);
400
401 mmiowb();
402 for (i = 0; i < len; i += 4) {
403 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
404 type, i >> 2), *data);
405 data++;
406 }
407 /* Write every possible data byte to force correct ECC calculation. */
408 for (; i < data_size; i += 4)
409 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
410 type, i >> 2), 0);
411 mmiowb();
412
413 val |= hsw_infoframe_enable(type);
414 I915_WRITE(ctl_reg, val);
415 POSTING_READ(ctl_reg);
416 }
417
418 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
419 const struct intel_crtc_state *pipe_config)
420 {
421 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
422 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
423
424 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
425 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
426 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
427 }
428
429 /*
430 * The data we write to the DIP data buffer registers is 1 byte bigger than the
431 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
432 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
433 * used for both technologies.
434 *
435 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
436 * DW1: DB3 | DB2 | DB1 | DB0
437 * DW2: DB7 | DB6 | DB5 | DB4
438 * DW3: ...
439 *
440 * (HB is Header Byte, DB is Data Byte)
441 *
442 * The hdmi pack() functions don't know about that hardware specific hole so we
443 * trick them by giving an offset into the buffer and moving back the header
444 * bytes by one.
445 */
446 static void intel_write_infoframe(struct drm_encoder *encoder,
447 const struct intel_crtc_state *crtc_state,
448 union hdmi_infoframe *frame)
449 {
450 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
451 u8 buffer[VIDEO_DIP_DATA_SIZE];
452 ssize_t len;
453
454 /* see comment above for the reason for this offset */
455 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
456 if (len < 0)
457 return;
458
459 /* Insert the 'hole' (see big comment above) at position 3 */
460 buffer[0] = buffer[1];
461 buffer[1] = buffer[2];
462 buffer[2] = buffer[3];
463 buffer[3] = 0;
464 len++;
465
466 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
467 }
468
469 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
470 const struct intel_crtc_state *crtc_state,
471 const struct drm_connector_state *conn_state)
472 {
473 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
474 const struct drm_display_mode *adjusted_mode =
475 &crtc_state->base.adjusted_mode;
476 struct drm_connector *connector = &intel_hdmi->attached_connector->base;
477 bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
478 union hdmi_infoframe frame;
479 int ret;
480
481 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
482 adjusted_mode,
483 is_hdmi2_sink);
484 if (ret < 0) {
485 DRM_ERROR("couldn't fill AVI infoframe\n");
486 return;
487 }
488
489 if (crtc_state->ycbcr420)
490 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
491 else
492 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
493
494 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
495 crtc_state->limited_color_range ?
496 HDMI_QUANTIZATION_RANGE_LIMITED :
497 HDMI_QUANTIZATION_RANGE_FULL,
498 intel_hdmi->rgb_quant_range_selectable,
499 is_hdmi2_sink);
500
501 drm_hdmi_avi_infoframe_content_type(&frame.avi,
502 conn_state);
503
504 /* TODO: handle pixel repetition for YCBCR420 outputs */
505 intel_write_infoframe(encoder, crtc_state, &frame);
506 }
507
508 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
509 const struct intel_crtc_state *crtc_state)
510 {
511 union hdmi_infoframe frame;
512 int ret;
513
514 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
515 if (ret < 0) {
516 DRM_ERROR("couldn't fill SPD infoframe\n");
517 return;
518 }
519
520 frame.spd.sdi = HDMI_SPD_SDI_PC;
521
522 intel_write_infoframe(encoder, crtc_state, &frame);
523 }
524
525 static void
526 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
527 const struct intel_crtc_state *crtc_state,
528 const struct drm_connector_state *conn_state)
529 {
530 union hdmi_infoframe frame;
531 int ret;
532
533 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
534 conn_state->connector,
535 &crtc_state->base.adjusted_mode);
536 if (ret < 0)
537 return;
538
539 intel_write_infoframe(encoder, crtc_state, &frame);
540 }
541
542 static void g4x_set_infoframes(struct drm_encoder *encoder,
543 bool enable,
544 const struct intel_crtc_state *crtc_state,
545 const struct drm_connector_state *conn_state)
546 {
547 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
548 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
549 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
550 i915_reg_t reg = VIDEO_DIP_CTL;
551 u32 val = I915_READ(reg);
552 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
553
554 assert_hdmi_port_disabled(intel_hdmi);
555
556 /* If the registers were not initialized yet, they might be zeroes,
557 * which means we're selecting the AVI DIP and we're setting its
558 * frequency to once. This seems to really confuse the HW and make
559 * things stop working (the register spec says the AVI always needs to
560 * be sent every VSync). So here we avoid writing to the register more
561 * than we need and also explicitly select the AVI DIP and explicitly
562 * set its frequency to every VSync. Avoiding to write it twice seems to
563 * be enough to solve the problem, but being defensive shouldn't hurt us
564 * either. */
565 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
566
567 if (!enable) {
568 if (!(val & VIDEO_DIP_ENABLE))
569 return;
570 if (port != (val & VIDEO_DIP_PORT_MASK)) {
571 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
572 (val & VIDEO_DIP_PORT_MASK) >> 29);
573 return;
574 }
575 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
576 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
577 I915_WRITE(reg, val);
578 POSTING_READ(reg);
579 return;
580 }
581
582 if (port != (val & VIDEO_DIP_PORT_MASK)) {
583 if (val & VIDEO_DIP_ENABLE) {
584 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
585 (val & VIDEO_DIP_PORT_MASK) >> 29);
586 return;
587 }
588 val &= ~VIDEO_DIP_PORT_MASK;
589 val |= port;
590 }
591
592 val |= VIDEO_DIP_ENABLE;
593 val &= ~(VIDEO_DIP_ENABLE_AVI |
594 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
595
596 I915_WRITE(reg, val);
597 POSTING_READ(reg);
598
599 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
600 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
601 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
602 }
603
604 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
605 {
606 struct drm_connector *connector = conn_state->connector;
607
608 /*
609 * HDMI cloning is only supported on g4x which doesn't
610 * support deep color or GCP infoframes anyway so no
611 * need to worry about multiple HDMI sinks here.
612 */
613
614 return connector->display_info.bpc > 8;
615 }
616
617 /*
618 * Determine if default_phase=1 can be indicated in the GCP infoframe.
619 *
620 * From HDMI specification 1.4a:
621 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
622 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
623 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
624 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
625 * phase of 0
626 */
627 static bool gcp_default_phase_possible(int pipe_bpp,
628 const struct drm_display_mode *mode)
629 {
630 unsigned int pixels_per_group;
631
632 switch (pipe_bpp) {
633 case 30:
634 /* 4 pixels in 5 clocks */
635 pixels_per_group = 4;
636 break;
637 case 36:
638 /* 2 pixels in 3 clocks */
639 pixels_per_group = 2;
640 break;
641 case 48:
642 /* 1 pixel in 2 clocks */
643 pixels_per_group = 1;
644 break;
645 default:
646 /* phase information not relevant for 8bpc */
647 return false;
648 }
649
650 return mode->crtc_hdisplay % pixels_per_group == 0 &&
651 mode->crtc_htotal % pixels_per_group == 0 &&
652 mode->crtc_hblank_start % pixels_per_group == 0 &&
653 mode->crtc_hblank_end % pixels_per_group == 0 &&
654 mode->crtc_hsync_start % pixels_per_group == 0 &&
655 mode->crtc_hsync_end % pixels_per_group == 0 &&
656 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
657 mode->crtc_htotal/2 % pixels_per_group == 0);
658 }
659
660 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
661 const struct intel_crtc_state *crtc_state,
662 const struct drm_connector_state *conn_state)
663 {
664 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
665 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
666 i915_reg_t reg;
667 u32 val = 0;
668
669 if (HAS_DDI(dev_priv))
670 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
671 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
672 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
673 else if (HAS_PCH_SPLIT(dev_priv))
674 reg = TVIDEO_DIP_GCP(crtc->pipe);
675 else
676 return false;
677
678 /* Indicate color depth whenever the sink supports deep color */
679 if (hdmi_sink_is_deep_color(conn_state))
680 val |= GCP_COLOR_INDICATION;
681
682 /* Enable default_phase whenever the display mode is suitably aligned */
683 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
684 &crtc_state->base.adjusted_mode))
685 val |= GCP_DEFAULT_PHASE_ENABLE;
686
687 I915_WRITE(reg, val);
688
689 return val != 0;
690 }
691
692 static void ibx_set_infoframes(struct drm_encoder *encoder,
693 bool enable,
694 const struct intel_crtc_state *crtc_state,
695 const struct drm_connector_state *conn_state)
696 {
697 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
699 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
700 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
701 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
702 u32 val = I915_READ(reg);
703 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
704
705 assert_hdmi_port_disabled(intel_hdmi);
706
707 /* See the big comment in g4x_set_infoframes() */
708 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
709
710 if (!enable) {
711 if (!(val & VIDEO_DIP_ENABLE))
712 return;
713 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
714 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
715 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
716 I915_WRITE(reg, val);
717 POSTING_READ(reg);
718 return;
719 }
720
721 if (port != (val & VIDEO_DIP_PORT_MASK)) {
722 WARN(val & VIDEO_DIP_ENABLE,
723 "DIP already enabled on port %c\n",
724 (val & VIDEO_DIP_PORT_MASK) >> 29);
725 val &= ~VIDEO_DIP_PORT_MASK;
726 val |= port;
727 }
728
729 val |= VIDEO_DIP_ENABLE;
730 val &= ~(VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
733
734 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
735 val |= VIDEO_DIP_ENABLE_GCP;
736
737 I915_WRITE(reg, val);
738 POSTING_READ(reg);
739
740 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
741 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
742 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
743 }
744
745 static void cpt_set_infoframes(struct drm_encoder *encoder,
746 bool enable,
747 const struct intel_crtc_state *crtc_state,
748 const struct drm_connector_state *conn_state)
749 {
750 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
752 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
753 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
754 u32 val = I915_READ(reg);
755
756 assert_hdmi_port_disabled(intel_hdmi);
757
758 /* See the big comment in g4x_set_infoframes() */
759 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
760
761 if (!enable) {
762 if (!(val & VIDEO_DIP_ENABLE))
763 return;
764 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
765 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
766 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
767 I915_WRITE(reg, val);
768 POSTING_READ(reg);
769 return;
770 }
771
772 /* Set both together, unset both together: see the spec. */
773 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
774 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
775 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
776
777 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
778 val |= VIDEO_DIP_ENABLE_GCP;
779
780 I915_WRITE(reg, val);
781 POSTING_READ(reg);
782
783 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
784 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
785 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
786 }
787
788 static void vlv_set_infoframes(struct drm_encoder *encoder,
789 bool enable,
790 const struct intel_crtc_state *crtc_state,
791 const struct drm_connector_state *conn_state)
792 {
793 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
794 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
796 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
797 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
798 u32 val = I915_READ(reg);
799 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
800
801 assert_hdmi_port_disabled(intel_hdmi);
802
803 /* See the big comment in g4x_set_infoframes() */
804 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
805
806 if (!enable) {
807 if (!(val & VIDEO_DIP_ENABLE))
808 return;
809 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
810 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
811 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
812 I915_WRITE(reg, val);
813 POSTING_READ(reg);
814 return;
815 }
816
817 if (port != (val & VIDEO_DIP_PORT_MASK)) {
818 WARN(val & VIDEO_DIP_ENABLE,
819 "DIP already enabled on port %c\n",
820 (val & VIDEO_DIP_PORT_MASK) >> 29);
821 val &= ~VIDEO_DIP_PORT_MASK;
822 val |= port;
823 }
824
825 val |= VIDEO_DIP_ENABLE;
826 val &= ~(VIDEO_DIP_ENABLE_AVI |
827 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
828 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
829
830 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
831 val |= VIDEO_DIP_ENABLE_GCP;
832
833 I915_WRITE(reg, val);
834 POSTING_READ(reg);
835
836 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
837 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
838 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
839 }
840
841 static void hsw_set_infoframes(struct drm_encoder *encoder,
842 bool enable,
843 const struct intel_crtc_state *crtc_state,
844 const struct drm_connector_state *conn_state)
845 {
846 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
847 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
848 u32 val = I915_READ(reg);
849
850 assert_hdmi_transcoder_func_disabled(dev_priv,
851 crtc_state->cpu_transcoder);
852
853 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
854 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
855 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
856
857 if (!enable) {
858 I915_WRITE(reg, val);
859 POSTING_READ(reg);
860 return;
861 }
862
863 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
864 val |= VIDEO_DIP_ENABLE_GCP_HSW;
865
866 I915_WRITE(reg, val);
867 POSTING_READ(reg);
868
869 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
870 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
871 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
872 }
873
874 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
875 {
876 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
877 struct i2c_adapter *adapter =
878 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
879
880 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
881 return;
882
883 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
884 enable ? "Enabling" : "Disabling");
885
886 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
887 adapter, enable);
888 }
889
890 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
891 unsigned int offset, void *buffer, size_t size)
892 {
893 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
894 struct drm_i915_private *dev_priv =
895 intel_dig_port->base.base.dev->dev_private;
896 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
897 hdmi->ddc_bus);
898 int ret;
899 u8 start = offset & 0xff;
900 struct i2c_msg msgs[] = {
901 {
902 .addr = DRM_HDCP_DDC_ADDR,
903 .flags = 0,
904 .len = 1,
905 .buf = &start,
906 },
907 {
908 .addr = DRM_HDCP_DDC_ADDR,
909 .flags = I2C_M_RD,
910 .len = size,
911 .buf = buffer
912 }
913 };
914 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
915 if (ret == ARRAY_SIZE(msgs))
916 return 0;
917 return ret >= 0 ? -EIO : ret;
918 }
919
920 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
921 unsigned int offset, void *buffer, size_t size)
922 {
923 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
924 struct drm_i915_private *dev_priv =
925 intel_dig_port->base.base.dev->dev_private;
926 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
927 hdmi->ddc_bus);
928 int ret;
929 u8 *write_buf;
930 struct i2c_msg msg;
931
932 write_buf = kzalloc(size + 1, GFP_KERNEL);
933 if (!write_buf)
934 return -ENOMEM;
935
936 write_buf[0] = offset & 0xff;
937 memcpy(&write_buf[1], buffer, size);
938
939 msg.addr = DRM_HDCP_DDC_ADDR;
940 msg.flags = 0,
941 msg.len = size + 1,
942 msg.buf = write_buf;
943
944 ret = i2c_transfer(adapter, &msg, 1);
945 if (ret == 1)
946 ret = 0;
947 else if (ret >= 0)
948 ret = -EIO;
949
950 kfree(write_buf);
951 return ret;
952 }
953
954 static
955 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
956 u8 *an)
957 {
958 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
959 struct drm_i915_private *dev_priv =
960 intel_dig_port->base.base.dev->dev_private;
961 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
962 hdmi->ddc_bus);
963 int ret;
964
965 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
966 DRM_HDCP_AN_LEN);
967 if (ret) {
968 DRM_ERROR("Write An over DDC failed (%d)\n", ret);
969 return ret;
970 }
971
972 ret = intel_gmbus_output_aksv(adapter);
973 if (ret < 0) {
974 DRM_ERROR("Failed to output aksv (%d)\n", ret);
975 return ret;
976 }
977 return 0;
978 }
979
980 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
981 u8 *bksv)
982 {
983 int ret;
984 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
985 DRM_HDCP_KSV_LEN);
986 if (ret)
987 DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret);
988 return ret;
989 }
990
991 static
992 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
993 u8 *bstatus)
994 {
995 int ret;
996 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
997 bstatus, DRM_HDCP_BSTATUS_LEN);
998 if (ret)
999 DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret);
1000 return ret;
1001 }
1002
1003 static
1004 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1005 bool *repeater_present)
1006 {
1007 int ret;
1008 u8 val;
1009
1010 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1011 if (ret) {
1012 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1013 return ret;
1014 }
1015 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1016 return 0;
1017 }
1018
1019 static
1020 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1021 u8 *ri_prime)
1022 {
1023 int ret;
1024 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1025 ri_prime, DRM_HDCP_RI_LEN);
1026 if (ret)
1027 DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret);
1028 return ret;
1029 }
1030
1031 static
1032 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1033 bool *ksv_ready)
1034 {
1035 int ret;
1036 u8 val;
1037
1038 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1039 if (ret) {
1040 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1041 return ret;
1042 }
1043 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1044 return 0;
1045 }
1046
1047 static
1048 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1049 int num_downstream, u8 *ksv_fifo)
1050 {
1051 int ret;
1052 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1053 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1054 if (ret) {
1055 DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret);
1056 return ret;
1057 }
1058 return 0;
1059 }
1060
1061 static
1062 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1063 int i, u32 *part)
1064 {
1065 int ret;
1066
1067 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1068 return -EINVAL;
1069
1070 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1071 part, DRM_HDCP_V_PRIME_PART_LEN);
1072 if (ret)
1073 DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret);
1074 return ret;
1075 }
1076
1077 static
1078 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1079 bool enable)
1080 {
1081 int ret;
1082
1083 if (!enable)
1084 usleep_range(6, 60); /* Bspec says >= 6us */
1085
1086 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1087 if (ret) {
1088 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1089 enable ? "Enable" : "Disable", ret);
1090 return ret;
1091 }
1092 return 0;
1093 }
1094
1095 static
1096 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1097 {
1098 struct drm_i915_private *dev_priv =
1099 intel_dig_port->base.base.dev->dev_private;
1100 enum port port = intel_dig_port->base.port;
1101 int ret;
1102 union {
1103 u32 reg;
1104 u8 shim[DRM_HDCP_RI_LEN];
1105 } ri;
1106
1107 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1108 if (ret)
1109 return false;
1110
1111 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1112
1113 /* Wait for Ri prime match */
1114 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1115 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1116 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1117 I915_READ(PORT_HDCP_STATUS(port)));
1118 return false;
1119 }
1120 return true;
1121 }
1122
1123 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1124 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1125 .read_bksv = intel_hdmi_hdcp_read_bksv,
1126 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1127 .repeater_present = intel_hdmi_hdcp_repeater_present,
1128 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1129 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1130 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1131 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1132 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1133 .check_link = intel_hdmi_hdcp_check_link,
1134 };
1135
1136 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1137 const struct intel_crtc_state *crtc_state)
1138 {
1139 struct drm_device *dev = encoder->base.dev;
1140 struct drm_i915_private *dev_priv = to_i915(dev);
1141 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1142 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1143 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1144 u32 hdmi_val;
1145
1146 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1147
1148 hdmi_val = SDVO_ENCODING_HDMI;
1149 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1150 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1151 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1152 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1153 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1154 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1155
1156 if (crtc_state->pipe_bpp > 24)
1157 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1158 else
1159 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1160
1161 if (crtc_state->has_hdmi_sink)
1162 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1163
1164 if (HAS_PCH_CPT(dev_priv))
1165 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1166 else if (IS_CHERRYVIEW(dev_priv))
1167 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1168 else
1169 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1170
1171 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1172 POSTING_READ(intel_hdmi->hdmi_reg);
1173 }
1174
1175 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1176 enum pipe *pipe)
1177 {
1178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1179 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1180 bool ret;
1181
1182 if (!intel_display_power_get_if_enabled(dev_priv,
1183 encoder->power_domain))
1184 return false;
1185
1186 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1187
1188 intel_display_power_put(dev_priv, encoder->power_domain);
1189
1190 return ret;
1191 }
1192
1193 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1194 struct intel_crtc_state *pipe_config)
1195 {
1196 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1197 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1198 struct drm_device *dev = encoder->base.dev;
1199 struct drm_i915_private *dev_priv = to_i915(dev);
1200 u32 tmp, flags = 0;
1201 int dotclock;
1202
1203 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1204
1205 tmp = I915_READ(intel_hdmi->hdmi_reg);
1206
1207 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1208 flags |= DRM_MODE_FLAG_PHSYNC;
1209 else
1210 flags |= DRM_MODE_FLAG_NHSYNC;
1211
1212 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1213 flags |= DRM_MODE_FLAG_PVSYNC;
1214 else
1215 flags |= DRM_MODE_FLAG_NVSYNC;
1216
1217 if (tmp & HDMI_MODE_SELECT_HDMI)
1218 pipe_config->has_hdmi_sink = true;
1219
1220 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
1221 pipe_config->has_infoframe = true;
1222
1223 if (tmp & SDVO_AUDIO_ENABLE)
1224 pipe_config->has_audio = true;
1225
1226 if (!HAS_PCH_SPLIT(dev_priv) &&
1227 tmp & HDMI_COLOR_RANGE_16_235)
1228 pipe_config->limited_color_range = true;
1229
1230 pipe_config->base.adjusted_mode.flags |= flags;
1231
1232 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1233 dotclock = pipe_config->port_clock * 2 / 3;
1234 else
1235 dotclock = pipe_config->port_clock;
1236
1237 if (pipe_config->pixel_multiplier)
1238 dotclock /= pipe_config->pixel_multiplier;
1239
1240 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1241
1242 pipe_config->lane_count = 4;
1243 }
1244
1245 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1246 const struct intel_crtc_state *pipe_config,
1247 const struct drm_connector_state *conn_state)
1248 {
1249 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1250
1251 WARN_ON(!pipe_config->has_hdmi_sink);
1252 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1253 pipe_name(crtc->pipe));
1254 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1255 }
1256
1257 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1258 const struct intel_crtc_state *pipe_config,
1259 const struct drm_connector_state *conn_state)
1260 {
1261 struct drm_device *dev = encoder->base.dev;
1262 struct drm_i915_private *dev_priv = to_i915(dev);
1263 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1264 u32 temp;
1265
1266 temp = I915_READ(intel_hdmi->hdmi_reg);
1267
1268 temp |= SDVO_ENABLE;
1269 if (pipe_config->has_audio)
1270 temp |= SDVO_AUDIO_ENABLE;
1271
1272 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1273 POSTING_READ(intel_hdmi->hdmi_reg);
1274
1275 if (pipe_config->has_audio)
1276 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1277 }
1278
1279 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1280 const struct intel_crtc_state *pipe_config,
1281 const struct drm_connector_state *conn_state)
1282 {
1283 struct drm_device *dev = encoder->base.dev;
1284 struct drm_i915_private *dev_priv = to_i915(dev);
1285 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1286 u32 temp;
1287
1288 temp = I915_READ(intel_hdmi->hdmi_reg);
1289
1290 temp |= SDVO_ENABLE;
1291 if (pipe_config->has_audio)
1292 temp |= SDVO_AUDIO_ENABLE;
1293
1294 /*
1295 * HW workaround, need to write this twice for issue
1296 * that may result in first write getting masked.
1297 */
1298 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1299 POSTING_READ(intel_hdmi->hdmi_reg);
1300 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1301 POSTING_READ(intel_hdmi->hdmi_reg);
1302
1303 /*
1304 * HW workaround, need to toggle enable bit off and on
1305 * for 12bpc with pixel repeat.
1306 *
1307 * FIXME: BSpec says this should be done at the end of
1308 * of the modeset sequence, so not sure if this isn't too soon.
1309 */
1310 if (pipe_config->pipe_bpp > 24 &&
1311 pipe_config->pixel_multiplier > 1) {
1312 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1313 POSTING_READ(intel_hdmi->hdmi_reg);
1314
1315 /*
1316 * HW workaround, need to write this twice for issue
1317 * that may result in first write getting masked.
1318 */
1319 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1320 POSTING_READ(intel_hdmi->hdmi_reg);
1321 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1322 POSTING_READ(intel_hdmi->hdmi_reg);
1323 }
1324
1325 if (pipe_config->has_audio)
1326 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1327 }
1328
1329 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1330 const struct intel_crtc_state *pipe_config,
1331 const struct drm_connector_state *conn_state)
1332 {
1333 struct drm_device *dev = encoder->base.dev;
1334 struct drm_i915_private *dev_priv = to_i915(dev);
1335 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1336 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1337 enum pipe pipe = crtc->pipe;
1338 u32 temp;
1339
1340 temp = I915_READ(intel_hdmi->hdmi_reg);
1341
1342 temp |= SDVO_ENABLE;
1343 if (pipe_config->has_audio)
1344 temp |= SDVO_AUDIO_ENABLE;
1345
1346 /*
1347 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1348 *
1349 * The procedure for 12bpc is as follows:
1350 * 1. disable HDMI clock gating
1351 * 2. enable HDMI with 8bpc
1352 * 3. enable HDMI with 12bpc
1353 * 4. enable HDMI clock gating
1354 */
1355
1356 if (pipe_config->pipe_bpp > 24) {
1357 I915_WRITE(TRANS_CHICKEN1(pipe),
1358 I915_READ(TRANS_CHICKEN1(pipe)) |
1359 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1360
1361 temp &= ~SDVO_COLOR_FORMAT_MASK;
1362 temp |= SDVO_COLOR_FORMAT_8bpc;
1363 }
1364
1365 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1366 POSTING_READ(intel_hdmi->hdmi_reg);
1367
1368 if (pipe_config->pipe_bpp > 24) {
1369 temp &= ~SDVO_COLOR_FORMAT_MASK;
1370 temp |= HDMI_COLOR_FORMAT_12bpc;
1371
1372 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1373 POSTING_READ(intel_hdmi->hdmi_reg);
1374
1375 I915_WRITE(TRANS_CHICKEN1(pipe),
1376 I915_READ(TRANS_CHICKEN1(pipe)) &
1377 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1378 }
1379
1380 if (pipe_config->has_audio)
1381 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1382 }
1383
1384 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1385 const struct intel_crtc_state *pipe_config,
1386 const struct drm_connector_state *conn_state)
1387 {
1388 }
1389
1390 static void intel_disable_hdmi(struct intel_encoder *encoder,
1391 const struct intel_crtc_state *old_crtc_state,
1392 const struct drm_connector_state *old_conn_state)
1393 {
1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = to_i915(dev);
1396 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1397 struct intel_digital_port *intel_dig_port =
1398 hdmi_to_dig_port(intel_hdmi);
1399 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1400 u32 temp;
1401
1402 temp = I915_READ(intel_hdmi->hdmi_reg);
1403
1404 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1405 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1406 POSTING_READ(intel_hdmi->hdmi_reg);
1407
1408 /*
1409 * HW workaround for IBX, we need to move the port
1410 * to transcoder A after disabling it to allow the
1411 * matching DP port to be enabled on transcoder A.
1412 */
1413 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1414 /*
1415 * We get CPU/PCH FIFO underruns on the other pipe when
1416 * doing the workaround. Sweep them under the rug.
1417 */
1418 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1419 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1420
1421 temp &= ~SDVO_PIPE_SEL_MASK;
1422 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1423 /*
1424 * HW workaround, need to write this twice for issue
1425 * that may result in first write getting masked.
1426 */
1427 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1428 POSTING_READ(intel_hdmi->hdmi_reg);
1429 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1430 POSTING_READ(intel_hdmi->hdmi_reg);
1431
1432 temp &= ~SDVO_ENABLE;
1433 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1434 POSTING_READ(intel_hdmi->hdmi_reg);
1435
1436 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1437 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1438 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1439 }
1440
1441 intel_dig_port->set_infoframes(&encoder->base, false,
1442 old_crtc_state, old_conn_state);
1443
1444 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1445 }
1446
1447 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1448 const struct intel_crtc_state *old_crtc_state,
1449 const struct drm_connector_state *old_conn_state)
1450 {
1451 if (old_crtc_state->has_audio)
1452 intel_audio_codec_disable(encoder,
1453 old_crtc_state, old_conn_state);
1454
1455 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1456 }
1457
1458 static void pch_disable_hdmi(struct intel_encoder *encoder,
1459 const struct intel_crtc_state *old_crtc_state,
1460 const struct drm_connector_state *old_conn_state)
1461 {
1462 if (old_crtc_state->has_audio)
1463 intel_audio_codec_disable(encoder,
1464 old_crtc_state, old_conn_state);
1465 }
1466
1467 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1468 const struct intel_crtc_state *old_crtc_state,
1469 const struct drm_connector_state *old_conn_state)
1470 {
1471 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1472 }
1473
1474 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1475 {
1476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1477 const struct ddi_vbt_port_info *info =
1478 &dev_priv->vbt.ddi_port_info[encoder->port];
1479 int max_tmds_clock;
1480
1481 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1482 max_tmds_clock = 594000;
1483 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1484 max_tmds_clock = 300000;
1485 else if (INTEL_GEN(dev_priv) >= 5)
1486 max_tmds_clock = 225000;
1487 else
1488 max_tmds_clock = 165000;
1489
1490 if (info->max_tmds_clock)
1491 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1492
1493 return max_tmds_clock;
1494 }
1495
1496 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1497 bool respect_downstream_limits,
1498 bool force_dvi)
1499 {
1500 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1501 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1502
1503 if (respect_downstream_limits) {
1504 struct intel_connector *connector = hdmi->attached_connector;
1505 const struct drm_display_info *info = &connector->base.display_info;
1506
1507 if (hdmi->dp_dual_mode.max_tmds_clock)
1508 max_tmds_clock = min(max_tmds_clock,
1509 hdmi->dp_dual_mode.max_tmds_clock);
1510
1511 if (info->max_tmds_clock)
1512 max_tmds_clock = min(max_tmds_clock,
1513 info->max_tmds_clock);
1514 else if (!hdmi->has_hdmi_sink || force_dvi)
1515 max_tmds_clock = min(max_tmds_clock, 165000);
1516 }
1517
1518 return max_tmds_clock;
1519 }
1520
1521 static enum drm_mode_status
1522 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1523 int clock, bool respect_downstream_limits,
1524 bool force_dvi)
1525 {
1526 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1527
1528 if (clock < 25000)
1529 return MODE_CLOCK_LOW;
1530 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1531 return MODE_CLOCK_HIGH;
1532
1533 /* BXT DPLL can't generate 223-240 MHz */
1534 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1535 return MODE_CLOCK_RANGE;
1536
1537 /* CHV DPLL can't generate 216-240 MHz */
1538 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1539 return MODE_CLOCK_RANGE;
1540
1541 return MODE_OK;
1542 }
1543
1544 static enum drm_mode_status
1545 intel_hdmi_mode_valid(struct drm_connector *connector,
1546 struct drm_display_mode *mode)
1547 {
1548 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1549 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1550 struct drm_i915_private *dev_priv = to_i915(dev);
1551 enum drm_mode_status status;
1552 int clock;
1553 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1554 bool force_dvi =
1555 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1556
1557 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1558 return MODE_NO_DBLESCAN;
1559
1560 clock = mode->clock;
1561
1562 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1563 clock *= 2;
1564
1565 if (clock > max_dotclk)
1566 return MODE_CLOCK_HIGH;
1567
1568 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1569 clock *= 2;
1570
1571 if (drm_mode_is_420_only(&connector->display_info, mode))
1572 clock /= 2;
1573
1574 /* check if we can do 8bpc */
1575 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1576
1577 if (hdmi->has_hdmi_sink && !force_dvi) {
1578 /* if we can't do 8bpc we may still be able to do 12bpc */
1579 if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
1580 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1581 true, force_dvi);
1582
1583 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1584 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1585 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1586 true, force_dvi);
1587 }
1588
1589 return status;
1590 }
1591
1592 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1593 int bpc)
1594 {
1595 struct drm_i915_private *dev_priv =
1596 to_i915(crtc_state->base.crtc->dev);
1597 struct drm_atomic_state *state = crtc_state->base.state;
1598 struct drm_connector_state *connector_state;
1599 struct drm_connector *connector;
1600 int i;
1601
1602 if (HAS_GMCH_DISPLAY(dev_priv))
1603 return false;
1604
1605 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1606 return false;
1607
1608 if (crtc_state->pipe_bpp <= 8*3)
1609 return false;
1610
1611 if (!crtc_state->has_hdmi_sink)
1612 return false;
1613
1614 /*
1615 * HDMI deep color affects the clocks, so it's only possible
1616 * when not cloning with other encoder types.
1617 */
1618 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1619 return false;
1620
1621 for_each_new_connector_in_state(state, connector, connector_state, i) {
1622 const struct drm_display_info *info = &connector->display_info;
1623
1624 if (connector_state->crtc != crtc_state->base.crtc)
1625 continue;
1626
1627 if (crtc_state->ycbcr420) {
1628 const struct drm_hdmi_info *hdmi = &info->hdmi;
1629
1630 if (bpc == 12 && !(hdmi->y420_dc_modes &
1631 DRM_EDID_YCBCR420_DC_36))
1632 return false;
1633 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1634 DRM_EDID_YCBCR420_DC_30))
1635 return false;
1636 } else {
1637 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1638 DRM_EDID_HDMI_DC_36))
1639 return false;
1640 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1641 DRM_EDID_HDMI_DC_30))
1642 return false;
1643 }
1644 }
1645
1646 /* Display WA #1139: glk */
1647 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1648 crtc_state->base.adjusted_mode.htotal > 5460)
1649 return false;
1650
1651 return true;
1652 }
1653
1654 static bool
1655 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1656 struct intel_crtc_state *config,
1657 int *clock_12bpc, int *clock_10bpc,
1658 int *clock_8bpc)
1659 {
1660 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1661
1662 if (!connector->ycbcr_420_allowed) {
1663 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1664 return false;
1665 }
1666
1667 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1668 config->port_clock /= 2;
1669 *clock_12bpc /= 2;
1670 *clock_10bpc /= 2;
1671 *clock_8bpc /= 2;
1672 config->ycbcr420 = true;
1673
1674 /* YCBCR 420 output conversion needs a scaler */
1675 if (skl_update_scaler_crtc(config)) {
1676 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1677 return false;
1678 }
1679
1680 intel_pch_panel_fitting(intel_crtc, config,
1681 DRM_MODE_SCALE_FULLSCREEN);
1682
1683 return true;
1684 }
1685
1686 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1687 struct intel_crtc_state *pipe_config,
1688 struct drm_connector_state *conn_state)
1689 {
1690 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1692 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1693 struct drm_connector *connector = conn_state->connector;
1694 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1695 struct intel_digital_connector_state *intel_conn_state =
1696 to_intel_digital_connector_state(conn_state);
1697 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1698 int clock_10bpc = clock_8bpc * 5 / 4;
1699 int clock_12bpc = clock_8bpc * 3 / 2;
1700 int desired_bpp;
1701 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1702
1703 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1704 return false;
1705
1706 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1707
1708 if (pipe_config->has_hdmi_sink)
1709 pipe_config->has_infoframe = true;
1710
1711 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1712 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1713 pipe_config->limited_color_range =
1714 pipe_config->has_hdmi_sink &&
1715 drm_default_rgb_quant_range(adjusted_mode) ==
1716 HDMI_QUANTIZATION_RANGE_LIMITED;
1717 } else {
1718 pipe_config->limited_color_range =
1719 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1720 }
1721
1722 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1723 pipe_config->pixel_multiplier = 2;
1724 clock_8bpc *= 2;
1725 clock_10bpc *= 2;
1726 clock_12bpc *= 2;
1727 }
1728
1729 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1730 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1731 &clock_12bpc, &clock_10bpc,
1732 &clock_8bpc)) {
1733 DRM_ERROR("Can't support YCBCR420 output\n");
1734 return false;
1735 }
1736 }
1737
1738 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1739 pipe_config->has_pch_encoder = true;
1740
1741 if (pipe_config->has_hdmi_sink) {
1742 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1743 pipe_config->has_audio = intel_hdmi->has_audio;
1744 else
1745 pipe_config->has_audio =
1746 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1747 }
1748
1749 /*
1750 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1751 * to check that the higher clock still fits within limits.
1752 */
1753 if (hdmi_deep_color_possible(pipe_config, 12) &&
1754 hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1755 true, force_dvi) == MODE_OK) {
1756 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1757 desired_bpp = 12*3;
1758
1759 /* Need to adjust the port link by 1.5x for 12bpc. */
1760 pipe_config->port_clock = clock_12bpc;
1761 } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1762 hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1763 true, force_dvi) == MODE_OK) {
1764 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1765 desired_bpp = 10 * 3;
1766
1767 /* Need to adjust the port link by 1.25x for 10bpc. */
1768 pipe_config->port_clock = clock_10bpc;
1769 } else {
1770 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1771 desired_bpp = 8*3;
1772
1773 pipe_config->port_clock = clock_8bpc;
1774 }
1775
1776 if (!pipe_config->bw_constrained) {
1777 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1778 pipe_config->pipe_bpp = desired_bpp;
1779 }
1780
1781 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1782 false, force_dvi) != MODE_OK) {
1783 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1784 return false;
1785 }
1786
1787 /* Set user selected PAR to incoming mode's member */
1788 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1789
1790 pipe_config->lane_count = 4;
1791
1792 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1793 IS_GEMINILAKE(dev_priv))) {
1794 if (scdc->scrambling.low_rates)
1795 pipe_config->hdmi_scrambling = true;
1796
1797 if (pipe_config->port_clock > 340000) {
1798 pipe_config->hdmi_scrambling = true;
1799 pipe_config->hdmi_high_tmds_clock_ratio = true;
1800 }
1801 }
1802
1803 return true;
1804 }
1805
1806 static void
1807 intel_hdmi_unset_edid(struct drm_connector *connector)
1808 {
1809 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1810
1811 intel_hdmi->has_hdmi_sink = false;
1812 intel_hdmi->has_audio = false;
1813 intel_hdmi->rgb_quant_range_selectable = false;
1814
1815 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1816 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1817
1818 kfree(to_intel_connector(connector)->detect_edid);
1819 to_intel_connector(connector)->detect_edid = NULL;
1820 }
1821
1822 static void
1823 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1824 {
1825 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1826 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1827 enum port port = hdmi_to_dig_port(hdmi)->base.port;
1828 struct i2c_adapter *adapter =
1829 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1830 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1831
1832 /*
1833 * Type 1 DVI adaptors are not required to implement any
1834 * registers, so we can't always detect their presence.
1835 * Ideally we should be able to check the state of the
1836 * CONFIG1 pin, but no such luck on our hardware.
1837 *
1838 * The only method left to us is to check the VBT to see
1839 * if the port is a dual mode capable DP port. But let's
1840 * only do that when we sucesfully read the EDID, to avoid
1841 * confusing log messages about DP dual mode adaptors when
1842 * there's nothing connected to the port.
1843 */
1844 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1845 /* An overridden EDID imply that we want this port for testing.
1846 * Make sure not to set limits for that port.
1847 */
1848 if (has_edid && !connector->override_edid &&
1849 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1850 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1851 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1852 } else {
1853 type = DRM_DP_DUAL_MODE_NONE;
1854 }
1855 }
1856
1857 if (type == DRM_DP_DUAL_MODE_NONE)
1858 return;
1859
1860 hdmi->dp_dual_mode.type = type;
1861 hdmi->dp_dual_mode.max_tmds_clock =
1862 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1863
1864 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1865 drm_dp_get_dual_mode_type_name(type),
1866 hdmi->dp_dual_mode.max_tmds_clock);
1867 }
1868
1869 static bool
1870 intel_hdmi_set_edid(struct drm_connector *connector)
1871 {
1872 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1873 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1874 struct edid *edid;
1875 bool connected = false;
1876 struct i2c_adapter *i2c;
1877
1878 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1879
1880 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1881
1882 edid = drm_get_edid(connector, i2c);
1883
1884 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1885 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1886 intel_gmbus_force_bit(i2c, true);
1887 edid = drm_get_edid(connector, i2c);
1888 intel_gmbus_force_bit(i2c, false);
1889 }
1890
1891 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1892
1893 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1894
1895 to_intel_connector(connector)->detect_edid = edid;
1896 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1897 intel_hdmi->rgb_quant_range_selectable =
1898 drm_rgb_quant_range_selectable(edid);
1899
1900 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1901 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1902
1903 connected = true;
1904 }
1905
1906 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1907
1908 return connected;
1909 }
1910
1911 static enum drm_connector_status
1912 intel_hdmi_detect(struct drm_connector *connector, bool force)
1913 {
1914 enum drm_connector_status status;
1915 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1916 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1917
1918 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1919 connector->base.id, connector->name);
1920
1921 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1922
1923 intel_hdmi_unset_edid(connector);
1924
1925 if (intel_hdmi_set_edid(connector))
1926 status = connector_status_connected;
1927 else
1928 status = connector_status_disconnected;
1929
1930 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1931
1932 if (status != connector_status_connected)
1933 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1934
1935 return status;
1936 }
1937
1938 static void
1939 intel_hdmi_force(struct drm_connector *connector)
1940 {
1941 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1942 connector->base.id, connector->name);
1943
1944 intel_hdmi_unset_edid(connector);
1945
1946 if (connector->status != connector_status_connected)
1947 return;
1948
1949 intel_hdmi_set_edid(connector);
1950 }
1951
1952 static int intel_hdmi_get_modes(struct drm_connector *connector)
1953 {
1954 struct edid *edid;
1955
1956 edid = to_intel_connector(connector)->detect_edid;
1957 if (edid == NULL)
1958 return 0;
1959
1960 return intel_connector_update_modes(connector, edid);
1961 }
1962
1963 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1964 const struct intel_crtc_state *pipe_config,
1965 const struct drm_connector_state *conn_state)
1966 {
1967 struct intel_digital_port *intel_dig_port =
1968 enc_to_dig_port(&encoder->base);
1969
1970 intel_hdmi_prepare(encoder, pipe_config);
1971
1972 intel_dig_port->set_infoframes(&encoder->base,
1973 pipe_config->has_infoframe,
1974 pipe_config, conn_state);
1975 }
1976
1977 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1978 const struct intel_crtc_state *pipe_config,
1979 const struct drm_connector_state *conn_state)
1980 {
1981 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1983
1984 vlv_phy_pre_encoder_enable(encoder, pipe_config);
1985
1986 /* HDMI 1.0V-2dB */
1987 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1988 0x2b247878);
1989
1990 dport->set_infoframes(&encoder->base,
1991 pipe_config->has_infoframe,
1992 pipe_config, conn_state);
1993
1994 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1995
1996 vlv_wait_port_ready(dev_priv, dport, 0x0);
1997 }
1998
1999 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2000 const struct intel_crtc_state *pipe_config,
2001 const struct drm_connector_state *conn_state)
2002 {
2003 intel_hdmi_prepare(encoder, pipe_config);
2004
2005 vlv_phy_pre_pll_enable(encoder, pipe_config);
2006 }
2007
2008 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2009 const struct intel_crtc_state *pipe_config,
2010 const struct drm_connector_state *conn_state)
2011 {
2012 intel_hdmi_prepare(encoder, pipe_config);
2013
2014 chv_phy_pre_pll_enable(encoder, pipe_config);
2015 }
2016
2017 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2018 const struct intel_crtc_state *old_crtc_state,
2019 const struct drm_connector_state *old_conn_state)
2020 {
2021 chv_phy_post_pll_disable(encoder, old_crtc_state);
2022 }
2023
2024 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2025 const struct intel_crtc_state *old_crtc_state,
2026 const struct drm_connector_state *old_conn_state)
2027 {
2028 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2029 vlv_phy_reset_lanes(encoder, old_crtc_state);
2030 }
2031
2032 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2033 const struct intel_crtc_state *old_crtc_state,
2034 const struct drm_connector_state *old_conn_state)
2035 {
2036 struct drm_device *dev = encoder->base.dev;
2037 struct drm_i915_private *dev_priv = to_i915(dev);
2038
2039 mutex_lock(&dev_priv->sb_lock);
2040
2041 /* Assert data lane reset */
2042 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2043
2044 mutex_unlock(&dev_priv->sb_lock);
2045 }
2046
2047 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2048 const struct intel_crtc_state *pipe_config,
2049 const struct drm_connector_state *conn_state)
2050 {
2051 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2052 struct drm_device *dev = encoder->base.dev;
2053 struct drm_i915_private *dev_priv = to_i915(dev);
2054
2055 chv_phy_pre_encoder_enable(encoder, pipe_config);
2056
2057 /* FIXME: Program the support xxx V-dB */
2058 /* Use 800mV-0dB */
2059 chv_set_phy_signal_level(encoder, 128, 102, false);
2060
2061 dport->set_infoframes(&encoder->base,
2062 pipe_config->has_infoframe,
2063 pipe_config, conn_state);
2064
2065 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2066
2067 vlv_wait_port_ready(dev_priv, dport, 0x0);
2068
2069 /* Second common lane will stay alive on its own now */
2070 chv_phy_release_cl2_override(encoder);
2071 }
2072
2073 static void intel_hdmi_destroy(struct drm_connector *connector)
2074 {
2075 if (intel_attached_hdmi(connector)->cec_notifier)
2076 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2077 kfree(to_intel_connector(connector)->detect_edid);
2078 drm_connector_cleanup(connector);
2079 kfree(connector);
2080 }
2081
2082 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2083 .detect = intel_hdmi_detect,
2084 .force = intel_hdmi_force,
2085 .fill_modes = drm_helper_probe_single_connector_modes,
2086 .atomic_get_property = intel_digital_connector_atomic_get_property,
2087 .atomic_set_property = intel_digital_connector_atomic_set_property,
2088 .late_register = intel_connector_register,
2089 .early_unregister = intel_connector_unregister,
2090 .destroy = intel_hdmi_destroy,
2091 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2092 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2093 };
2094
2095 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2096 .get_modes = intel_hdmi_get_modes,
2097 .mode_valid = intel_hdmi_mode_valid,
2098 .atomic_check = intel_digital_connector_atomic_check,
2099 };
2100
2101 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2102 .destroy = intel_encoder_destroy,
2103 };
2104
2105 static void
2106 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2107 {
2108 intel_attach_force_audio_property(connector);
2109 intel_attach_broadcast_rgb_property(connector);
2110 intel_attach_aspect_ratio_property(connector);
2111 drm_connector_attach_content_type_property(connector);
2112 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2113 }
2114
2115 /*
2116 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2117 * @encoder: intel_encoder
2118 * @connector: drm_connector
2119 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2120 * or reset the high tmds clock ratio for scrambling
2121 * @scrambling: bool to Indicate if the function needs to set or reset
2122 * sink scrambling
2123 *
2124 * This function handles scrambling on HDMI 2.0 capable sinks.
2125 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2126 * it enables scrambling. This should be called before enabling the HDMI
2127 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2128 * detect a scrambled clock within 100 ms.
2129 *
2130 * Returns:
2131 * True on success, false on failure.
2132 */
2133 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2134 struct drm_connector *connector,
2135 bool high_tmds_clock_ratio,
2136 bool scrambling)
2137 {
2138 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2139 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2140 struct drm_scrambling *sink_scrambling =
2141 &connector->display_info.hdmi.scdc.scrambling;
2142 struct i2c_adapter *adapter =
2143 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2144
2145 if (!sink_scrambling->supported)
2146 return true;
2147
2148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2149 connector->base.id, connector->name,
2150 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2151
2152 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2153 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2154 high_tmds_clock_ratio) &&
2155 drm_scdc_set_scrambling(adapter, scrambling);
2156 }
2157
2158 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2159 {
2160 u8 ddc_pin;
2161
2162 switch (port) {
2163 case PORT_B:
2164 ddc_pin = GMBUS_PIN_DPB;
2165 break;
2166 case PORT_C:
2167 ddc_pin = GMBUS_PIN_DPC;
2168 break;
2169 case PORT_D:
2170 ddc_pin = GMBUS_PIN_DPD_CHV;
2171 break;
2172 default:
2173 MISSING_CASE(port);
2174 ddc_pin = GMBUS_PIN_DPB;
2175 break;
2176 }
2177 return ddc_pin;
2178 }
2179
2180 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2181 {
2182 u8 ddc_pin;
2183
2184 switch (port) {
2185 case PORT_B:
2186 ddc_pin = GMBUS_PIN_1_BXT;
2187 break;
2188 case PORT_C:
2189 ddc_pin = GMBUS_PIN_2_BXT;
2190 break;
2191 default:
2192 MISSING_CASE(port);
2193 ddc_pin = GMBUS_PIN_1_BXT;
2194 break;
2195 }
2196 return ddc_pin;
2197 }
2198
2199 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2200 enum port port)
2201 {
2202 u8 ddc_pin;
2203
2204 switch (port) {
2205 case PORT_B:
2206 ddc_pin = GMBUS_PIN_1_BXT;
2207 break;
2208 case PORT_C:
2209 ddc_pin = GMBUS_PIN_2_BXT;
2210 break;
2211 case PORT_D:
2212 ddc_pin = GMBUS_PIN_4_CNP;
2213 break;
2214 case PORT_F:
2215 ddc_pin = GMBUS_PIN_3_BXT;
2216 break;
2217 default:
2218 MISSING_CASE(port);
2219 ddc_pin = GMBUS_PIN_1_BXT;
2220 break;
2221 }
2222 return ddc_pin;
2223 }
2224
2225 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2226 {
2227 u8 ddc_pin;
2228
2229 switch (port) {
2230 case PORT_A:
2231 ddc_pin = GMBUS_PIN_1_BXT;
2232 break;
2233 case PORT_B:
2234 ddc_pin = GMBUS_PIN_2_BXT;
2235 break;
2236 case PORT_C:
2237 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2238 break;
2239 case PORT_D:
2240 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2241 break;
2242 case PORT_E:
2243 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2244 break;
2245 case PORT_F:
2246 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2247 break;
2248 default:
2249 MISSING_CASE(port);
2250 ddc_pin = GMBUS_PIN_2_BXT;
2251 break;
2252 }
2253 return ddc_pin;
2254 }
2255
2256 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2257 enum port port)
2258 {
2259 u8 ddc_pin;
2260
2261 switch (port) {
2262 case PORT_B:
2263 ddc_pin = GMBUS_PIN_DPB;
2264 break;
2265 case PORT_C:
2266 ddc_pin = GMBUS_PIN_DPC;
2267 break;
2268 case PORT_D:
2269 ddc_pin = GMBUS_PIN_DPD;
2270 break;
2271 default:
2272 MISSING_CASE(port);
2273 ddc_pin = GMBUS_PIN_DPB;
2274 break;
2275 }
2276 return ddc_pin;
2277 }
2278
2279 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2280 enum port port)
2281 {
2282 const struct ddi_vbt_port_info *info =
2283 &dev_priv->vbt.ddi_port_info[port];
2284 u8 ddc_pin;
2285
2286 if (info->alternate_ddc_pin) {
2287 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2288 info->alternate_ddc_pin, port_name(port));
2289 return info->alternate_ddc_pin;
2290 }
2291
2292 if (IS_CHERRYVIEW(dev_priv))
2293 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2294 else if (IS_GEN9_LP(dev_priv))
2295 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2296 else if (HAS_PCH_CNP(dev_priv))
2297 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2298 else if (HAS_PCH_ICP(dev_priv))
2299 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2300 else
2301 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2302
2303 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2304 ddc_pin, port_name(port));
2305
2306 return ddc_pin;
2307 }
2308
2309 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2310 {
2311 struct drm_i915_private *dev_priv =
2312 to_i915(intel_dig_port->base.base.dev);
2313
2314 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2315 intel_dig_port->write_infoframe = vlv_write_infoframe;
2316 intel_dig_port->set_infoframes = vlv_set_infoframes;
2317 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2318 } else if (IS_G4X(dev_priv)) {
2319 intel_dig_port->write_infoframe = g4x_write_infoframe;
2320 intel_dig_port->set_infoframes = g4x_set_infoframes;
2321 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2322 } else if (HAS_DDI(dev_priv)) {
2323 intel_dig_port->write_infoframe = hsw_write_infoframe;
2324 intel_dig_port->set_infoframes = hsw_set_infoframes;
2325 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
2326 } else if (HAS_PCH_IBX(dev_priv)) {
2327 intel_dig_port->write_infoframe = ibx_write_infoframe;
2328 intel_dig_port->set_infoframes = ibx_set_infoframes;
2329 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2330 } else {
2331 intel_dig_port->write_infoframe = cpt_write_infoframe;
2332 intel_dig_port->set_infoframes = cpt_set_infoframes;
2333 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2334 }
2335 }
2336
2337 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2338 struct intel_connector *intel_connector)
2339 {
2340 struct drm_connector *connector = &intel_connector->base;
2341 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2342 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2343 struct drm_device *dev = intel_encoder->base.dev;
2344 struct drm_i915_private *dev_priv = to_i915(dev);
2345 enum port port = intel_encoder->port;
2346
2347 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2348 port_name(port));
2349
2350 if (WARN(intel_dig_port->max_lanes < 4,
2351 "Not enough lanes (%d) for HDMI on port %c\n",
2352 intel_dig_port->max_lanes, port_name(port)))
2353 return;
2354
2355 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2356 DRM_MODE_CONNECTOR_HDMIA);
2357 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2358
2359 connector->interlace_allowed = 1;
2360 connector->doublescan_allowed = 0;
2361 connector->stereo_allowed = 1;
2362
2363 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2364 connector->ycbcr_420_allowed = true;
2365
2366 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2367
2368 if (WARN_ON(port == PORT_A))
2369 return;
2370 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2371
2372 if (HAS_DDI(dev_priv))
2373 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2374 else
2375 intel_connector->get_hw_state = intel_connector_get_hw_state;
2376
2377 intel_hdmi_add_properties(intel_hdmi, connector);
2378
2379 if (is_hdcp_supported(dev_priv, port)) {
2380 int ret = intel_hdcp_init(intel_connector,
2381 &intel_hdmi_hdcp_shim);
2382 if (ret)
2383 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2384 }
2385
2386 intel_connector_attach_encoder(intel_connector, intel_encoder);
2387 intel_hdmi->attached_connector = intel_connector;
2388
2389 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2390 * 0xd. Failure to do so will result in spurious interrupts being
2391 * generated on the port when a cable is not attached.
2392 */
2393 if (IS_G45(dev_priv)) {
2394 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2395 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2396 }
2397
2398 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2399 port_identifier(port));
2400 if (!intel_hdmi->cec_notifier)
2401 DRM_DEBUG_KMS("CEC notifier get failed\n");
2402 }
2403
2404 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2405 i915_reg_t hdmi_reg, enum port port)
2406 {
2407 struct intel_digital_port *intel_dig_port;
2408 struct intel_encoder *intel_encoder;
2409 struct intel_connector *intel_connector;
2410
2411 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2412 if (!intel_dig_port)
2413 return;
2414
2415 intel_connector = intel_connector_alloc();
2416 if (!intel_connector) {
2417 kfree(intel_dig_port);
2418 return;
2419 }
2420
2421 intel_encoder = &intel_dig_port->base;
2422
2423 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2424 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2425 "HDMI %c", port_name(port));
2426
2427 intel_encoder->hotplug = intel_encoder_hotplug;
2428 intel_encoder->compute_config = intel_hdmi_compute_config;
2429 if (HAS_PCH_SPLIT(dev_priv)) {
2430 intel_encoder->disable = pch_disable_hdmi;
2431 intel_encoder->post_disable = pch_post_disable_hdmi;
2432 } else {
2433 intel_encoder->disable = g4x_disable_hdmi;
2434 }
2435 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2436 intel_encoder->get_config = intel_hdmi_get_config;
2437 if (IS_CHERRYVIEW(dev_priv)) {
2438 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2439 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2440 intel_encoder->enable = vlv_enable_hdmi;
2441 intel_encoder->post_disable = chv_hdmi_post_disable;
2442 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2443 } else if (IS_VALLEYVIEW(dev_priv)) {
2444 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2445 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2446 intel_encoder->enable = vlv_enable_hdmi;
2447 intel_encoder->post_disable = vlv_hdmi_post_disable;
2448 } else {
2449 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2450 if (HAS_PCH_CPT(dev_priv))
2451 intel_encoder->enable = cpt_enable_hdmi;
2452 else if (HAS_PCH_IBX(dev_priv))
2453 intel_encoder->enable = ibx_enable_hdmi;
2454 else
2455 intel_encoder->enable = g4x_enable_hdmi;
2456 }
2457
2458 intel_encoder->type = INTEL_OUTPUT_HDMI;
2459 intel_encoder->power_domain = intel_port_to_power_domain(port);
2460 intel_encoder->port = port;
2461 if (IS_CHERRYVIEW(dev_priv)) {
2462 if (port == PORT_D)
2463 intel_encoder->crtc_mask = 1 << 2;
2464 else
2465 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2466 } else {
2467 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2468 }
2469 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2470 /*
2471 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2472 * to work on real hardware. And since g4x can send infoframes to
2473 * only one port anyway, nothing is lost by allowing it.
2474 */
2475 if (IS_G4X(dev_priv))
2476 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2477
2478 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2479 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2480 intel_dig_port->max_lanes = 4;
2481
2482 intel_infoframe_init(intel_dig_port);
2483
2484 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2485 }
Linux with added FPC-III support