drm/msm/hdmi: Enable HPD after HDMI IRQ is set up
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvc0_fbcon.c
blobc0deef4fe7274ff5b96ef36aaba8156e161b106c
1 /*
2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
25 #include "nouveau_drv.h"
26 #include "nouveau_dma.h"
27 #include "nouveau_fbcon.h"
28 #include "nouveau_vmm.h"
30 int
31 nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
33 struct nouveau_fbdev *nfbdev = info->par;
34 struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
35 struct nouveau_channel *chan = drm->channel;
36 int ret;
38 ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11);
39 if (ret)
40 return ret;
42 if (rect->rop != ROP_COPY) {
43 BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1);
44 OUT_RING (chan, 1);
46 BEGIN_NVC0(chan, NvSub2D, 0x0588, 1);
47 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
48 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
49 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
50 else
51 OUT_RING (chan, rect->color);
52 BEGIN_NVC0(chan, NvSub2D, 0x0600, 4);
53 OUT_RING (chan, rect->dx);
54 OUT_RING (chan, rect->dy);
55 OUT_RING (chan, rect->dx + rect->width);
56 OUT_RING (chan, rect->dy + rect->height);
57 if (rect->rop != ROP_COPY) {
58 BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1);
59 OUT_RING (chan, 3);
61 FIRE_RING(chan);
62 return 0;
65 int
66 nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
68 struct nouveau_fbdev *nfbdev = info->par;
69 struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
70 struct nouveau_channel *chan = drm->channel;
71 int ret;
73 ret = RING_SPACE(chan, 12);
74 if (ret)
75 return ret;
77 BEGIN_NVC0(chan, NvSub2D, 0x0110, 1);
78 OUT_RING (chan, 0);
79 BEGIN_NVC0(chan, NvSub2D, 0x08b0, 4);
80 OUT_RING (chan, region->dx);
81 OUT_RING (chan, region->dy);
82 OUT_RING (chan, region->width);
83 OUT_RING (chan, region->height);
84 BEGIN_NVC0(chan, NvSub2D, 0x08d0, 4);
85 OUT_RING (chan, 0);
86 OUT_RING (chan, region->sx);
87 OUT_RING (chan, 0);
88 OUT_RING (chan, region->sy);
89 FIRE_RING(chan);
90 return 0;
93 int
94 nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
96 struct nouveau_fbdev *nfbdev = info->par;
97 struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
98 struct nouveau_channel *chan = drm->channel;
99 uint32_t dwords, *data = (uint32_t *)image->data;
100 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
101 uint32_t *palette = info->pseudo_palette;
102 int ret;
104 if (image->depth != 1)
105 return -ENODEV;
107 ret = RING_SPACE(chan, 11);
108 if (ret)
109 return ret;
111 BEGIN_NVC0(chan, NvSub2D, 0x0814, 2);
112 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
113 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
114 OUT_RING (chan, palette[image->bg_color] | mask);
115 OUT_RING (chan, palette[image->fg_color] | mask);
116 } else {
117 OUT_RING (chan, image->bg_color);
118 OUT_RING (chan, image->fg_color);
120 BEGIN_NVC0(chan, NvSub2D, 0x0838, 2);
121 OUT_RING (chan, image->width);
122 OUT_RING (chan, image->height);
123 BEGIN_NVC0(chan, NvSub2D, 0x0850, 4);
124 OUT_RING (chan, 0);
125 OUT_RING (chan, image->dx);
126 OUT_RING (chan, 0);
127 OUT_RING (chan, image->dy);
129 dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
130 while (dwords) {
131 int push = dwords > 2047 ? 2047 : dwords;
133 ret = RING_SPACE(chan, push + 1);
134 if (ret)
135 return ret;
137 dwords -= push;
139 BEGIN_NIC0(chan, NvSub2D, 0x0860, push);
140 OUT_RINGp(chan, data, push);
141 data += push;
144 FIRE_RING(chan);
145 return 0;
149 nvc0_fbcon_accel_init(struct fb_info *info)
151 struct nouveau_fbdev *nfbdev = info->par;
152 struct drm_device *dev = nfbdev->helper.dev;
153 struct nouveau_framebuffer *fb = nouveau_framebuffer(nfbdev->helper.fb);
154 struct nouveau_drm *drm = nouveau_drm(dev);
155 struct nouveau_channel *chan = drm->channel;
156 int ret, format;
158 ret = nvif_object_init(&chan->user, 0x902d, 0x902d, NULL, 0,
159 &nfbdev->twod);
160 if (ret)
161 return ret;
163 switch (info->var.bits_per_pixel) {
164 case 8:
165 format = 0xf3;
166 break;
167 case 15:
168 format = 0xf8;
169 break;
170 case 16:
171 format = 0xe8;
172 break;
173 case 32:
174 switch (info->var.transp.length) {
175 case 0: /* depth 24 */
176 case 8: /* depth 32, just use 24.. */
177 format = 0xe6;
178 break;
179 case 2: /* depth 30 */
180 format = 0xd1;
181 break;
182 default:
183 return -EINVAL;
185 break;
186 default:
187 return -EINVAL;
190 ret = RING_SPACE(chan, 58);
191 if (ret) {
192 WARN_ON(1);
193 nouveau_fbcon_gpu_lockup(info);
194 return ret;
197 BEGIN_NVC0(chan, NvSub2D, 0x0000, 1);
198 OUT_RING (chan, nfbdev->twod.handle);
199 BEGIN_NVC0(chan, NvSub2D, 0x0290, 1);
200 OUT_RING (chan, 0);
201 BEGIN_NVC0(chan, NvSub2D, 0x0888, 1);
202 OUT_RING (chan, 1);
203 BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1);
204 OUT_RING (chan, 3);
205 BEGIN_NVC0(chan, NvSub2D, 0x02a0, 1);
206 OUT_RING (chan, 0x55);
207 BEGIN_NVC0(chan, NvSub2D, 0x08c0, 4);
208 OUT_RING (chan, 0);
209 OUT_RING (chan, 1);
210 OUT_RING (chan, 0);
211 OUT_RING (chan, 1);
212 BEGIN_NVC0(chan, NvSub2D, 0x0580, 2);
213 OUT_RING (chan, 4);
214 OUT_RING (chan, format);
215 BEGIN_NVC0(chan, NvSub2D, 0x02e8, 2);
216 OUT_RING (chan, 2);
217 OUT_RING (chan, 1);
219 BEGIN_NVC0(chan, NvSub2D, 0x0804, 1);
220 OUT_RING (chan, format);
221 BEGIN_NVC0(chan, NvSub2D, 0x0800, 1);
222 OUT_RING (chan, 1);
223 BEGIN_NVC0(chan, NvSub2D, 0x0808, 3);
224 OUT_RING (chan, 0);
225 OUT_RING (chan, 0);
226 OUT_RING (chan, 1);
227 BEGIN_NVC0(chan, NvSub2D, 0x081c, 1);
228 OUT_RING (chan, 1);
229 BEGIN_NVC0(chan, NvSub2D, 0x0840, 4);
230 OUT_RING (chan, 0);
231 OUT_RING (chan, 1);
232 OUT_RING (chan, 0);
233 OUT_RING (chan, 1);
234 BEGIN_NVC0(chan, NvSub2D, 0x0200, 10);
235 OUT_RING (chan, format);
236 OUT_RING (chan, 1);
237 OUT_RING (chan, 0);
238 OUT_RING (chan, 1);
239 OUT_RING (chan, 0);
240 OUT_RING (chan, info->fix.line_length);
241 OUT_RING (chan, info->var.xres_virtual);
242 OUT_RING (chan, info->var.yres_virtual);
243 OUT_RING (chan, upper_32_bits(fb->vma->addr));
244 OUT_RING (chan, lower_32_bits(fb->vma->addr));
245 BEGIN_NVC0(chan, NvSub2D, 0x0230, 10);
246 OUT_RING (chan, format);
247 OUT_RING (chan, 1);
248 OUT_RING (chan, 0);
249 OUT_RING (chan, 1);
250 OUT_RING (chan, 0);
251 OUT_RING (chan, info->fix.line_length);
252 OUT_RING (chan, info->var.xres_virtual);
253 OUT_RING (chan, info->var.yres_virtual);
254 OUT_RING (chan, upper_32_bits(fb->vma->addr));
255 OUT_RING (chan, lower_32_bits(fb->vma->addr));
256 FIRE_RING (chan);
258 return 0;