drivers/gpu/drm/panel/panel-raydium-rm68200.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <philippe.cornu@st.com>
   6  *          Yannick Fertre <yannick.fertre@st.com>
   7  */
   8
   9 #include <linux/backlight.h>
  10 #include <linux/gpio/consumer.h>
  11 #include <linux/regulator/consumer.h>
  12
  13 #include <video/mipi_display.h>
  14
  15 #include <drm/drmP.h>
  16 #include <drm/drm_mipi_dsi.h>
  17 #include <drm/drm_panel.h>
  18
  19 /*** Manufacturer Command Set ***/
  20 #define MCS_CMD_MODE_SW         0xFE /* CMD Mode Switch */
  21 #define MCS_CMD1_UCS            0x00 /* User Command Set (UCS = CMD1) */
  22 #define MCS_CMD2_P0             0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  23 #define MCS_CMD2_P1             0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  24 #define MCS_CMD2_P2             0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  25 #define MCS_CMD2_P3             0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  26
  27 /* CMD2 P0 commands (Display Options and Power) */
  28 #define MCS_STBCTR              0x12 /* TE1 Output Setting Zig-Zag Connection */
  29 #define MCS_SGOPCTR             0x16 /* Source Bias Current */
  30 #define MCS_SDCTR               0x1A /* Source Output Delay Time */
  31 #define MCS_INVCTR              0x1B /* Inversion Type */
  32 #define MCS_EXT_PWR_IC          0x24 /* External PWR IC Control */
  33 #define MCS_SETAVDD             0x27 /* PFM Control for AVDD Output */
  34 #define MCS_SETAVEE             0x29 /* PFM Control for AVEE Output */
  35 #define MCS_BT2CTR              0x2B /* DDVDL Charge Pump Control */
  36 #define MCS_BT3CTR              0x2F /* VGH Charge Pump Control */
  37 #define MCS_BT4CTR              0x34 /* VGL Charge Pump Control */
  38 #define MCS_VCMCTR              0x46 /* VCOM Output Level Control */
  39 #define MCS_SETVGN              0x52 /* VG M/S N Control */
  40 #define MCS_SETVGP              0x54 /* VG M/S P Control */
  41 #define MCS_SW_CTRL             0x5F /* Interface Control for PFM and MIPI */
  42
  43 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  44 #define GOA_VSTV1               0x00
  45 #define GOA_VSTV2               0x07
  46 #define GOA_VCLK1               0x0E
  47 #define GOA_VCLK2               0x17
  48 #define GOA_VCLK_OPT1           0x20
  49 #define GOA_BICLK1              0x2A
  50 #define GOA_BICLK2              0x37
  51 #define GOA_BICLK3              0x44
  52 #define GOA_BICLK4              0x4F
  53 #define GOA_BICLK_OPT1          0x5B
  54 #define GOA_BICLK_OPT2          0x60
  55 #define MCS_GOA_GPO1            0x6D
  56 #define MCS_GOA_GPO2            0x71
  57 #define MCS_GOA_EQ              0x74
  58 #define MCS_GOA_CLK_GALLON      0x7C
  59 #define MCS_GOA_FS_SEL0         0x7E
  60 #define MCS_GOA_FS_SEL1         0x87
  61 #define MCS_GOA_FS_SEL2         0x91
  62 #define MCS_GOA_FS_SEL3         0x9B
  63 #define MCS_GOA_BS_SEL0         0xAC
  64 #define MCS_GOA_BS_SEL1         0xB5
  65 #define MCS_GOA_BS_SEL2         0xBF
  66 #define MCS_GOA_BS_SEL3         0xC9
  67 #define MCS_GOA_BS_SEL4         0xD3
  68
  69 /* CMD2 P3 commands (Gamma) */
  70 #define MCS_GAMMA_VP            0x60 /* Gamma VP1~VP16 */
  71 #define MCS_GAMMA_VN            0x70 /* Gamma VN1~VN16 */
  72
  73 struct rm68200 {
  74         struct device *dev;
  75         struct drm_panel panel;
  76         struct gpio_desc *reset_gpio;
  77         struct regulator *supply;
  78         struct backlight_device *backlight;
  79         bool prepared;
  80         bool enabled;
  81 };
  82
  83 static const struct drm_display_mode default_mode = {
  84         .clock = 52582,
  85         .hdisplay = 720,
  86         .hsync_start = 720 + 38,
  87         .hsync_end = 720 + 38 + 8,
  88         .htotal = 720 + 38 + 8 + 38,
  89         .vdisplay = 1280,
  90         .vsync_start = 1280 + 12,
  91         .vsync_end = 1280 + 12 + 4,
  92         .vtotal = 1280 + 12 + 4 + 12,
  93         .vrefresh = 50,
  94         .flags = 0,
  95         .width_mm = 68,
  96         .height_mm = 122,
  97 };
  98
  99 static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
 100 {
 101         return container_of(panel, struct rm68200, panel);
 102 }
 103
 104 static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
 105                                   size_t len)
 106 {
 107         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 108         int err;
 109
 110         err = mipi_dsi_dcs_write_buffer(dsi, data, len);
 111         if (err < 0)
 112                 DRM_ERROR_RATELIMITED("MIPI DSI DCS write buffer failed: %d\n",
 113                                       err);
 114 }
 115
 116 static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
 117 {
 118         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 119         int err;
 120
 121         err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
 122         if (err < 0)
 123                 DRM_ERROR_RATELIMITED("MIPI DSI DCS write failed: %d\n", err);
 124 }
 125
 126 #define dcs_write_seq(ctx, seq...)                              \
 127 ({                                                              \
 128         static const u8 d[] = { seq };                          \
 129                                                                 \
 130         rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));           \
 131 })
 132
 133 /*
 134  * This panel is not able to auto-increment all cmd addresses so for some of
 135  * them, we need to send them one by one...
 136  */
 137 #define dcs_write_cmd_seq(ctx, cmd, seq...)                     \
 138 ({                                                              \
 139         static const u8 d[] = { seq };                          \
 140         unsigned int i;                                         \
 141                                                                 \
 142         for (i = 0; i < ARRAY_SIZE(d) ; i++)                    \
 143                 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);      \
 144 })
 145
 146 static void rm68200_init_sequence(struct rm68200 *ctx)
 147 {
 148         /* Enter CMD2 with page 0 */
 149         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
 150         dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
 151         dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
 152         dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
 153         dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
 154         dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
 155         dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
 156         dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
 157         dcs_write_seq(ctx, MCS_INVCTR, 0x00);
 158         dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
 159         dcs_write_seq(ctx, MCS_SDCTR, 0x06);
 160         dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
 161         dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
 162         dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
 163         dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
 164
 165         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
 166         dcs_write_seq(ctx, GOA_VSTV1, 0x05);
 167         dcs_write_seq(ctx, 0x02, 0x0B);
 168         dcs_write_seq(ctx, 0x03, 0x0F);
 169         dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
 170         dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
 171                           0x50);
 172         dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
 173                           0x00, 0x85, 0x08);
 174         dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
 175                           0x00, 0x85, 0x08);
 176         dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 177                       0x00, 0x00, 0x00, 0x00);
 178         dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
 179         dcs_write_seq(ctx, 0x2D, 0x01);
 180         dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
 181                       0x00);
 182         dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
 183         dcs_write_seq(ctx, 0x3D, 0x40);
 184         dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
 185         dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 186                       0x00, 0x00, 0x00, 0x00, 0x00);
 187         dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 188                       0x00, 0x00);
 189         dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
 190         dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
 191         dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 192                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 193         dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
 194         dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
 195         dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
 196                       0x00, 0x00);
 197         dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
 198         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
 199                           0x16, 0x12, 0x08, 0x3F);
 200         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
 201                           0x0A, 0x0E, 0x3F, 0x3F, 0x00);
 202         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
 203                           0x05, 0x01, 0x3F, 0x3F, 0x0F);
 204         dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
 205                           0x3F);
 206         dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
 207         dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
 208         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
 209                           0x15, 0x11, 0x0F, 0x3F);
 210         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
 211                           0x0D, 0x09, 0x3F, 0x3F, 0x07);
 212         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
 213                           0x02, 0x06, 0x3F, 0x3F, 0x08);
 214         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
 215                           0x3F, 0x3F, 0x0E, 0x10, 0x14);
 216         dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
 217         dcs_write_seq(ctx, 0xDC, 0x02);
 218         dcs_write_seq(ctx, 0xDE, 0x12);
 219
 220         dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
 221         dcs_write_seq(ctx, 0x01, 0x75);
 222
 223         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
 224         dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 225                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 226                           0x12, 0x0C, 0x00);
 227         dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 228                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 229                           0x12, 0x0C, 0x00);
 230
 231         /* Exit CMD2 */
 232         dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
 233 }
 234
 235 static int rm68200_disable(struct drm_panel *panel)
 236 {
 237         struct rm68200 *ctx = panel_to_rm68200(panel);
 238
 239         if (!ctx->enabled)
 240                 return 0;
 241
 242         backlight_disable(ctx->backlight);
 243
 244         ctx->enabled = false;
 245
 246         return 0;
 247 }
 248
 249 static int rm68200_unprepare(struct drm_panel *panel)
 250 {
 251         struct rm68200 *ctx = panel_to_rm68200(panel);
 252         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 253         int ret;
 254
 255         if (!ctx->prepared)
 256                 return 0;
 257
 258         ret = mipi_dsi_dcs_set_display_off(dsi);
 259         if (ret)
 260                 DRM_WARN("failed to set display off: %d\n", ret);
 261
 262         ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
 263         if (ret)
 264                 DRM_WARN("failed to enter sleep mode: %d\n", ret);
 265
 266         msleep(120);
 267
 268         if (ctx->reset_gpio) {
 269                 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 270                 msleep(20);
 271         }
 272
 273         regulator_disable(ctx->supply);
 274
 275         ctx->prepared = false;
 276
 277         return 0;
 278 }
 279
 280 static int rm68200_prepare(struct drm_panel *panel)
 281 {
 282         struct rm68200 *ctx = panel_to_rm68200(panel);
 283         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 284         int ret;
 285
 286         if (ctx->prepared)
 287                 return 0;
 288
 289         ret = regulator_enable(ctx->supply);
 290         if (ret < 0) {
 291                 DRM_ERROR("failed to enable supply: %d\n", ret);
 292                 return ret;
 293         }
 294
 295         if (ctx->reset_gpio) {
 296                 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 297                 msleep(20);
 298                 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
 299                 msleep(100);
 300         }
 301
 302         rm68200_init_sequence(ctx);
 303
 304         ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 305         if (ret)
 306                 return ret;
 307
 308         msleep(125);
 309
 310         ret = mipi_dsi_dcs_set_display_on(dsi);
 311         if (ret)
 312                 return ret;
 313
 314         msleep(20);
 315
 316         ctx->prepared = true;
 317
 318         return 0;
 319 }
 320
 321 static int rm68200_enable(struct drm_panel *panel)
 322 {
 323         struct rm68200 *ctx = panel_to_rm68200(panel);
 324
 325         if (ctx->enabled)
 326                 return 0;
 327
 328         backlight_enable(ctx->backlight);
 329
 330         ctx->enabled = true;
 331
 332         return 0;
 333 }
 334
 335 static int rm68200_get_modes(struct drm_panel *panel)
 336 {
 337         struct drm_display_mode *mode;
 338
 339         mode = drm_mode_duplicate(panel->drm, &default_mode);
 340         if (!mode) {
 341                 DRM_ERROR("failed to add mode %ux%ux@%u\n",
 342                           default_mode.hdisplay, default_mode.vdisplay,
 343                           default_mode.vrefresh);
 344                 return -ENOMEM;
 345         }
 346
 347         drm_mode_set_name(mode);
 348
 349         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 350         drm_mode_probed_add(panel->connector, mode);
 351
 352         panel->connector->display_info.width_mm = mode->width_mm;
 353         panel->connector->display_info.height_mm = mode->height_mm;
 354
 355         return 1;
 356 }
 357
 358 static const struct drm_panel_funcs rm68200_drm_funcs = {
 359         .disable = rm68200_disable,
 360         .unprepare = rm68200_unprepare,
 361         .prepare = rm68200_prepare,
 362         .enable = rm68200_enable,
 363         .get_modes = rm68200_get_modes,
 364 };
 365
 366 static int rm68200_probe(struct mipi_dsi_device *dsi)
 367 {
 368         struct device *dev = &dsi->dev;
 369         struct rm68200 *ctx;
 370         int ret;
 371
 372         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 373         if (!ctx)
 374                 return -ENOMEM;
 375
 376         ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
 377         if (IS_ERR(ctx->reset_gpio)) {
 378                 ret = PTR_ERR(ctx->reset_gpio);
 379                 dev_err(dev, "cannot get reset GPIO: %d\n", ret);
 380                 return ret;
 381         }
 382
 383         ctx->supply = devm_regulator_get(dev, "power");
 384         if (IS_ERR(ctx->supply)) {
 385                 ret = PTR_ERR(ctx->supply);
 386                 dev_err(dev, "cannot get regulator: %d\n", ret);
 387                 return ret;
 388         }
 389
 390         ctx->backlight = devm_of_find_backlight(dev);
 391         if (IS_ERR(ctx->backlight))
 392                 return PTR_ERR(ctx->backlight);
 393
 394         mipi_dsi_set_drvdata(dsi, ctx);
 395
 396         ctx->dev = dev;
 397
 398         dsi->lanes = 2;
 399         dsi->format = MIPI_DSI_FMT_RGB888;
 400         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
 401                           MIPI_DSI_MODE_LPM;
 402
 403         drm_panel_init(&ctx->panel);
 404         ctx->panel.dev = dev;
 405         ctx->panel.funcs = &rm68200_drm_funcs;
 406
 407         drm_panel_add(&ctx->panel);
 408
 409         ret = mipi_dsi_attach(dsi);
 410         if (ret < 0) {
 411                 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
 412                 drm_panel_remove(&ctx->panel);
 413                 return ret;
 414         }
 415
 416         return 0;
 417 }
 418
 419 static int rm68200_remove(struct mipi_dsi_device *dsi)
 420 {
 421         struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
 422
 423         mipi_dsi_detach(dsi);
 424         drm_panel_remove(&ctx->panel);
 425
 426         return 0;
 427 }
 428
 429 static const struct of_device_id raydium_rm68200_of_match[] = {
 430         { .compatible = "raydium,rm68200" },
 431         { }
 432 };
 433 MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
 434
 435 static struct mipi_dsi_driver raydium_rm68200_driver = {
 436         .probe = rm68200_probe,
 437         .remove = rm68200_remove,
 438         .driver = {
 439                 .name = "panel-raydium-rm68200",
 440                 .of_match_table = raydium_rm68200_of_match,
 441         },
 442 };
 443 module_mipi_dsi_driver(raydium_rm68200_driver);
 444
 445 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
 446 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
 447 MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
 448 MODULE_LICENSE("GPL v2");