drivers/gpu/drm/rcar-du/rcar_du_kms.c

   1 /*
   2  * rcar_du_kms.c  --  R-Car Display Unit Mode Setting
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <drm/drmP.h>
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_gem_framebuffer_helper.h>
  22
  23 #include <linux/of_graph.h>
  24 #include <linux/wait.h>
  25
  26 #include "rcar_du_crtc.h"
  27 #include "rcar_du_drv.h"
  28 #include "rcar_du_encoder.h"
  29 #include "rcar_du_kms.h"
  30 #include "rcar_du_regs.h"
  31 #include "rcar_du_vsp.h"
  32
  33 /* -----------------------------------------------------------------------------
  34  * Format helpers
  35  */
  36
  37 static const struct rcar_du_format_info rcar_du_format_infos[] = {
  38         {
  39                 .fourcc = DRM_FORMAT_RGB565,
  40                 .bpp = 16,
  41                 .planes = 1,
  42                 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
  43                 .edf = PnDDCR4_EDF_NONE,
  44         }, {
  45                 .fourcc = DRM_FORMAT_ARGB1555,
  46                 .bpp = 16,
  47                 .planes = 1,
  48                 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
  49                 .edf = PnDDCR4_EDF_NONE,
  50         }, {
  51                 .fourcc = DRM_FORMAT_XRGB1555,
  52                 .bpp = 16,
  53                 .planes = 1,
  54                 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
  55                 .edf = PnDDCR4_EDF_NONE,
  56         }, {
  57                 .fourcc = DRM_FORMAT_XRGB8888,
  58                 .bpp = 32,
  59                 .planes = 1,
  60                 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
  61                 .edf = PnDDCR4_EDF_RGB888,
  62         }, {
  63                 .fourcc = DRM_FORMAT_ARGB8888,
  64                 .bpp = 32,
  65                 .planes = 1,
  66                 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
  67                 .edf = PnDDCR4_EDF_ARGB8888,
  68         }, {
  69                 .fourcc = DRM_FORMAT_UYVY,
  70                 .bpp = 16,
  71                 .planes = 1,
  72                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  73                 .edf = PnDDCR4_EDF_NONE,
  74         }, {
  75                 .fourcc = DRM_FORMAT_YUYV,
  76                 .bpp = 16,
  77                 .planes = 1,
  78                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  79                 .edf = PnDDCR4_EDF_NONE,
  80         }, {
  81                 .fourcc = DRM_FORMAT_NV12,
  82                 .bpp = 12,
  83                 .planes = 2,
  84                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  85                 .edf = PnDDCR4_EDF_NONE,
  86         }, {
  87                 .fourcc = DRM_FORMAT_NV21,
  88                 .bpp = 12,
  89                 .planes = 2,
  90                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  91                 .edf = PnDDCR4_EDF_NONE,
  92         }, {
  93                 .fourcc = DRM_FORMAT_NV16,
  94                 .bpp = 16,
  95                 .planes = 2,
  96                 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
  97                 .edf = PnDDCR4_EDF_NONE,
  98         },
  99         /*
 100          * The following formats are not supported on Gen2 and thus have no
 101          * associated .pnmr or .edf settings.
 102          */
 103         {
 104                 .fourcc = DRM_FORMAT_NV61,
 105                 .bpp = 16,
 106                 .planes = 2,
 107         }, {
 108                 .fourcc = DRM_FORMAT_YUV420,
 109                 .bpp = 12,
 110                 .planes = 3,
 111         }, {
 112                 .fourcc = DRM_FORMAT_YVU420,
 113                 .bpp = 12,
 114                 .planes = 3,
 115         }, {
 116                 .fourcc = DRM_FORMAT_YUV422,
 117                 .bpp = 16,
 118                 .planes = 3,
 119         }, {
 120                 .fourcc = DRM_FORMAT_YVU422,
 121                 .bpp = 16,
 122                 .planes = 3,
 123         }, {
 124                 .fourcc = DRM_FORMAT_YUV444,
 125                 .bpp = 24,
 126                 .planes = 3,
 127         }, {
 128                 .fourcc = DRM_FORMAT_YVU444,
 129                 .bpp = 24,
 130                 .planes = 3,
 131         },
 132 };
 133
 134 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
 135 {
 136         unsigned int i;
 137
 138         for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
 139                 if (rcar_du_format_infos[i].fourcc == fourcc)
 140                         return &rcar_du_format_infos[i];
 141         }
 142
 143         return NULL;
 144 }
 145
 146 /* -----------------------------------------------------------------------------
 147  * Frame buffer
 148  */
 149
 150 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
 151                         struct drm_mode_create_dumb *args)
 152 {
 153         struct rcar_du_device *rcdu = dev->dev_private;
 154         unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
 155         unsigned int align;
 156
 157         /*
 158          * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
 159          * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
 160          */
 161         if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
 162                 align = 128;
 163         else
 164                 align = 16 * args->bpp / 8;
 165
 166         args->pitch = roundup(min_pitch, align);
 167
 168         return drm_gem_cma_dumb_create_internal(file, dev, args);
 169 }
 170
 171 static struct drm_framebuffer *
 172 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
 173                   const struct drm_mode_fb_cmd2 *mode_cmd)
 174 {
 175         struct rcar_du_device *rcdu = dev->dev_private;
 176         const struct rcar_du_format_info *format;
 177         unsigned int max_pitch;
 178         unsigned int align;
 179         unsigned int bpp;
 180         unsigned int i;
 181
 182         format = rcar_du_format_info(mode_cmd->pixel_format);
 183         if (format == NULL) {
 184                 dev_dbg(dev->dev, "unsupported pixel format %08x\n",
 185                         mode_cmd->pixel_format);
 186                 return ERR_PTR(-EINVAL);
 187         }
 188
 189         /*
 190          * The pitch and alignment constraints are expressed in pixels on the
 191          * hardware side and in bytes in the DRM API.
 192          */
 193         bpp = format->planes == 1 ? format->bpp / 8 : 1;
 194         max_pitch =  4096 * bpp;
 195
 196         if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
 197                 align = 128;
 198         else
 199                 align = 16 * bpp;
 200
 201         if (mode_cmd->pitches[0] & (align - 1) ||
 202             mode_cmd->pitches[0] >= max_pitch) {
 203                 dev_dbg(dev->dev, "invalid pitch value %u\n",
 204                         mode_cmd->pitches[0]);
 205                 return ERR_PTR(-EINVAL);
 206         }
 207
 208         for (i = 1; i < format->planes; ++i) {
 209                 if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) {
 210                         dev_dbg(dev->dev,
 211                                 "luma and chroma pitches do not match\n");
 212                         return ERR_PTR(-EINVAL);
 213                 }
 214         }
 215
 216         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 217 }
 218
 219 static void rcar_du_output_poll_changed(struct drm_device *dev)
 220 {
 221         struct rcar_du_device *rcdu = dev->dev_private;
 222
 223         drm_fbdev_cma_hotplug_event(rcdu->fbdev);
 224 }
 225
 226 /* -----------------------------------------------------------------------------
 227  * Atomic Check and Update
 228  */
 229
 230 static int rcar_du_atomic_check(struct drm_device *dev,
 231                                 struct drm_atomic_state *state)
 232 {
 233         struct rcar_du_device *rcdu = dev->dev_private;
 234         int ret;
 235
 236         ret = drm_atomic_helper_check(dev, state);
 237         if (ret)
 238                 return ret;
 239
 240         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
 241                 return 0;
 242
 243         return rcar_du_atomic_check_planes(dev, state);
 244 }
 245
 246 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
 247 {
 248         struct drm_device *dev = old_state->dev;
 249
 250         /* Apply the atomic update. */
 251         drm_atomic_helper_commit_modeset_disables(dev, old_state);
 252         drm_atomic_helper_commit_planes(dev, old_state,
 253                                         DRM_PLANE_COMMIT_ACTIVE_ONLY);
 254         drm_atomic_helper_commit_modeset_enables(dev, old_state);
 255
 256         drm_atomic_helper_commit_hw_done(old_state);
 257         drm_atomic_helper_wait_for_flip_done(dev, old_state);
 258
 259         drm_atomic_helper_cleanup_planes(dev, old_state);
 260 }
 261
 262 /* -----------------------------------------------------------------------------
 263  * Initialization
 264  */
 265
 266 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
 267         .atomic_commit_tail = rcar_du_atomic_commit_tail,
 268 };
 269
 270 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
 271         .fb_create = rcar_du_fb_create,
 272         .output_poll_changed = rcar_du_output_poll_changed,
 273         .atomic_check = rcar_du_atomic_check,
 274         .atomic_commit = drm_atomic_helper_commit,
 275 };
 276
 277 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
 278                                      enum rcar_du_output output,
 279                                      struct of_endpoint *ep)
 280 {
 281         struct device_node *connector = NULL;
 282         struct device_node *encoder = NULL;
 283         struct device_node *ep_node = NULL;
 284         struct device_node *entity_ep_node;
 285         struct device_node *entity;
 286         int ret;
 287
 288         /*
 289          * Locate the connected entity and infer its type from the number of
 290          * endpoints.
 291          */
 292         entity = of_graph_get_remote_port_parent(ep->local_node);
 293         if (!entity) {
 294                 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
 295                         ep->local_node);
 296                 return -ENODEV;
 297         }
 298
 299         if (!of_device_is_available(entity)) {
 300                 dev_dbg(rcdu->dev,
 301                         "connected entity %pOF is disabled, skipping\n",
 302                         entity);
 303                 return -ENODEV;
 304         }
 305
 306         entity_ep_node = of_graph_get_remote_endpoint(ep->local_node);
 307
 308         for_each_endpoint_of_node(entity, ep_node) {
 309                 if (ep_node == entity_ep_node)
 310                         continue;
 311
 312                 /*
 313                  * We've found one endpoint other than the input, this must
 314                  * be an encoder. Locate the connector.
 315                  */
 316                 encoder = entity;
 317                 connector = of_graph_get_remote_port_parent(ep_node);
 318                 of_node_put(ep_node);
 319
 320                 if (!connector) {
 321                         dev_warn(rcdu->dev,
 322                                  "no connector for encoder %pOF, skipping\n",
 323                                  encoder);
 324                         of_node_put(entity_ep_node);
 325                         of_node_put(encoder);
 326                         return -ENODEV;
 327                 }
 328
 329                 break;
 330         }
 331
 332         of_node_put(entity_ep_node);
 333
 334         if (!encoder) {
 335                 dev_warn(rcdu->dev,
 336                          "no encoder found for endpoint %pOF, skipping\n",
 337                          ep->local_node);
 338                 return -ENODEV;
 339         }
 340
 341         ret = rcar_du_encoder_init(rcdu, output, encoder, connector);
 342         if (ret && ret != -EPROBE_DEFER)
 343                 dev_warn(rcdu->dev,
 344                          "failed to initialize encoder %pOF on output %u (%d), skipping\n",
 345                          encoder, output, ret);
 346
 347         of_node_put(encoder);
 348         of_node_put(connector);
 349
 350         return ret;
 351 }
 352
 353 static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
 354 {
 355         struct device_node *np = rcdu->dev->of_node;
 356         struct device_node *ep_node;
 357         unsigned int num_encoders = 0;
 358
 359         /*
 360          * Iterate over the endpoints and create one encoder for each output
 361          * pipeline.
 362          */
 363         for_each_endpoint_of_node(np, ep_node) {
 364                 enum rcar_du_output output;
 365                 struct of_endpoint ep;
 366                 unsigned int i;
 367                 int ret;
 368
 369                 ret = of_graph_parse_endpoint(ep_node, &ep);
 370                 if (ret < 0) {
 371                         of_node_put(ep_node);
 372                         return ret;
 373                 }
 374
 375                 /* Find the output route corresponding to the port number. */
 376                 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
 377                         if (rcdu->info->routes[i].possible_crtcs &&
 378                             rcdu->info->routes[i].port == ep.port) {
 379                                 output = i;
 380                                 break;
 381                         }
 382                 }
 383
 384                 if (i == RCAR_DU_OUTPUT_MAX) {
 385                         dev_warn(rcdu->dev,
 386                                  "port %u references unexisting output, skipping\n",
 387                                  ep.port);
 388                         continue;
 389                 }
 390
 391                 /* Process the output pipeline. */
 392                 ret = rcar_du_encoders_init_one(rcdu, output, &ep);
 393                 if (ret < 0) {
 394                         if (ret == -EPROBE_DEFER) {
 395                                 of_node_put(ep_node);
 396                                 return ret;
 397                         }
 398
 399                         continue;
 400                 }
 401
 402                 num_encoders++;
 403         }
 404
 405         return num_encoders;
 406 }
 407
 408 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
 409 {
 410         /*
 411          * The color key is expressed as an RGB888 triplet stored in a 32-bit
 412          * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
 413          * or enable source color keying (1).
 414          */
 415         rcdu->props.colorkey =
 416                 drm_property_create_range(rcdu->ddev, 0, "colorkey",
 417                                           0, 0x01ffffff);
 418         if (rcdu->props.colorkey == NULL)
 419                 return -ENOMEM;
 420
 421         return 0;
 422 }
 423
 424 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
 425 {
 426         const struct device_node *np = rcdu->dev->of_node;
 427         struct of_phandle_args args;
 428         struct {
 429                 struct device_node *np;
 430                 unsigned int crtcs_mask;
 431         } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
 432         unsigned int vsps_count = 0;
 433         unsigned int cells;
 434         unsigned int i;
 435         int ret;
 436
 437         /*
 438          * First parse the DT vsps property to populate the list of VSPs. Each
 439          * entry contains a pointer to the VSP DT node and a bitmask of the
 440          * connected DU CRTCs.
 441          */
 442         cells = of_property_count_u32_elems(np, "vsps") / rcdu->num_crtcs - 1;
 443         if (cells > 1)
 444                 return -EINVAL;
 445
 446         for (i = 0; i < rcdu->num_crtcs; ++i) {
 447                 unsigned int j;
 448
 449                 ret = of_parse_phandle_with_fixed_args(np, "vsps", cells, i,
 450                                                        &args);
 451                 if (ret < 0)
 452                         goto error;
 453
 454                 /*
 455                  * Add the VSP to the list or update the corresponding existing
 456                  * entry if the VSP has already been added.
 457                  */
 458                 for (j = 0; j < vsps_count; ++j) {
 459                         if (vsps[j].np == args.np)
 460                                 break;
 461                 }
 462
 463                 if (j < vsps_count)
 464                         of_node_put(args.np);
 465                 else
 466                         vsps[vsps_count++].np = args.np;
 467
 468                 vsps[j].crtcs_mask |= BIT(i);
 469
 470                 /* Store the VSP pointer and pipe index in the CRTC. */
 471                 rcdu->crtcs[i].vsp = &rcdu->vsps[j];
 472                 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
 473         }
 474
 475         /*
 476          * Then initialize all the VSPs from the node pointers and CRTCs bitmask
 477          * computed previously.
 478          */
 479         for (i = 0; i < vsps_count; ++i) {
 480                 struct rcar_du_vsp *vsp = &rcdu->vsps[i];
 481
 482                 vsp->index = i;
 483                 vsp->dev = rcdu;
 484
 485                 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
 486                 if (ret < 0)
 487                         goto error;
 488         }
 489
 490         return 0;
 491
 492 error:
 493         for (i = 0; i < ARRAY_SIZE(vsps); ++i)
 494                 of_node_put(vsps[i].np);
 495
 496         return ret;
 497 }
 498
 499 int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 500 {
 501         static const unsigned int mmio_offsets[] = {
 502                 DU0_REG_OFFSET, DU2_REG_OFFSET
 503         };
 504
 505         struct drm_device *dev = rcdu->ddev;
 506         struct drm_encoder *encoder;
 507         struct drm_fbdev_cma *fbdev;
 508         unsigned int num_encoders;
 509         unsigned int num_groups;
 510         unsigned int swindex;
 511         unsigned int hwindex;
 512         unsigned int i;
 513         int ret;
 514
 515         drm_mode_config_init(dev);
 516
 517         dev->mode_config.min_width = 0;
 518         dev->mode_config.min_height = 0;
 519         dev->mode_config.normalize_zpos = true;
 520         dev->mode_config.funcs = &rcar_du_mode_config_funcs;
 521         dev->mode_config.helper_private = &rcar_du_mode_config_helper;
 522
 523         if (rcdu->info->gen < 3) {
 524                 dev->mode_config.max_width = 4095;
 525                 dev->mode_config.max_height = 2047;
 526         } else {
 527                 /*
 528                  * The Gen3 DU uses the VSP1 for memory access, and is limited
 529                  * to frame sizes of 8190x8190.
 530                  */
 531                 dev->mode_config.max_width = 8190;
 532                 dev->mode_config.max_height = 8190;
 533         }
 534
 535         rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
 536
 537         ret = rcar_du_properties_init(rcdu);
 538         if (ret < 0)
 539                 return ret;
 540
 541         /*
 542          * Initialize vertical blanking interrupts handling. Start with vblank
 543          * disabled for all CRTCs.
 544          */
 545         ret = drm_vblank_init(dev, (1 << rcdu->num_crtcs) - 1);
 546         if (ret < 0)
 547                 return ret;
 548
 549         /* Initialize the groups. */
 550         num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
 551
 552         for (i = 0; i < num_groups; ++i) {
 553                 struct rcar_du_group *rgrp = &rcdu->groups[i];
 554
 555                 mutex_init(&rgrp->lock);
 556
 557                 rgrp->dev = rcdu;
 558                 rgrp->mmio_offset = mmio_offsets[i];
 559                 rgrp->index = i;
 560                 /* Extract the channel mask for this group only. */
 561                 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
 562                                    & GENMASK(1, 0);
 563                 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
 564
 565                 /*
 566                  * If we have more than one CRTCs in this group pre-associate
 567                  * the low-order planes with CRTC 0 and the high-order planes
 568                  * with CRTC 1 to minimize flicker occurring when the
 569                  * association is changed.
 570                  */
 571                 rgrp->dptsr_planes = rgrp->num_crtcs > 1
 572                                    ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
 573                                    : 0;
 574
 575                 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 576                         ret = rcar_du_planes_init(rgrp);
 577                         if (ret < 0)
 578                                 return ret;
 579                 }
 580         }
 581
 582         /* Initialize the compositors. */
 583         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 584                 ret = rcar_du_vsps_init(rcdu);
 585                 if (ret < 0)
 586                         return ret;
 587         }
 588
 589         /* Create the CRTCs. */
 590         for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
 591                 struct rcar_du_group *rgrp;
 592
 593                 /* Skip unpopulated DU channels. */
 594                 if (!(rcdu->info->channels_mask & BIT(hwindex)))
 595                         continue;
 596
 597                 rgrp = &rcdu->groups[hwindex / 2];
 598
 599                 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
 600                 if (ret < 0)
 601                         return ret;
 602         }
 603
 604         /* Initialize the encoders. */
 605         ret = rcar_du_encoders_init(rcdu);
 606         if (ret < 0)
 607                 return ret;
 608
 609         if (ret == 0) {
 610                 dev_err(rcdu->dev, "error: no encoder could be initialized\n");
 611                 return -EINVAL;
 612         }
 613
 614         num_encoders = ret;
 615
 616         /*
 617          * Set the possible CRTCs and possible clones. There's always at least
 618          * one way for all encoders to clone each other, set all bits in the
 619          * possible clones field.
 620          */
 621         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 622                 struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
 623                 const struct rcar_du_output_routing *route =
 624                         &rcdu->info->routes[renc->output];
 625
 626                 encoder->possible_crtcs = route->possible_crtcs;
 627                 encoder->possible_clones = (1 << num_encoders) - 1;
 628         }
 629
 630         drm_mode_config_reset(dev);
 631
 632         drm_kms_helper_poll_init(dev);
 633
 634         if (dev->mode_config.num_connector) {
 635                 fbdev = drm_fbdev_cma_init(dev, 32,
 636                                            dev->mode_config.num_connector);
 637                 if (IS_ERR(fbdev))
 638                         return PTR_ERR(fbdev);
 639
 640                 rcdu->fbdev = fbdev;
 641         } else {
 642                 dev_info(rcdu->dev,
 643                          "no connector found, disabling fbdev emulation\n");
 644         }
 645
 646         return 0;
 647 }