drivers/gpu/drm/tegra/hub.h

   1 /*
   2  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef TEGRA_HUB_H
  10 #define TEGRA_HUB_H 1
  11
  12 #include <drm/drmP.h>
  13 #include <drm/drm_plane.h>
  14
  15 #include "plane.h"
  16
  17 struct tegra_dc;
  18
  19 struct tegra_windowgroup {
  20         unsigned int usecount;
  21         struct mutex lock;
  22
  23         unsigned int index;
  24         struct device *parent;
  25         struct reset_control *rst;
  26 };
  27
  28 struct tegra_shared_plane {
  29         struct tegra_plane base;
  30         struct tegra_windowgroup *wgrp;
  31 };
  32
  33 static inline struct tegra_shared_plane *
  34 to_tegra_shared_plane(struct drm_plane *plane)
  35 {
  36         return container_of(plane, struct tegra_shared_plane, base.base);
  37 }
  38
  39 struct tegra_display_hub_soc {
  40         unsigned int num_wgrps;
  41 };
  42
  43 struct tegra_display_hub {
  44         struct drm_private_obj base;
  45         struct host1x_client client;
  46         struct clk *clk_disp;
  47         struct clk *clk_dsc;
  48         struct clk *clk_hub;
  49         struct reset_control *rst;
  50
  51         const struct tegra_display_hub_soc *soc;
  52         struct tegra_windowgroup *wgrps;
  53 };
  54
  55 static inline struct tegra_display_hub *
  56 to_tegra_display_hub(struct host1x_client *client)
  57 {
  58         return container_of(client, struct tegra_display_hub, client);
  59 }
  60
  61 struct tegra_display_hub_state {
  62         struct drm_private_state base;
  63
  64         struct tegra_dc *dc;
  65         unsigned long rate;
  66         struct clk *clk;
  67 };
  68
  69 static inline struct tegra_display_hub_state *
  70 to_tegra_display_hub_state(struct drm_private_state *priv)
  71 {
  72         return container_of(priv, struct tegra_display_hub_state, base);
  73 }
  74
  75 struct tegra_dc;
  76 struct tegra_plane;
  77
  78 int tegra_display_hub_prepare(struct tegra_display_hub *hub);
  79 void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
  80
  81 struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
  82                                             struct tegra_dc *dc,
  83                                             unsigned int wgrp,
  84                                             unsigned int index);
  85
  86 int tegra_display_hub_atomic_check(struct drm_device *drm,
  87                                    struct drm_atomic_state *state);
  88 void tegra_display_hub_atomic_commit(struct drm_device *drm,
  89                                      struct drm_atomic_state *state);
  90
  91 #define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
  92 #define  LATENCY_EVENT (1 << 3)
  93
  94 #define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
  95 #define  CURS_SLOTS(x) (((x) & 0xff) << 8)
  96 #define  WGRP_SLOTS(x) (((x) & 0xff) << 0)
  97
  98 #endif /* TEGRA_HUB_H */