drivers/thermal/mtk_thermal.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Hanyi Wu <hanyi.wu@mediatek.com>
   4  *         Sascha Hauer <s.hauer@pengutronix.de>
   5  *         Dawei Chien <dawei.chien@mediatek.com>
   6  *         Louis Yu <louis.yu@mediatek.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/nvmem-consumer.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/thermal.h>
  31 #include <linux/reset.h>
  32 #include <linux/types.h>
  33
  34 /* AUXADC Registers */
  35 #define AUXADC_CON0_V           0x000
  36 #define AUXADC_CON1_V           0x004
  37 #define AUXADC_CON1_SET_V       0x008
  38 #define AUXADC_CON1_CLR_V       0x00c
  39 #define AUXADC_CON2_V           0x010
  40 #define AUXADC_DATA(channel)    (0x14 + (channel) * 4)
  41 #define AUXADC_MISC_V           0x094
  42
  43 #define AUXADC_CON1_CHANNEL(x)  BIT(x)
  44
  45 #define APMIXED_SYS_TS_CON1     0x604
  46
  47 /* Thermal Controller Registers */
  48 #define TEMP_MONCTL0            0x000
  49 #define TEMP_MONCTL1            0x004
  50 #define TEMP_MONCTL2            0x008
  51 #define TEMP_MONIDET0           0x014
  52 #define TEMP_MONIDET1           0x018
  53 #define TEMP_MSRCTL0            0x038
  54 #define TEMP_AHBPOLL            0x040
  55 #define TEMP_AHBTO              0x044
  56 #define TEMP_ADCPNP0            0x048
  57 #define TEMP_ADCPNP1            0x04c
  58 #define TEMP_ADCPNP2            0x050
  59 #define TEMP_ADCPNP3            0x0b4
  60
  61 #define TEMP_ADCMUX             0x054
  62 #define TEMP_ADCEN              0x060
  63 #define TEMP_PNPMUXADDR         0x064
  64 #define TEMP_ADCMUXADDR         0x068
  65 #define TEMP_ADCENADDR          0x074
  66 #define TEMP_ADCVALIDADDR       0x078
  67 #define TEMP_ADCVOLTADDR        0x07c
  68 #define TEMP_RDCTRL             0x080
  69 #define TEMP_ADCVALIDMASK       0x084
  70 #define TEMP_ADCVOLTAGESHIFT    0x088
  71 #define TEMP_ADCWRITECTRL       0x08c
  72 #define TEMP_MSR0               0x090
  73 #define TEMP_MSR1               0x094
  74 #define TEMP_MSR2               0x098
  75 #define TEMP_MSR3               0x0B8
  76
  77 #define TEMP_SPARE0             0x0f0
  78
  79 #define PTPCORESEL              0x400
  80
  81 #define TEMP_MONCTL1_PERIOD_UNIT(x)     ((x) & 0x3ff)
  82
  83 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
  84 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
  85
  86 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)       (x)
  87
  88 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE         BIT(0)
  89 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE         BIT(1)
  90
  91 #define TEMP_ADCVALIDMASK_VALID_HIGH            BIT(5)
  92 #define TEMP_ADCVALIDMASK_VALID_POS(bit)        (bit)
  93
  94 /* MT8173 thermal sensors */
  95 #define MT8173_TS1      0
  96 #define MT8173_TS2      1
  97 #define MT8173_TS3      2
  98 #define MT8173_TS4      3
  99 #define MT8173_TSABB    4
 100
 101 /* AUXADC channel 11 is used for the temperature sensors */
 102 #define MT8173_TEMP_AUXADC_CHANNEL      11
 103
 104 /* The total number of temperature sensors in the MT8173 */
 105 #define MT8173_NUM_SENSORS              5
 106
 107 /* The number of banks in the MT8173 */
 108 #define MT8173_NUM_ZONES                4
 109
 110 /* The number of sensing points per bank */
 111 #define MT8173_NUM_SENSORS_PER_ZONE     4
 112
 113 /*
 114  * Layout of the fuses providing the calibration data
 115  * These macros could be used for MT8173, MT2701, and MT2712.
 116  * MT8173 has 5 sensors and needs 5 VTS calibration data.
 117  * MT2701 has 3 sensors and needs 3 VTS calibration data.
 118  * MT2712 has 4 sensors and needs 4 VTS calibration data.
 119  */
 120 #define MT8173_CALIB_BUF0_VALID         BIT(0)
 121 #define MT8173_CALIB_BUF1_ADC_GE(x)     (((x) >> 22) & 0x3ff)
 122 #define MT8173_CALIB_BUF0_VTS_TS1(x)    (((x) >> 17) & 0x1ff)
 123 #define MT8173_CALIB_BUF0_VTS_TS2(x)    (((x) >> 8) & 0x1ff)
 124 #define MT8173_CALIB_BUF1_VTS_TS3(x)    (((x) >> 0) & 0x1ff)
 125 #define MT8173_CALIB_BUF2_VTS_TS4(x)    (((x) >> 23) & 0x1ff)
 126 #define MT8173_CALIB_BUF2_VTS_TSABB(x)  (((x) >> 14) & 0x1ff)
 127 #define MT8173_CALIB_BUF0_DEGC_CALI(x)  (((x) >> 1) & 0x3f)
 128 #define MT8173_CALIB_BUF0_O_SLOPE(x)    (((x) >> 26) & 0x3f)
 129 #define MT8173_CALIB_BUF0_O_SLOPE_SIGN(x)       (((x) >> 7) & 0x1)
 130 #define MT8173_CALIB_BUF1_ID(x) (((x) >> 9) & 0x1)
 131
 132 /* MT2701 thermal sensors */
 133 #define MT2701_TS1      0
 134 #define MT2701_TS2      1
 135 #define MT2701_TSABB    2
 136
 137 /* AUXADC channel 11 is used for the temperature sensors */
 138 #define MT2701_TEMP_AUXADC_CHANNEL      11
 139
 140 /* The total number of temperature sensors in the MT2701 */
 141 #define MT2701_NUM_SENSORS      3
 142
 143 /* The number of sensing points per bank */
 144 #define MT2701_NUM_SENSORS_PER_ZONE     3
 145
 146 /* MT2712 thermal sensors */
 147 #define MT2712_TS1      0
 148 #define MT2712_TS2      1
 149 #define MT2712_TS3      2
 150 #define MT2712_TS4      3
 151
 152 /* AUXADC channel 11 is used for the temperature sensors */
 153 #define MT2712_TEMP_AUXADC_CHANNEL      11
 154
 155 /* The total number of temperature sensors in the MT2712 */
 156 #define MT2712_NUM_SENSORS      4
 157
 158 /* The number of sensing points per bank */
 159 #define MT2712_NUM_SENSORS_PER_ZONE     4
 160
 161 #define THERMAL_NAME    "mtk-thermal"
 162
 163 struct mtk_thermal;
 164
 165 struct thermal_bank_cfg {
 166         unsigned int num_sensors;
 167         const int *sensors;
 168 };
 169
 170 struct mtk_thermal_bank {
 171         struct mtk_thermal *mt;
 172         int id;
 173 };
 174
 175 struct mtk_thermal_data {
 176         s32 num_banks;
 177         s32 num_sensors;
 178         s32 auxadc_channel;
 179         const int *sensor_mux_values;
 180         const int *msr;
 181         const int *adcpnp;
 182         struct thermal_bank_cfg bank_data[];
 183 };
 184
 185 struct mtk_thermal {
 186         struct device *dev;
 187         void __iomem *thermal_base;
 188
 189         struct clk *clk_peri_therm;
 190         struct clk *clk_auxadc;
 191         /* lock: for getting and putting banks */
 192         struct mutex lock;
 193
 194         /* Calibration values */
 195         s32 adc_ge;
 196         s32 degc_cali;
 197         s32 o_slope;
 198         s32 vts[MT8173_NUM_SENSORS];
 199
 200         const struct mtk_thermal_data *conf;
 201         struct mtk_thermal_bank banks[];
 202 };
 203
 204 /* MT8173 thermal sensor data */
 205 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
 206         { MT8173_TS2, MT8173_TS3 },
 207         { MT8173_TS2, MT8173_TS4 },
 208         { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
 209         { MT8173_TS2 },
 210 };
 211
 212 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
 213         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
 214 };
 215
 216 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
 217         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
 218 };
 219
 220 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
 221
 222 /* MT2701 thermal sensor data */
 223 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
 224         MT2701_TS1, MT2701_TS2, MT2701_TSABB
 225 };
 226
 227 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
 228         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
 229 };
 230
 231 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
 232         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
 233 };
 234
 235 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
 236
 237 /* MT2712 thermal sensor data */
 238 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
 239         MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
 240 };
 241
 242 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
 243         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
 244 };
 245
 246 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
 247         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
 248 };
 249
 250 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
 251
 252 /**
 253  * The MT8173 thermal controller has four banks. Each bank can read up to
 254  * four temperature sensors simultaneously. The MT8173 has a total of 5
 255  * temperature sensors. We use each bank to measure a certain area of the
 256  * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
 257  * areas, hence is used in different banks.
 258  *
 259  * The thermal core only gets the maximum temperature of all banks, so
 260  * the bank concept wouldn't be necessary here. However, the SVS (Smart
 261  * Voltage Scaling) unit makes its decisions based on the same bank
 262  * data, and this indeed needs the temperatures of the individual banks
 263  * for making better decisions.
 264  */
 265 static const struct mtk_thermal_data mt8173_thermal_data = {
 266         .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
 267         .num_banks = MT8173_NUM_ZONES,
 268         .num_sensors = MT8173_NUM_SENSORS,
 269         .bank_data = {
 270                 {
 271                         .num_sensors = 2,
 272                         .sensors = mt8173_bank_data[0],
 273                 }, {
 274                         .num_sensors = 2,
 275                         .sensors = mt8173_bank_data[1],
 276                 }, {
 277                         .num_sensors = 3,
 278                         .sensors = mt8173_bank_data[2],
 279                 }, {
 280                         .num_sensors = 1,
 281                         .sensors = mt8173_bank_data[3],
 282                 },
 283         },
 284         .msr = mt8173_msr,
 285         .adcpnp = mt8173_adcpnp,
 286         .sensor_mux_values = mt8173_mux_values,
 287 };
 288
 289 /**
 290  * The MT2701 thermal controller has one bank, which can read up to
 291  * three temperature sensors simultaneously. The MT2701 has a total of 3
 292  * temperature sensors.
 293  *
 294  * The thermal core only gets the maximum temperature of this one bank,
 295  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
 296  * Voltage Scaling) unit makes its decisions based on the same bank
 297  * data.
 298  */
 299 static const struct mtk_thermal_data mt2701_thermal_data = {
 300         .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
 301         .num_banks = 1,
 302         .num_sensors = MT2701_NUM_SENSORS,
 303         .bank_data = {
 304                 {
 305                         .num_sensors = 3,
 306                         .sensors = mt2701_bank_data,
 307                 },
 308         },
 309         .msr = mt2701_msr,
 310         .adcpnp = mt2701_adcpnp,
 311         .sensor_mux_values = mt2701_mux_values,
 312 };
 313
 314 /**
 315  * The MT2712 thermal controller has one bank, which can read up to
 316  * four temperature sensors simultaneously. The MT2712 has a total of 4
 317  * temperature sensors.
 318  *
 319  * The thermal core only gets the maximum temperature of this one bank,
 320  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
 321  * Voltage Scaling) unit makes its decisions based on the same bank
 322  * data.
 323  */
 324 static const struct mtk_thermal_data mt2712_thermal_data = {
 325         .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
 326         .num_banks = 1,
 327         .num_sensors = MT2712_NUM_SENSORS,
 328         .bank_data = {
 329                 {
 330                         .num_sensors = 4,
 331                         .sensors = mt2712_bank_data,
 332                 },
 333         },
 334         .msr = mt2712_msr,
 335         .adcpnp = mt2712_adcpnp,
 336         .sensor_mux_values = mt2712_mux_values,
 337 };
 338
 339 /**
 340  * raw_to_mcelsius - convert a raw ADC value to mcelsius
 341  * @mt:         The thermal controller
 342  * @raw:        raw ADC value
 343  *
 344  * This converts the raw ADC value to mcelsius using the SoC specific
 345  * calibration constants
 346  */
 347 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
 348 {
 349         s32 tmp;
 350
 351         raw &= 0xfff;
 352
 353         tmp = 203450520 << 3;
 354         tmp /= 165 + mt->o_slope;
 355         tmp /= 10000 + mt->adc_ge;
 356         tmp *= raw - mt->vts[sensno] - 3350;
 357         tmp >>= 3;
 358
 359         return mt->degc_cali * 500 - tmp;
 360 }
 361
 362 /**
 363  * mtk_thermal_get_bank - get bank
 364  * @bank:       The bank
 365  *
 366  * The bank registers are banked, we have to select a bank in the
 367  * PTPCORESEL register to access it.
 368  */
 369 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
 370 {
 371         struct mtk_thermal *mt = bank->mt;
 372         u32 val;
 373
 374         mutex_lock(&mt->lock);
 375
 376         val = readl(mt->thermal_base + PTPCORESEL);
 377         val &= ~0xf;
 378         val |= bank->id;
 379         writel(val, mt->thermal_base + PTPCORESEL);
 380 }
 381
 382 /**
 383  * mtk_thermal_put_bank - release bank
 384  * @bank:       The bank
 385  *
 386  * release a bank previously taken with mtk_thermal_get_bank,
 387  */
 388 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
 389 {
 390         struct mtk_thermal *mt = bank->mt;
 391
 392         mutex_unlock(&mt->lock);
 393 }
 394
 395 /**
 396  * mtk_thermal_bank_temperature - get the temperature of a bank
 397  * @bank:       The bank
 398  *
 399  * The temperature of a bank is considered the maximum temperature of
 400  * the sensors associated to the bank.
 401  */
 402 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
 403 {
 404         struct mtk_thermal *mt = bank->mt;
 405         const struct mtk_thermal_data *conf = mt->conf;
 406         int i, temp = INT_MIN, max = INT_MIN;
 407         u32 raw;
 408
 409         for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
 410                 raw = readl(mt->thermal_base + conf->msr[i]);
 411
 412                 temp = raw_to_mcelsius(mt,
 413                                        conf->bank_data[bank->id].sensors[i],
 414                                        raw);
 415
 416                 /*
 417                  * The first read of a sensor often contains very high bogus
 418                  * temperature value. Filter these out so that the system does
 419                  * not immediately shut down.
 420                  */
 421                 if (temp > 200000)
 422                         temp = 0;
 423
 424                 if (temp > max)
 425                         max = temp;
 426         }
 427
 428         return max;
 429 }
 430
 431 static int mtk_read_temp(void *data, int *temperature)
 432 {
 433         struct mtk_thermal *mt = data;
 434         int i;
 435         int tempmax = INT_MIN;
 436
 437         for (i = 0; i < mt->conf->num_banks; i++) {
 438                 struct mtk_thermal_bank *bank = &mt->banks[i];
 439
 440                 mtk_thermal_get_bank(bank);
 441
 442                 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
 443
 444                 mtk_thermal_put_bank(bank);
 445         }
 446
 447         *temperature = tempmax;
 448
 449         return 0;
 450 }
 451
 452 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
 453         .get_temp = mtk_read_temp,
 454 };
 455
 456 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
 457                                   u32 apmixed_phys_base, u32 auxadc_phys_base)
 458 {
 459         struct mtk_thermal_bank *bank = &mt->banks[num];
 460         const struct mtk_thermal_data *conf = mt->conf;
 461         int i;
 462
 463         bank->id = num;
 464         bank->mt = mt;
 465
 466         mtk_thermal_get_bank(bank);
 467
 468         /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
 469         writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
 470
 471         /*
 472          * filt interval is 1 * 46.540us = 46.54us,
 473          * sen interval is 429 * 46.540us = 19.96ms
 474          */
 475         writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
 476                         TEMP_MONCTL2_SENSOR_INTERVAL(429),
 477                         mt->thermal_base + TEMP_MONCTL2);
 478
 479         /* poll is set to 10u */
 480         writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
 481                mt->thermal_base + TEMP_AHBPOLL);
 482
 483         /* temperature sampling control, 1 sample */
 484         writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
 485
 486         /* exceed this polling time, IRQ would be inserted */
 487         writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
 488
 489         /* number of interrupts per event, 1 is enough */
 490         writel(0x0, mt->thermal_base + TEMP_MONIDET0);
 491         writel(0x0, mt->thermal_base + TEMP_MONIDET1);
 492
 493         /*
 494          * The MT8173 thermal controller does not have its own ADC. Instead it
 495          * uses AHB bus accesses to control the AUXADC. To do this the thermal
 496          * controller has to be programmed with the physical addresses of the
 497          * AUXADC registers and with the various bit positions in the AUXADC.
 498          * Also the thermal controller controls a mux in the APMIXEDSYS register
 499          * space.
 500          */
 501
 502         /*
 503          * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
 504          * automatically by hw
 505          */
 506         writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX);
 507
 508         /* AHB address for auxadc mux selection */
 509         writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
 510                mt->thermal_base + TEMP_ADCMUXADDR);
 511
 512         /* AHB address for pnp sensor mux selection */
 513         writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
 514                mt->thermal_base + TEMP_PNPMUXADDR);
 515
 516         /* AHB value for auxadc enable */
 517         writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN);
 518
 519         /* AHB address for auxadc enable (channel 0 immediate mode selected) */
 520         writel(auxadc_phys_base + AUXADC_CON1_SET_V,
 521                mt->thermal_base + TEMP_ADCENADDR);
 522
 523         /* AHB address for auxadc valid bit */
 524         writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
 525                mt->thermal_base + TEMP_ADCVALIDADDR);
 526
 527         /* AHB address for auxadc voltage output */
 528         writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
 529                mt->thermal_base + TEMP_ADCVOLTADDR);
 530
 531         /* read valid & voltage are at the same register */
 532         writel(0x0, mt->thermal_base + TEMP_RDCTRL);
 533
 534         /* indicate where the valid bit is */
 535         writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
 536                mt->thermal_base + TEMP_ADCVALIDMASK);
 537
 538         /* no shift */
 539         writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
 540
 541         /* enable auxadc mux write transaction */
 542         writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 543                mt->thermal_base + TEMP_ADCWRITECTRL);
 544
 545         for (i = 0; i < conf->bank_data[num].num_sensors; i++)
 546                 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
 547                        mt->thermal_base + conf->adcpnp[i]);
 548
 549         writel((1 << conf->bank_data[num].num_sensors) - 1,
 550                mt->thermal_base + TEMP_MONCTL0);
 551
 552         writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
 553                TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 554                mt->thermal_base + TEMP_ADCWRITECTRL);
 555
 556         mtk_thermal_put_bank(bank);
 557 }
 558
 559 static u64 of_get_phys_base(struct device_node *np)
 560 {
 561         u64 size64;
 562         const __be32 *regaddr_p;
 563
 564         regaddr_p = of_get_address(np, 0, &size64, NULL);
 565         if (!regaddr_p)
 566                 return OF_BAD_ADDR;
 567
 568         return of_translate_address(np, regaddr_p);
 569 }
 570
 571 static int mtk_thermal_get_calibration_data(struct device *dev,
 572                                             struct mtk_thermal *mt)
 573 {
 574         struct nvmem_cell *cell;
 575         u32 *buf;
 576         size_t len;
 577         int i, ret = 0;
 578
 579         /* Start with default values */
 580         mt->adc_ge = 512;
 581         for (i = 0; i < mt->conf->num_sensors; i++)
 582                 mt->vts[i] = 260;
 583         mt->degc_cali = 40;
 584         mt->o_slope = 0;
 585
 586         cell = nvmem_cell_get(dev, "calibration-data");
 587         if (IS_ERR(cell)) {
 588                 if (PTR_ERR(cell) == -EPROBE_DEFER)
 589                         return PTR_ERR(cell);
 590                 return 0;
 591         }
 592
 593         buf = (u32 *)nvmem_cell_read(cell, &len);
 594
 595         nvmem_cell_put(cell);
 596
 597         if (IS_ERR(buf))
 598                 return PTR_ERR(buf);
 599
 600         if (len < 3 * sizeof(u32)) {
 601                 dev_warn(dev, "invalid calibration data\n");
 602                 ret = -EINVAL;
 603                 goto out;
 604         }
 605
 606         if (buf[0] & MT8173_CALIB_BUF0_VALID) {
 607                 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
 608                 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
 609                 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
 610                 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
 611                 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
 612                 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
 613                 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
 614                 if (MT8173_CALIB_BUF1_ID(buf[1]) &
 615                     MT8173_CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
 616                         mt->o_slope = -MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
 617                 else
 618                         mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
 619         } else {
 620                 dev_info(dev, "Device not calibrated, using default calibration values\n");
 621         }
 622
 623 out:
 624         kfree(buf);
 625
 626         return ret;
 627 }
 628
 629 static const struct of_device_id mtk_thermal_of_match[] = {
 630         {
 631                 .compatible = "mediatek,mt8173-thermal",
 632                 .data = (void *)&mt8173_thermal_data,
 633         },
 634         {
 635                 .compatible = "mediatek,mt2701-thermal",
 636                 .data = (void *)&mt2701_thermal_data,
 637         },
 638         {
 639                 .compatible = "mediatek,mt2712-thermal",
 640                 .data = (void *)&mt2712_thermal_data,
 641         }, {
 642         },
 643 };
 644 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
 645
 646 static int mtk_thermal_probe(struct platform_device *pdev)
 647 {
 648         int ret, i;
 649         struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
 650         struct mtk_thermal *mt;
 651         struct resource *res;
 652         const struct of_device_id *of_id;
 653         u64 auxadc_phys_base, apmixed_phys_base;
 654         struct thermal_zone_device *tzdev;
 655
 656         mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
 657         if (!mt)
 658                 return -ENOMEM;
 659
 660         of_id = of_match_device(mtk_thermal_of_match, &pdev->dev);
 661         if (of_id)
 662                 mt->conf = (const struct mtk_thermal_data *)of_id->data;
 663
 664         mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
 665         if (IS_ERR(mt->clk_peri_therm))
 666                 return PTR_ERR(mt->clk_peri_therm);
 667
 668         mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
 669         if (IS_ERR(mt->clk_auxadc))
 670                 return PTR_ERR(mt->clk_auxadc);
 671
 672         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 673         mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
 674         if (IS_ERR(mt->thermal_base))
 675                 return PTR_ERR(mt->thermal_base);
 676
 677         ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
 678         if (ret)
 679                 return ret;
 680
 681         mutex_init(&mt->lock);
 682
 683         mt->dev = &pdev->dev;
 684
 685         auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
 686         if (!auxadc) {
 687                 dev_err(&pdev->dev, "missing auxadc node\n");
 688                 return -ENODEV;
 689         }
 690
 691         auxadc_phys_base = of_get_phys_base(auxadc);
 692
 693         of_node_put(auxadc);
 694
 695         if (auxadc_phys_base == OF_BAD_ADDR) {
 696                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 697                 return -EINVAL;
 698         }
 699
 700         apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
 701         if (!apmixedsys) {
 702                 dev_err(&pdev->dev, "missing apmixedsys node\n");
 703                 return -ENODEV;
 704         }
 705
 706         apmixed_phys_base = of_get_phys_base(apmixedsys);
 707
 708         of_node_put(apmixedsys);
 709
 710         if (apmixed_phys_base == OF_BAD_ADDR) {
 711                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 712                 return -EINVAL;
 713         }
 714
 715         ret = device_reset(&pdev->dev);
 716         if (ret)
 717                 return ret;
 718
 719         ret = clk_prepare_enable(mt->clk_auxadc);
 720         if (ret) {
 721                 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
 722                 return ret;
 723         }
 724
 725         ret = clk_prepare_enable(mt->clk_peri_therm);
 726         if (ret) {
 727                 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
 728                 goto err_disable_clk_auxadc;
 729         }
 730
 731         for (i = 0; i < mt->conf->num_banks; i++)
 732                 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
 733                                       auxadc_phys_base);
 734
 735         platform_set_drvdata(pdev, mt);
 736
 737         tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
 738                                                      &mtk_thermal_ops);
 739         if (IS_ERR(tzdev)) {
 740                 ret = PTR_ERR(tzdev);
 741                 goto err_disable_clk_peri_therm;
 742         }
 743
 744         return 0;
 745
 746 err_disable_clk_peri_therm:
 747         clk_disable_unprepare(mt->clk_peri_therm);
 748 err_disable_clk_auxadc:
 749         clk_disable_unprepare(mt->clk_auxadc);
 750
 751         return ret;
 752 }
 753
 754 static int mtk_thermal_remove(struct platform_device *pdev)
 755 {
 756         struct mtk_thermal *mt = platform_get_drvdata(pdev);
 757
 758         clk_disable_unprepare(mt->clk_peri_therm);
 759         clk_disable_unprepare(mt->clk_auxadc);
 760
 761         return 0;
 762 }
 763
 764 static struct platform_driver mtk_thermal_driver = {
 765         .probe = mtk_thermal_probe,
 766         .remove = mtk_thermal_remove,
 767         .driver = {
 768                 .name = THERMAL_NAME,
 769                 .of_match_table = mtk_thermal_of_match,
 770         },
 771 };
 772
 773 module_platform_driver(mtk_thermal_driver);
 774
 775 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
 776 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
 777 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
 778 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
 779 MODULE_DESCRIPTION("Mediatek thermal driver");
 780 MODULE_LICENSE("GPL v2");