Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

   1 Binding for a ST pll clock driver.
   2
   3 This binding uses the common clock binding[1].
   4 Base address is located to the parent node. See clock binding[2]
   5
   6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
   8
   9 Required properties:
  10
  11 - compatible : shall be:
  12         "st,clkgen-pll0"
  13         "st,clkgen-pll1"
  14         "st,stih407-clkgen-plla9"
  15         "st,stih418-clkgen-plla9"
  16
  17 - #clock-cells : From common clock binding; shall be set to 1.
  18
  19 - clocks : From common clock binding
  20
  21 - clock-output-names : From common clock binding.
  22
  23 Example:
  24
  25         clockgen-a9@92b0000 {
  26                 compatible = "st,clkgen-c32";
  27                 reg = <0x92b0000 0xffff>;
  28
  29                 clockgen_a9_pll: clockgen-a9-pll {
  30                         #clock-cells = <1>;
  31                         compatible = "st,stih407-clkgen-plla9";
  32
  33                         clocks = <&clk_sysin>;
  34
  35                         clock-output-names = "clockgen-a9-pll-odf";
  36                 };
  37         };