3 The following bindings apply to a family of Display Processors sold as
4 licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
5 DP650 processors that offer multiple composition layers, support for
6 rotation and scaling output.
9 - compatible: should be one of
13 depending on the particular implementation present in the hardware
14 - reg: Physical base address and size of the block of registers used by
16 - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
17 interrupt client nodes.
18 - interrupt-names: name of the engine inside the processor that will
19 use the corresponding interrupt. Should be one of "DE" or "SE".
20 - clocks: A list of phandle + clock-specifier pairs, one for each entry
22 - clock-names: A list of clock names. It should contain:
23 - "pclk": for the APB interface clock
24 - "aclk": for the AXI interface clock
25 - "mclk": for the main processor clock
26 - "pxlclk": for the pixel clock feeding the output PLL of the processor.
27 - arm,malidp-output-port-lines: Array of u8 values describing the number
28 of output lines per channel (R, G and B).
31 - port: The Mali DP connection to an encoder input port. The connection
32 is modelled using the OF graph bindings specified in
33 Documentation/devicetree/bindings/graph.txt
36 - memory-region: phandle to a node describing memory (see
37 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
38 to be used for the framebuffer; if not present, the framebuffer may
39 be located anywhere in memory.
47 dp0: malidp@6f200000 {
48 compatible = "arm,mali-dp650";
49 reg = <0 0x6f200000 0 0x20000>;
50 memory-region = <&display_reserved>;
51 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
52 <0 168 IRQ_TYPE_LEVEL_HIGH>;
53 interrupt-names = "DE", "SE";
54 clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
55 clock-names = "pxlclk", "mclk", "aclk", "pclk";
56 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
58 dp0_output: endpoint {
59 remote-endpoint = <&tda998x_2_input>;