1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
11 - compatible: Should be "marvell,cp110-icu"
13 - reg: Should contain ICU registers location and length.
15 - #interrupt-cells: Specifies the number of cells needed to encode an
16 interrupt source. The value shall be 3.
18 The 1st cell is the group type of the ICU interrupt. Possible group
21 ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
22 ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
23 ICU_GRP_SEI (0x4) : System error interrupt
24 ICU_GRP_REI (0x5) : RAM error interrupt
26 The 2nd cell is the index of the interrupt in the ICU unit.
28 The 3rd cell is the type of the interrupt. See arm,gic.txt for
31 - interrupt-controller: Identifies the node as an interrupt
34 - msi-parent: Should point to the GICP controller, the GIC extension
35 that allows to trigger interrupts using MSG memory mapped
40 icu: interrupt-controller@1e0000 {
41 compatible = "marvell,cp110-icu";
42 reg = <0x1e0000 0x10>;
43 #interrupt-cells = <3>;
49 interrupt-parent = <&icu>;
50 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;