Documentation/devicetree/bindings/media/mediatek-mdp.txt

   1 * Mediatek Media Data Path
   2
   3 Media Data Path is used for scaling and color space conversion.
   4
   5 Required properties (controller node):
   6 - compatible: "mediatek,mt8173-mdp"
   7 - mediatek,vpu: the node of video processor unit, see
   8   Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
   9
  10 Required properties (all function blocks, child node):
  11 - compatible: Should be one of
  12         "mediatek,mt8173-mdp-rdma"  - read DMA
  13         "mediatek,mt8173-mdp-rsz"   - resizer
  14         "mediatek,mt8173-mdp-wdma"  - write DMA
  15         "mediatek,mt8173-mdp-wrot"  - write DMA with rotation
  16 - reg: Physical base address and length of the function block register space
  17 - clocks: device clocks, see
  18   Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  19 - power-domains: a phandle to the power domain, see
  20   Documentation/devicetree/bindings/power/power_domain.txt for details.
  21
  22 Required properties (DMA function blocks, child node):
  23 - compatible: Should be one of
  24         "mediatek,mt8173-mdp-rdma"
  25         "mediatek,mt8173-mdp-wdma"
  26         "mediatek,mt8173-mdp-wrot"
  27 - iommus: should point to the respective IOMMU block with master port as
  28   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
  29   for details.
  30 - mediatek,larb: must contain the local arbiters in the current Socs, see
  31   Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
  32   for details.
  33
  34 Example:
  35         mdp_rdma0: rdma@14001000 {
  36                 compatible = "mediatek,mt8173-mdp-rdma";
  37                              "mediatek,mt8173-mdp";
  38                 reg = <0 0x14001000 0 0x1000>;
  39                 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
  40                          <&mmsys CLK_MM_MUTEX_32K>;
  41                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  42                 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
  43                 mediatek,larb = <&larb0>;
  44                 mediatek,vpu = <&vpu>;
  45         };
  46
  47         mdp_rdma1: rdma@14002000 {
  48                 compatible = "mediatek,mt8173-mdp-rdma";
  49                 reg = <0 0x14002000 0 0x1000>;
  50                 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
  51                          <&mmsys CLK_MM_MUTEX_32K>;
  52                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  53                 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
  54                 mediatek,larb = <&larb4>;
  55         };
  56
  57         mdp_rsz0: rsz@14003000 {
  58                 compatible = "mediatek,mt8173-mdp-rsz";
  59                 reg = <0 0x14003000 0 0x1000>;
  60                 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
  61                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  62         };
  63
  64         mdp_rsz1: rsz@14004000 {
  65                 compatible = "mediatek,mt8173-mdp-rsz";
  66                 reg = <0 0x14004000 0 0x1000>;
  67                 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
  68                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  69         };
  70
  71         mdp_rsz2: rsz@14005000 {
  72                 compatible = "mediatek,mt8173-mdp-rsz";
  73                 reg = <0 0x14005000 0 0x1000>;
  74                 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
  75                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  76         };
  77
  78         mdp_wdma0: wdma@14006000 {
  79                 compatible = "mediatek,mt8173-mdp-wdma";
  80                 reg = <0 0x14006000 0 0x1000>;
  81                 clocks = <&mmsys CLK_MM_MDP_WDMA>;
  82                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  83                 iommus = <&iommu M4U_PORT_MDP_WDMA>;
  84                 mediatek,larb = <&larb0>;
  85         };
  86
  87         mdp_wrot0: wrot@14007000 {
  88                 compatible = "mediatek,mt8173-mdp-wrot";
  89                 reg = <0 0x14007000 0 0x1000>;
  90                 clocks = <&mmsys CLK_MM_MDP_WROT0>;
  91                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  92                 iommus = <&iommu M4U_PORT_MDP_WROT0>;
  93                 mediatek,larb = <&larb0>;
  94         };
  95
  96         mdp_wrot1: wrot@14008000 {
  97                 compatible = "mediatek,mt8173-mdp-wrot";
  98                 reg = <0 0x14008000 0 0x1000>;
  99                 clocks = <&mmsys CLK_MM_MDP_WROT1>;
 100                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 101                 iommus = <&iommu M4U_PORT_MDP_WROT1>;
 102                 mediatek,larb = <&larb4>;
 103         };