1 NVIDIA Tegra Video Decoder Engine
4 - compatible : Must contain one of the following values:
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
21 - iram : Must contain phandle to the mmio-sram device node that represents
22 IRAM region used by VDE.
23 - interrupts : Must contain an entry for each entry in interrupt-names.
24 - interrupt-names : Must include the following entries:
28 - clocks : Must include the following entries:
30 - resets : Must include the following entries:
35 video-codec@6001a000 {
36 compatible = "nvidia,tegra20-vde";
37 reg = <0x6001a000 0x1000 /* Syntax Engine */
38 0x6001b000 0x1000 /* Video Bitstream Engine */
39 0x6001c000 0x100 /* Macroblock Engine */
40 0x6001c200 0x100 /* Post-processing Engine */
41 0x6001c400 0x100 /* Motion Compensation Engine */
42 0x6001c600 0x100 /* Transform Engine */
43 0x6001c800 0x100 /* Pixel prediction block */
44 0x6001ca00 0x100 /* Video DMA */
45 0x6001d800 0x300 /* Video frame controls */>;
46 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
47 "tfe", "ppb", "vdma", "frameid";
48 iram = <&vde_pool>; /* IRAM region */
49 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
50 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
51 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
52 interrupt-names = "sync-token", "bsev", "sxe";
53 clocks = <&tegra_car TEGRA20_CLK_VDE>;
54 resets = <&tegra_car 61>;