| blob | 6173af6885f86731a9e81182737afc0a185cd212 |
1 * Marvell EBU PCIe interfaces
3 Mandatory properties:
5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
15 - ranges: ranges describing the MMIO registers to control the PCIe
16 interfaces, and ranges describing the MBus windows needed to access
17 the memory and I/O regions of each PCIe interface.
18 - msi-parent: Link to the hardware entity that serves as the Message
19 Signaled Interrupt controller for this PCI controller.
21 The ranges describing the MMIO registers have the following layout:
23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
25 where:
27 * r is a 32-bits value that gives the offset of the MMIO
28 registers of this PCIe interface, from the base of the internal
29 registers.
31 * s is a 32-bits value that give the size of this MMIO
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
37 The ranges describing the MBus windows have the following layout:
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
41 where:
43 * t is the type of the MBus window (as defined by the standard PCI DT
44 bindings), 1 for I/O and 2 for memory.
46 * s is the PCI slot that corresponds to this PCIe interface
48 * w is the 'target ID' value for the MBus window
50 * a the 'attribute' value for the MBus window.
52 Since the location and size of the different MBus windows is not fixed in
53 hardware, and only determined in runtime, those ranges cover the full first
54 4 GB of the physical address space, and do not translate into a valid CPU
55 address.
57 In addition, the device tree node must have sub-nodes describing each
58 PCIe interface, having the following mandatory properties:
60 - reg: used only for interrupt mapping, so only the first four bytes
61 are used to refer to the correct bus number and device number.
62 - assigned-addresses: reference to the MMIO registers used to control
63 this PCIe interface.
64 - clocks: the clock associated to this PCIe interface
65 - marvell,pcie-port: the physical PCIe port number
66 - status: either "disabled" or "okay"
67 - device_type, set to "pci"
68 - #address-cells, set to <3>
69 - #size-cells, set to <2>
70 - #interrupt-cells, set to <1>
71 - ranges, translating the MBus windows ranges of the parent node into
72 standard PCI addresses.
73 - interrupt-map-mask and interrupt-map, standard PCI properties to
74 define the mapping of the PCIe interface to interrupt numbers.
76 and the following optional properties:
77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
78 multiple lanes. If this property is not found, we assume that the
79 value is 0.
80 - reset-gpios: optional GPIO to PERST#
81 - reset-delay-us: delay in us to wait after reset de-assertion, if not
82 specified will default to 100ms, as required by the PCIe specification.
84 Example:
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
88 device_type = "pci";
90 #address-cells = <3>;
91 #size-cells = <2>;
93 bus-range = <0x00 0xff>;
94 msi-parent = <&mpic>;
96 ranges =
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
99 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
100 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
101 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
102 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
103 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
104 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
105 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
106 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
107 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
108 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
109 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
110 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
111 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
112 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
113 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
114 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
116 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
117 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
118 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
119 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
120 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
121 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
122 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
123 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
125 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
126 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
128 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
129 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
131 pcie@1,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
134 reg = <0x0800 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
139 0x81000000 0 0 0x81000000 0x1 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 58>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <0>;
144 /* low-active PERST# reset on GPIO 25 */
145 reset-gpios = <&gpio0 25 1>;
146 /* wait 20ms for device settle after reset deassertion */
147 reset-delay-us = <20000>;
148 clocks = <&gateclk 5>;
149 };
151 pcie@2,0 {
152 device_type = "pci";
153 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
154 reg = <0x1000 0 0 0 0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 #interrupt-cells = <1>;
158 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
159 0x81000000 0 0 0x81000000 0x2 0 1 0>;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 59>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <1>;
164 clocks = <&gateclk 6>;
165 };
167 pcie@3,0 {
168 device_type = "pci";
169 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
170 reg = <0x1800 0 0 0 0>;
171 #address-cells = <3>;
172 #size-cells = <2>;
173 #interrupt-cells = <1>;
174 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
175 0x81000000 0 0 0x81000000 0x3 0 1 0>;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 60>;
178 marvell,pcie-port = <0>;
179 marvell,pcie-lane = <2>;
180 clocks = <&gateclk 7>;
181 };
183 pcie@4,0 {
184 device_type = "pci";
185 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
186 reg = <0x2000 0 0 0 0>;
187 #address-cells = <3>;
188 #size-cells = <2>;
189 #interrupt-cells = <1>;
190 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
191 0x81000000 0 0 0x81000000 0x4 0 1 0>;
192 interrupt-map-mask = <0 0 0 0>;
193 interrupt-map = <0 0 0 0 &mpic 61>;
194 marvell,pcie-port = <0>;
195 marvell,pcie-lane = <3>;
196 clocks = <&gateclk 8>;
197 };
199 pcie@5,0 {
200 device_type = "pci";
201 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
202 reg = <0x2800 0 0 0 0>;
203 #address-cells = <3>;
204 #size-cells = <2>;
205 #interrupt-cells = <1>;
206 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
207 0x81000000 0 0 0x81000000 0x5 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 62>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <0>;
212 clocks = <&gateclk 9>;
213 };
215 pcie@6,0 {
216 device_type = "pci";
217 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
218 reg = <0x3000 0 0 0 0>;
219 #address-cells = <3>;
220 #size-cells = <2>;
221 #interrupt-cells = <1>;
222 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
223 0x81000000 0 0 0x81000000 0x6 0 1 0>;
224 interrupt-map-mask = <0 0 0 0>;
225 interrupt-map = <0 0 0 0 &mpic 63>;
226 marvell,pcie-port = <1>;
227 marvell,pcie-lane = <1>;
228 clocks = <&gateclk 10>;
229 };
231 pcie@7,0 {
232 device_type = "pci";
233 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
234 reg = <0x3800 0 0 0 0>;
235 #address-cells = <3>;
236 #size-cells = <2>;
237 #interrupt-cells = <1>;
238 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
239 0x81000000 0 0 0x81000000 0x7 0 1 0>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &mpic 64>;
242 marvell,pcie-port = <1>;
243 marvell,pcie-lane = <2>;
244 clocks = <&gateclk 11>;
245 };
247 pcie@8,0 {
248 device_type = "pci";
249 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
250 reg = <0x4000 0 0 0 0>;
251 #address-cells = <3>;
252 #size-cells = <2>;
253 #interrupt-cells = <1>;
254 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
255 0x81000000 0 0 0x81000000 0x8 0 1 0>;
256 interrupt-map-mask = <0 0 0 0>;
257 interrupt-map = <0 0 0 0 &mpic 65>;
258 marvell,pcie-port = <1>;
259 marvell,pcie-lane = <3>;
260 clocks = <&gateclk 12>;
261 };
263 pcie@9,0 {
264 device_type = "pci";
265 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
266 reg = <0x4800 0 0 0 0>;
267 #address-cells = <3>;
268 #size-cells = <2>;
269 #interrupt-cells = <1>;
270 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
271 0x81000000 0 0 0x81000000 0x9 0 1 0>;
272 interrupt-map-mask = <0 0 0 0>;
273 interrupt-map = <0 0 0 0 &mpic 99>;
274 marvell,pcie-port = <2>;
275 marvell,pcie-lane = <0>;
276 clocks = <&gateclk 26>;
277 };
279 pcie@a,0 {
280 device_type = "pci";
281 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
282 reg = <0x5000 0 0 0 0>;
283 #address-cells = <3>;
284 #size-cells = <2>;
285 #interrupt-cells = <1>;
286 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
287 0x81000000 0 0 0x81000000 0xa 0 1 0>;
288 interrupt-map-mask = <0 0 0 0>;
289 interrupt-map = <0 0 0 0 &mpic 103>;
290 marvell,pcie-port = <3>;
291 marvell,pcie-lane = <0>;
292 clocks = <&gateclk 27>;
293 };
294 };