| blob | 145a4f04194fa053f069e478bad6f0a59feb00b1 |
1 NVIDIA Tegra PCIe controller
3 Required properties:
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
12 for Tegra186.
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
16 - reg-names: Must include the following entries:
17 "pads": PADS registers
18 "afi": AFI registers
19 "cs": configuration space region
20 - interrupts: A list of interrupt outputs of the controller. Must contain an
21 entry for each entry in the interrupt-names property.
22 - interrupt-names: Must include the following entries:
23 "intr": The Tegra interrupt that is asserted for controller interrupts
24 "msi": The Tegra interrupt that is asserted when an MSI is received
25 - bus-range: Range of bus numbers associated with this controller
26 - #address-cells: Address representation for root ports (must be 3)
27 - cell 0 specifies the bus and device numbers of the root port:
28 [23:16]: bus number
29 [15:11]: device number
30 - cell 1 denotes the upper 32 address bits and should be 0
31 - cell 2 contains the lower 32 address bits and is used to translate to the
32 CPU address space
33 - #size-cells: Size representation for root ports (must be 2)
34 - ranges: Describes the translation of addresses for root ports and standard
35 PCI regions. The entries must be 6 cells each, where the first three cells
36 correspond to the address as described for the #address-cells property
37 above, the fourth cell is the physical CPU address to translate to and the
38 fifth and six cells are as described for the #size-cells property above.
39 - The first two entries are expected to translate the addresses for the root
40 port registers, which are referenced by the assigned-addresses property of
41 the root port nodes (see below).
42 - The remaining entries setup the mapping for the standard I/O, memory and
43 prefetchable PCI regions. The first cell determines the type of region
44 that is setup:
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
48 Please refer to the standard PCI bus binding document for a more detailed
49 explanation.
50 - #interrupt-cells: Size representation for interrupts (must be 1)
51 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
52 Please refer to the standard PCI bus binding document for a more detailed
53 explanation.
54 - clocks: Must contain an entry for each entry in clock-names.
55 See ../clocks/clock-bindings.txt for details.
56 - clock-names: Must include the following entries:
57 - pex
58 - afi
59 - pll_e
60 - cml (not required for Tegra20)
61 - resets: Must contain an entry for each entry in reset-names.
62 See ../reset/reset.txt for details.
63 - reset-names: Must include the following entries:
64 - pex
65 - afi
66 - pcie_x
68 Required properties on Tegra124 and later (deprecated):
69 - phys: Must contain an entry for each entry in phy-names.
70 - phy-names: Must include the following entries:
71 - pcie
73 These properties are deprecated in favour of per-lane PHYs define in each of
74 the root ports (see below).
76 Power supplies for Tegra20:
77 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
78 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
79 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
80 supply 1.05 V.
81 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
82 supply 1.05 V.
83 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
85 Power supplies for Tegra30:
86 - Required:
87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
88 supply 1.05 V.
89 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
90 supply 1.05 V.
91 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
92 supply 1.8 V.
93 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
94 Must supply 3.3 V.
95 - Optional:
96 - If lanes 0 to 3 are used:
97 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
98 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
99 - If lanes 4 or 5 are used:
100 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
101 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
103 Power supplies for Tegra124:
104 - Required:
105 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
106 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
107 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
108 supply 1.05 V.
109 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
110 Must supply 3.3 V.
111 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
112 Must supply 3.3 V.
113 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
114 supply 2.8-3.3 V.
115 - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
116 supply 1.05 V.
118 Power supplies for Tegra210:
119 - Required:
120 - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must
121 supply 1.05 V.
122 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
123 clocks. Must supply 1.8 V.
124 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
125 - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
126 supply 1.05 V.
127 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
128 Must supply 3.3 V.
129 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
130 supply 1.8 V.
132 Power supplies for Tegra186:
133 - Required:
134 - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
135 - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
136 supply 1.8 V.
137 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
138 Must supply 1.8 V.
139 - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
140 supply 1.8 V.
142 Root ports are defined as subnodes of the PCIe controller node.
144 Required properties:
145 - device_type: Must be "pci"
146 - assigned-addresses: Address and size of the port configuration registers
147 - reg: PCI bus address of the root port
148 - #address-cells: Must be 3
149 - #size-cells: Must be 2
150 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
151 property is sufficient.
152 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
153 are:
154 - Root port 0 uses 4 lanes, root port 1 is unused.
155 - Both root ports use 2 lanes.
157 Required properties for Tegra124 and later:
158 - phys: Must contain an phandle to a PHY for each entry in phy-names.
159 - phy-names: Must include an entry for each active lane. Note that the number
160 of entries does not have to (though usually will) be equal to the specified
161 number of lanes in the nvidia,num-lanes property. Entries are of the form
162 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
164 Examples:
165 =========
167 Tegra20:
168 --------
170 SoC DTSI:
172 pcie-controller@80003000 {
173 compatible = "nvidia,tegra20-pcie";
174 device_type = "pci";
175 reg = <0x80003000 0x00000800 /* PADS registers */
176 0x80003800 0x00000200 /* AFI registers */
177 0x90000000 0x10000000>; /* configuration space */
178 reg-names = "pads", "afi", "cs";
179 interrupts = <0 98 0x04 /* controller interrupt */
180 0 99 0x04>; /* MSI interrupt */
181 interrupt-names = "intr", "msi";
183 #interrupt-cells = <1>;
184 interrupt-map-mask = <0 0 0 0>;
185 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
187 bus-range = <0x00 0xff>;
188 #address-cells = <3>;
189 #size-cells = <2>;
191 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
192 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
193 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
194 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
195 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
197 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
198 clock-names = "pex", "afi", "pll_e";
199 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
200 reset-names = "pex", "afi", "pcie_x";
201 status = "disabled";
203 pci@1,0 {
204 device_type = "pci";
205 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
206 reg = <0x000800 0 0 0 0>;
207 status = "disabled";
209 #address-cells = <3>;
210 #size-cells = <2>;
212 ranges;
214 nvidia,num-lanes = <2>;
215 };
217 pci@2,0 {
218 device_type = "pci";
219 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
220 reg = <0x001000 0 0 0 0>;
221 status = "disabled";
223 #address-cells = <3>;
224 #size-cells = <2>;
226 ranges;
228 nvidia,num-lanes = <2>;
229 };
230 };
232 Board DTS:
234 pcie-controller@80003000 {
235 status = "okay";
237 vdd-supply = <&pci_vdd_reg>;
238 pex-clk-supply = <&pci_clk_reg>;
240 /* root port 00:01.0 */
241 pci@1,0 {
242 status = "okay";
244 /* bridge 01:00.0 (optional) */
245 pci@0,0 {
246 reg = <0x010000 0 0 0 0>;
248 #address-cells = <3>;
249 #size-cells = <2>;
251 device_type = "pci";
253 /* endpoint 02:00.0 */
254 pci@0,0 {
255 reg = <0x020000 0 0 0 0>;
256 };
257 };
258 };
259 };
261 Note that devices on the PCI bus are dynamically discovered using PCI's bus
262 enumeration and therefore don't need corresponding device nodes in DT. However
263 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
264 device nodes need to be added in order to allow the bus' children to be
265 instantiated at the proper location in the operating system's device tree (as
266 illustrated by the optional nodes in the example above).
268 Tegra30:
269 --------
271 SoC DTSI:
273 pcie-controller@3000 {
274 compatible = "nvidia,tegra30-pcie";
275 device_type = "pci";
276 reg = <0x00003000 0x00000800 /* PADS registers */
277 0x00003800 0x00000200 /* AFI registers */
278 0x10000000 0x10000000>; /* configuration space */
279 reg-names = "pads", "afi", "cs";
280 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
281 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
282 interrupt-names = "intr", "msi";
284 #interrupt-cells = <1>;
285 interrupt-map-mask = <0 0 0 0>;
286 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
288 bus-range = <0x00 0xff>;
289 #address-cells = <3>;
290 #size-cells = <2>;
292 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
293 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
294 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
295 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
296 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
297 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
299 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
300 <&tegra_car TEGRA30_CLK_AFI>,
301 <&tegra_car TEGRA30_CLK_PLL_E>,
302 <&tegra_car TEGRA30_CLK_CML0>;
303 clock-names = "pex", "afi", "pll_e", "cml";
304 resets = <&tegra_car 70>,
305 <&tegra_car 72>,
306 <&tegra_car 74>;
307 reset-names = "pex", "afi", "pcie_x";
308 status = "disabled";
310 pci@1,0 {
311 device_type = "pci";
312 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
313 reg = <0x000800 0 0 0 0>;
314 status = "disabled";
316 #address-cells = <3>;
317 #size-cells = <2>;
318 ranges;
320 nvidia,num-lanes = <2>;
321 };
323 pci@2,0 {
324 device_type = "pci";
325 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
326 reg = <0x001000 0 0 0 0>;
327 status = "disabled";
329 #address-cells = <3>;
330 #size-cells = <2>;
331 ranges;
333 nvidia,num-lanes = <2>;
334 };
336 pci@3,0 {
337 device_type = "pci";
338 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
339 reg = <0x001800 0 0 0 0>;
340 status = "disabled";
342 #address-cells = <3>;
343 #size-cells = <2>;
344 ranges;
346 nvidia,num-lanes = <2>;
347 };
348 };
350 Board DTS:
352 pcie-controller@3000 {
353 status = "okay";
355 avdd-pexa-supply = <&ldo1_reg>;
356 vdd-pexa-supply = <&ldo1_reg>;
357 avdd-pexb-supply = <&ldo1_reg>;
358 vdd-pexb-supply = <&ldo1_reg>;
359 avdd-pex-pll-supply = <&ldo1_reg>;
360 avdd-plle-supply = <&ldo1_reg>;
361 vddio-pex-ctl-supply = <&sys_3v3_reg>;
362 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
364 pci@1,0 {
365 status = "okay";
366 };
368 pci@3,0 {
369 status = "okay";
370 };
371 };
373 Tegra124:
374 ---------
376 SoC DTSI:
378 pcie-controller@1003000 {
379 compatible = "nvidia,tegra124-pcie";
380 device_type = "pci";
381 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
382 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
383 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
384 reg-names = "pads", "afi", "cs";
385 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
386 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
387 interrupt-names = "intr", "msi";
389 #interrupt-cells = <1>;
390 interrupt-map-mask = <0 0 0 0>;
391 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
393 bus-range = <0x00 0xff>;
394 #address-cells = <3>;
395 #size-cells = <2>;
397 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
398 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
399 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
400 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
401 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
403 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
404 <&tegra_car TEGRA124_CLK_AFI>,
405 <&tegra_car TEGRA124_CLK_PLL_E>,
406 <&tegra_car TEGRA124_CLK_CML0>;
407 clock-names = "pex", "afi", "pll_e", "cml";
408 resets = <&tegra_car 70>,
409 <&tegra_car 72>,
410 <&tegra_car 74>;
411 reset-names = "pex", "afi", "pcie_x";
412 status = "disabled";
414 pci@1,0 {
415 device_type = "pci";
416 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
417 reg = <0x000800 0 0 0 0>;
418 status = "disabled";
420 #address-cells = <3>;
421 #size-cells = <2>;
422 ranges;
424 nvidia,num-lanes = <2>;
425 };
427 pci@2,0 {
428 device_type = "pci";
429 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
430 reg = <0x001000 0 0 0 0>;
431 status = "disabled";
433 #address-cells = <3>;
434 #size-cells = <2>;
435 ranges;
437 nvidia,num-lanes = <1>;
438 };
439 };
441 Board DTS:
443 pcie-controller@1003000 {
444 status = "okay";
446 avddio-pex-supply = <&vdd_1v05_run>;
447 dvddio-pex-supply = <&vdd_1v05_run>;
448 avdd-pex-pll-supply = <&vdd_1v05_run>;
449 hvdd-pex-supply = <&vdd_3v3_lp0>;
450 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
451 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
452 avdd-pll-erefe-supply = <&avdd_1v05_run>;
454 /* Mini PCIe */
455 pci@1,0 {
456 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
457 phy-names = "pcie-0";
458 status = "okay";
459 };
461 /* Gigabit Ethernet */
462 pci@2,0 {
463 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
464 phy-names = "pcie-0";
465 status = "okay";
466 };
467 };
469 Tegra210:
470 ---------
472 SoC DTSI:
474 pcie-controller@1003000 {
475 compatible = "nvidia,tegra210-pcie";
476 device_type = "pci";
477 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
478 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
479 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
480 reg-names = "pads", "afi", "cs";
481 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
482 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
483 interrupt-names = "intr", "msi";
485 #interrupt-cells = <1>;
486 interrupt-map-mask = <0 0 0 0>;
487 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
489 bus-range = <0x00 0xff>;
490 #address-cells = <3>;
491 #size-cells = <2>;
493 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
494 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
495 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
496 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
497 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
499 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
500 <&tegra_car TEGRA210_CLK_AFI>,
501 <&tegra_car TEGRA210_CLK_PLL_E>,
502 <&tegra_car TEGRA210_CLK_CML0>;
503 clock-names = "pex", "afi", "pll_e", "cml";
504 resets = <&tegra_car 70>,
505 <&tegra_car 72>,
506 <&tegra_car 74>;
507 reset-names = "pex", "afi", "pcie_x";
508 status = "disabled";
510 pci@1,0 {
511 device_type = "pci";
512 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
513 reg = <0x000800 0 0 0 0>;
514 status = "disabled";
516 #address-cells = <3>;
517 #size-cells = <2>;
518 ranges;
520 nvidia,num-lanes = <4>;
521 };
523 pci@2,0 {
524 device_type = "pci";
525 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
526 reg = <0x001000 0 0 0 0>;
527 status = "disabled";
529 #address-cells = <3>;
530 #size-cells = <2>;
531 ranges;
533 nvidia,num-lanes = <1>;
534 };
535 };
537 Board DTS:
539 pcie-controller@1003000 {
540 status = "okay";
542 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
543 hvddio-pex-supply = <&vdd_1v8>;
544 dvddio-pex-supply = <&vdd_pex_1v05>;
545 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
546 hvdd-pex-pll-e-supply = <&vdd_1v8>;
547 vddio-pex-ctl-supply = <&vdd_1v8>;
549 pci@1,0 {
550 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
551 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
552 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
553 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
554 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
555 status = "okay";
556 };
558 pci@2,0 {
559 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
560 phy-names = "pcie-0";
561 status = "okay";
562 };
563 };
565 Tegra186:
566 ---------
568 SoC DTSI:
570 pcie@10003000 {
571 compatible = "nvidia,tegra186-pcie";
572 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
573 device_type = "pci";
574 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
575 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
576 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
577 reg-names = "pads", "afi", "cs";
579 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
580 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
581 interrupt-names = "intr", "msi";
583 #interrupt-cells = <1>;
584 interrupt-map-mask = <0 0 0 0>;
585 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
587 bus-range = <0x00 0xff>;
588 #address-cells = <3>;
589 #size-cells = <2>;
591 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
592 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
593 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
594 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
595 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
596 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
598 clocks = <&bpmp TEGRA186_CLK_AFI>,
599 <&bpmp TEGRA186_CLK_PCIE>,
600 <&bpmp TEGRA186_CLK_PLLE>;
601 clock-names = "afi", "pex", "pll_e";
603 resets = <&bpmp TEGRA186_RESET_AFI>,
604 <&bpmp TEGRA186_RESET_PCIE>,
605 <&bpmp TEGRA186_RESET_PCIEXCLK>;
606 reset-names = "afi", "pex", "pcie_x";
608 status = "disabled";
610 pci@1,0 {
611 device_type = "pci";
612 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
613 reg = <0x000800 0 0 0 0>;
614 status = "disabled";
616 #address-cells = <3>;
617 #size-cells = <2>;
618 ranges;
620 nvidia,num-lanes = <2>;
621 };
623 pci@2,0 {
624 device_type = "pci";
625 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
626 reg = <0x001000 0 0 0 0>;
627 status = "disabled";
629 #address-cells = <3>;
630 #size-cells = <2>;
631 ranges;
633 nvidia,num-lanes = <1>;
634 };
636 pci@3,0 {
637 device_type = "pci";
638 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
639 reg = <0x001800 0 0 0 0>;
640 status = "disabled";
642 #address-cells = <3>;
643 #size-cells = <2>;
644 ranges;
646 nvidia,num-lanes = <1>;
647 };
648 };
650 Board DTS:
652 pcie@10003000 {
653 status = "okay";
655 dvdd-pex-supply = <&vdd_pex>;
656 hvdd-pex-pll-supply = <&vdd_1v8>;
657 hvdd-pex-supply = <&vdd_1v8>;
658 vddio-pexctl-aud-supply = <&vdd_1v8>;
660 pci@1,0 {
661 nvidia,num-lanes = <4>;
662 status = "okay";
663 };
665 pci@2,0 {
666 nvidia,num-lanes = <0>;
667 status = "disabled";
668 };
670 pci@3,0 {
671 nvidia,num-lanes = <1>;
672 status = "disabled";
673 };
674 };