1 TI Keystone DSP devices
2 =======================
4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
5 sub-systems that are used to offload some of the processor-intensive tasks or
6 algorithms, for achieving various system level goals.
8 These processor sub-systems usually contain additional sub-modules like L1
9 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
16 have an alias with the stem 'rproc' defined. Each node has a number of required
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
23 The following are the mandatory properties:
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
31 - reg: Should contain an entry for each value in 'reg-names'.
32 Each entry should have the memory region's start address
33 and the size of the region, the representation matching
34 the parent node's '#address-cells' and '#size-cells' values.
36 - reg-names: Should contain strings with the following names, each
37 representing a specific internal memory region, and
38 should be defined in this order,
39 "l2sram", "l1pram", "l1dram"
41 - ti,syscon-dev: Should be a pair of the phandle to the Keystone Device
42 State Control node, and the register offset of the DSP
43 boot address register within that node's address space.
45 - resets: Should contain the phandle to the reset controller node
46 managing the resets for this device, and a reset
47 specifier. Please refer to either of the following reset
48 bindings for the reset argument specifier as per SoC,
49 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
50 for 66AK2HK/66AK2L/66AK2E SoCs or,
51 Documentation/devicetree/bindings/reset/ti,sci-reset.txt
54 - interrupt-parent: Should contain a phandle to the Keystone 2 IRQ controller
55 IP node that is used by the ARM CorePac processor to
56 receive interrupts from the DSP remote processors. See
57 Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
60 - interrupts: Should contain an entry for each value in 'interrupt-names'.
61 Each entry should have the interrupt source number used by
62 the remote processor to the host processor. The values should
63 follow the interrupt-specifier format as dictated by the
64 'interrupt-parent' node. The purpose of each is as per the
65 description in the 'interrupt-names' property.
67 - interrupt-names: Should contain strings with the following names, each
68 representing a specific interrupt,
69 "vring" - interrupt for virtio based IPC
70 "exception" - interrupt for exception notification
72 - kick-gpios: Should specify the gpio device needed for the virtio IPC
73 stack. This will be used to interrupt the remote processor.
74 The gpio device to be used is as per the bindings in,
75 Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
77 SoC-specific Required properties:
78 ---------------------------------
79 The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
82 - clocks: Should contain the device's input clock, and should be
83 defined as per the bindings in,
84 Documentation/devicetree/bindings/clock/keystone-gate.txt
86 The following are mandatory properties for Keystone 2 66AK2G SoCs only:
88 - power-domains: Should contain a phandle to a PM domain provider node
89 and an args specifier containing the DSP device id
90 value. This property is as per the binding,
91 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
96 - memory-region: phandle to the reserved memory node to be associated
97 with the remoteproc device. The reserved memory node
98 can be a CMA memory node, and should be defined as
100 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
107 /* 66AK2H/K DSP aliases */
119 /* 66AK2H/K DSP memory node */
121 #address-cells = <2>;
125 dsp_common_memory: dsp-common-memory@81f800000 {
126 compatible = "shared-dma-pool";
127 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
132 /* 66AK2H/K DSP node */
135 compatible = "ti,k2hk-dsp";
136 reg = <0x10800000 0x00100000>,
137 <0x10e00000 0x00008000>,
138 <0x10f00000 0x00008000>;
139 reg-names = "l2sram", "l1pram", "l1dram";
141 ti,syscon-dev = <&devctrl 0x40>;
142 resets = <&pscrst 0>;
143 interrupt-parent = <&kirq0>;
145 interrupt-names = "vring", "exception";
146 kick-gpios = <&dspgpio0 27 0>;
147 memory-region = <&dsp_common_memory>;
153 /* 66AK2G DSP alias */
158 /* 66AK2G DSP memory node */
160 #address-cells = <2>;
164 dsp_common_memory: dsp-common-memory@81f800000 {
165 compatible = "shared-dma-pool";
166 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
171 /* 66AK2G DSP node */
174 compatible = "ti,k2g-dsp";
175 reg = <0x10800000 0x00100000>,
176 <0x10e00000 0x00008000>,
177 <0x10f00000 0x00008000>;
178 reg-names = "l2sram", "l1pram", "l1dram";
179 power-domains = <&k2g_pds 0x0046>;
180 ti,syscon-dev = <&devctrl 0x40>;
181 resets = <&k2g_reset 0x0046 0x1>;
182 interrupt-parent = <&kirq0>;
184 interrupt-names = "vring", "exception";
185 kick-gpios = <&dspgpio0 27 0>;
186 memory-region = <&dsp_common_memory>;