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rtc: stm32: fix misspelling and misalignment issues
[linux/fpc-iii.git] / drivers / net / ethernet / chelsio / cxgb4 / t4fw_api.h
blobe3d4751f21ac9665f5f427f0e7b82dc61fc73833
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
37
38 enum fw_retval {
39 FW_SUCCESS = 0, /* completed successfully */
40 FW_EPERM = 1, /* operation not permitted */
41 FW_ENOENT = 2, /* no such file or directory */
42 FW_EIO = 5, /* input/output error; hw bad */
43 FW_ENOEXEC = 8, /* exec format error; inv microcode */
44 FW_EAGAIN = 11, /* try again */
45 FW_ENOMEM = 12, /* out of memory */
46 FW_EFAULT = 14, /* bad address; fw bad */
47 FW_EBUSY = 16, /* resource busy */
48 FW_EEXIST = 17, /* file exists */
49 FW_ENODEV = 19, /* no such device */
50 FW_EINVAL = 22, /* invalid argument */
51 FW_ENOSPC = 28, /* no space left on device */
52 FW_ENOSYS = 38, /* functionality not implemented */
53 FW_ENODATA = 61, /* no data available */
54 FW_EPROTO = 71, /* protocol error */
55 FW_EADDRINUSE = 98, /* address already in use */
56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
57 FW_ENETDOWN = 100, /* network is down */
58 FW_ENETUNREACH = 101, /* network is unreachable */
59 FW_ENOBUFS = 105, /* no buffer space available */
60 FW_ETIMEDOUT = 110, /* timeout */
61 FW_EINPROGRESS = 115, /* fw internal */
62 FW_SCSI_ABORT_REQUESTED = 128, /* */
63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
64 FW_SCSI_ABORTED = 130, /* */
65 FW_SCSI_CLOSE_REQUESTED = 131, /* */
66 FW_ERR_LINK_DOWN = 132, /* */
67 FW_RDEV_NOT_READY = 133, /* */
68 FW_ERR_RDEV_LOST = 134, /* */
69 FW_ERR_RDEV_LOGO = 135, /* */
70 FW_FCOE_NO_XCHG = 136, /* */
71 FW_SCSI_RSP_ERR = 137, /* */
72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
74 FW_SCSI_OVER_FLOW_ERR = 140, /* */
75 FW_SCSI_DDP_ERR = 141, /* DDP error*/
76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
77 };
78
79 #define FW_T4VF_SGE_BASE_ADDR 0x0000
80 #define FW_T4VF_MPS_BASE_ADDR 0x0100
81 #define FW_T4VF_PL_BASE_ADDR 0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
83 #define FW_T4VF_CIM_BASE_ADDR 0x0300
84
85 enum fw_wr_opcodes {
86 FW_FILTER_WR = 0x02,
87 FW_ULPTX_WR = 0x04,
88 FW_TP_WR = 0x05,
89 FW_ETH_TX_PKT_WR = 0x08,
90 FW_OFLD_CONNECTION_WR = 0x2f,
91 FW_FLOWC_WR = 0x0a,
92 FW_OFLD_TX_DATA_WR = 0x0b,
93 FW_CMD_WR = 0x10,
94 FW_ETH_TX_PKT_VM_WR = 0x11,
95 FW_RI_RES_WR = 0x0c,
96 FW_RI_INIT_WR = 0x0d,
97 FW_RI_RDMA_WRITE_WR = 0x14,
98 FW_RI_SEND_WR = 0x15,
99 FW_RI_RDMA_READ_WR = 0x16,
100 FW_RI_RECV_WR = 0x17,
101 FW_RI_BIND_MW_WR = 0x18,
102 FW_RI_FR_NSMR_WR = 0x19,
103 FW_RI_FR_NSMR_TPTE_WR = 0x20,
104 FW_RI_RDMA_WRITE_CMPL_WR = 0x21,
105 FW_RI_INV_LSTAG_WR = 0x1a,
106 FW_ISCSI_TX_DATA_WR = 0x45,
107 FW_PTP_TX_PKT_WR = 0x46,
108 FW_TLSTX_DATA_WR = 0x68,
109 FW_CRYPTO_LOOKASIDE_WR = 0X6d,
110 FW_LASTC2E_WR = 0x70,
111 FW_FILTER2_WR = 0x77
112 };
113
114 struct fw_wr_hdr {
115 __be32 hi;
116 __be32 lo;
117 };
118
119 /* work request opcode (hi) */
120 #define FW_WR_OP_S 24
121 #define FW_WR_OP_M 0xff
122 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
123 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
124
125 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
126 #define FW_WR_ATOMIC_S 23
127 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
128
129 /* flush flag (hi) - firmware flushes flushable work request buffered
130 * in the flow context.
131 */
132 #define FW_WR_FLUSH_S 22
133 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
134
135 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
136 #define FW_WR_COMPL_S 21
137 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
138 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
139
140 /* work request immediate data length (hi) */
141 #define FW_WR_IMMDLEN_S 0
142 #define FW_WR_IMMDLEN_M 0xff
143 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
144
145 /* egress queue status update to associated ingress queue entry (lo) */
146 #define FW_WR_EQUIQ_S 31
147 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
148 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
149
150 /* egress queue status update to egress queue status entry (lo) */
151 #define FW_WR_EQUEQ_S 30
152 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
153 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
154
155 /* flow context identifier (lo) */
156 #define FW_WR_FLOWID_S 8
157 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
158
159 /* length in units of 16-bytes (lo) */
160 #define FW_WR_LEN16_S 0
161 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
162
163 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
164 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
165
166 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
167 enum fw_filter_wr_cookie {
168 FW_FILTER_WR_SUCCESS,
169 FW_FILTER_WR_FLT_ADDED,
170 FW_FILTER_WR_FLT_DELETED,
171 FW_FILTER_WR_SMT_TBL_FULL,
172 FW_FILTER_WR_EINVAL,
173 };
174
175 struct fw_filter_wr {
176 __be32 op_pkd;
177 __be32 len16_pkd;
178 __be64 r3;
179 __be32 tid_to_iq;
180 __be32 del_filter_to_l2tix;
181 __be16 ethtype;
182 __be16 ethtypem;
183 __u8 frag_to_ovlan_vldm;
184 __u8 smac_sel;
185 __be16 rx_chan_rx_rpl_iq;
186 __be32 maci_to_matchtypem;
187 __u8 ptcl;
188 __u8 ptclm;
189 __u8 ttyp;
190 __u8 ttypm;
191 __be16 ivlan;
192 __be16 ivlanm;
193 __be16 ovlan;
194 __be16 ovlanm;
195 __u8 lip[16];
196 __u8 lipm[16];
197 __u8 fip[16];
198 __u8 fipm[16];
199 __be16 lp;
200 __be16 lpm;
201 __be16 fp;
202 __be16 fpm;
203 __be16 r7;
204 __u8 sma[6];
205 };
206
207 struct fw_filter2_wr {
208 __be32 op_pkd;
209 __be32 len16_pkd;
210 __be64 r3;
211 __be32 tid_to_iq;
212 __be32 del_filter_to_l2tix;
213 __be16 ethtype;
214 __be16 ethtypem;
215 __u8 frag_to_ovlan_vldm;
216 __u8 smac_sel;
217 __be16 rx_chan_rx_rpl_iq;
218 __be32 maci_to_matchtypem;
219 __u8 ptcl;
220 __u8 ptclm;
221 __u8 ttyp;
222 __u8 ttypm;
223 __be16 ivlan;
224 __be16 ivlanm;
225 __be16 ovlan;
226 __be16 ovlanm;
227 __u8 lip[16];
228 __u8 lipm[16];
229 __u8 fip[16];
230 __u8 fipm[16];
231 __be16 lp;
232 __be16 lpm;
233 __be16 fp;
234 __be16 fpm;
235 __be16 r7;
236 __u8 sma[6];
237 __be16 r8;
238 __u8 filter_type_swapmac;
239 __u8 natmode_to_ulp_type;
240 __be16 newlport;
241 __be16 newfport;
242 __u8 newlip[16];
243 __u8 newfip[16];
244 __be32 natseqcheck;
245 __be32 r9;
246 __be64 r10;
247 __be64 r11;
248 __be64 r12;
249 __be64 r13;
250 };
251
252 #define FW_FILTER_WR_TID_S 12
253 #define FW_FILTER_WR_TID_M 0xfffff
254 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
255 #define FW_FILTER_WR_TID_G(x) \
256 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
257
258 #define FW_FILTER_WR_RQTYPE_S 11
259 #define FW_FILTER_WR_RQTYPE_M 0x1
260 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
261 #define FW_FILTER_WR_RQTYPE_G(x) \
262 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
263 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
264
265 #define FW_FILTER_WR_NOREPLY_S 10
266 #define FW_FILTER_WR_NOREPLY_M 0x1
267 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
268 #define FW_FILTER_WR_NOREPLY_G(x) \
269 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
270 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
271
272 #define FW_FILTER_WR_IQ_S 0
273 #define FW_FILTER_WR_IQ_M 0x3ff
274 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
275 #define FW_FILTER_WR_IQ_G(x) \
276 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
277
278 #define FW_FILTER_WR_DEL_FILTER_S 31
279 #define FW_FILTER_WR_DEL_FILTER_M 0x1
280 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
281 #define FW_FILTER_WR_DEL_FILTER_G(x) \
282 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
283 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
284
285 #define FW_FILTER_WR_RPTTID_S 25
286 #define FW_FILTER_WR_RPTTID_M 0x1
287 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
288 #define FW_FILTER_WR_RPTTID_G(x) \
289 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
290 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
291
292 #define FW_FILTER_WR_DROP_S 24
293 #define FW_FILTER_WR_DROP_M 0x1
294 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
295 #define FW_FILTER_WR_DROP_G(x) \
296 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
297 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
298
299 #define FW_FILTER_WR_DIRSTEER_S 23
300 #define FW_FILTER_WR_DIRSTEER_M 0x1
301 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
302 #define FW_FILTER_WR_DIRSTEER_G(x) \
303 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
304 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
305
306 #define FW_FILTER_WR_MASKHASH_S 22
307 #define FW_FILTER_WR_MASKHASH_M 0x1
308 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
309 #define FW_FILTER_WR_MASKHASH_G(x) \
310 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
311 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
312
313 #define FW_FILTER_WR_DIRSTEERHASH_S 21
314 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1
315 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
316 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \
317 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
318 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
319
320 #define FW_FILTER_WR_LPBK_S 20
321 #define FW_FILTER_WR_LPBK_M 0x1
322 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
323 #define FW_FILTER_WR_LPBK_G(x) \
324 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
325 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
326
327 #define FW_FILTER_WR_DMAC_S 19
328 #define FW_FILTER_WR_DMAC_M 0x1
329 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
330 #define FW_FILTER_WR_DMAC_G(x) \
331 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
332 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
333
334 #define FW_FILTER_WR_SMAC_S 18
335 #define FW_FILTER_WR_SMAC_M 0x1
336 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
337 #define FW_FILTER_WR_SMAC_G(x) \
338 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
339 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
340
341 #define FW_FILTER_WR_INSVLAN_S 17
342 #define FW_FILTER_WR_INSVLAN_M 0x1
343 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
344 #define FW_FILTER_WR_INSVLAN_G(x) \
345 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
346 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
347
348 #define FW_FILTER_WR_RMVLAN_S 16
349 #define FW_FILTER_WR_RMVLAN_M 0x1
350 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
351 #define FW_FILTER_WR_RMVLAN_G(x) \
352 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
353 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
354
355 #define FW_FILTER_WR_HITCNTS_S 15
356 #define FW_FILTER_WR_HITCNTS_M 0x1
357 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
358 #define FW_FILTER_WR_HITCNTS_G(x) \
359 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
360 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
361
362 #define FW_FILTER_WR_TXCHAN_S 13
363 #define FW_FILTER_WR_TXCHAN_M 0x3
364 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
365 #define FW_FILTER_WR_TXCHAN_G(x) \
366 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
367
368 #define FW_FILTER_WR_PRIO_S 12
369 #define FW_FILTER_WR_PRIO_M 0x1
370 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
371 #define FW_FILTER_WR_PRIO_G(x) \
372 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
373 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
374
375 #define FW_FILTER_WR_L2TIX_S 0
376 #define FW_FILTER_WR_L2TIX_M 0xfff
377 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
378 #define FW_FILTER_WR_L2TIX_G(x) \
379 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
380
381 #define FW_FILTER_WR_FRAG_S 7
382 #define FW_FILTER_WR_FRAG_M 0x1
383 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
384 #define FW_FILTER_WR_FRAG_G(x) \
385 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
386 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
387
388 #define FW_FILTER_WR_FRAGM_S 6
389 #define FW_FILTER_WR_FRAGM_M 0x1
390 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
391 #define FW_FILTER_WR_FRAGM_G(x) \
392 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
393 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
394
395 #define FW_FILTER_WR_IVLAN_VLD_S 5
396 #define FW_FILTER_WR_IVLAN_VLD_M 0x1
397 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
398 #define FW_FILTER_WR_IVLAN_VLD_G(x) \
399 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
400 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
401
402 #define FW_FILTER_WR_OVLAN_VLD_S 4
403 #define FW_FILTER_WR_OVLAN_VLD_M 0x1
404 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
405 #define FW_FILTER_WR_OVLAN_VLD_G(x) \
406 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
407 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
408
409 #define FW_FILTER_WR_IVLAN_VLDM_S 3
410 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1
411 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
412 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \
413 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
414 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
415
416 #define FW_FILTER_WR_OVLAN_VLDM_S 2
417 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1
418 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
419 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \
420 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
421 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
422
423 #define FW_FILTER_WR_RX_CHAN_S 15
424 #define FW_FILTER_WR_RX_CHAN_M 0x1
425 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
426 #define FW_FILTER_WR_RX_CHAN_G(x) \
427 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
428 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
429
430 #define FW_FILTER_WR_RX_RPL_IQ_S 0
431 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
432 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
433 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \
434 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
435
436 #define FW_FILTER2_WR_FILTER_TYPE_S 1
437 #define FW_FILTER2_WR_FILTER_TYPE_M 0x1
438 #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
439 #define FW_FILTER2_WR_FILTER_TYPE_G(x) \
440 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
441 #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U)
442
443 #define FW_FILTER2_WR_NATMODE_S 5
444 #define FW_FILTER2_WR_NATMODE_M 0x7
445 #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S)
446 #define FW_FILTER2_WR_NATMODE_G(x) \
447 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
448
449 #define FW_FILTER2_WR_NATFLAGCHECK_S 4
450 #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1
451 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
452 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
453 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
454 #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U)
455
456 #define FW_FILTER2_WR_ULP_TYPE_S 0
457 #define FW_FILTER2_WR_ULP_TYPE_M 0xf
458 #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S)
459 #define FW_FILTER2_WR_ULP_TYPE_G(x) \
460 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
461
462 #define FW_FILTER_WR_MACI_S 23
463 #define FW_FILTER_WR_MACI_M 0x1ff
464 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
465 #define FW_FILTER_WR_MACI_G(x) \
466 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
467
468 #define FW_FILTER_WR_MACIM_S 14
469 #define FW_FILTER_WR_MACIM_M 0x1ff
470 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
471 #define FW_FILTER_WR_MACIM_G(x) \
472 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
473
474 #define FW_FILTER_WR_FCOE_S 13
475 #define FW_FILTER_WR_FCOE_M 0x1
476 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
477 #define FW_FILTER_WR_FCOE_G(x) \
478 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
479 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
480
481 #define FW_FILTER_WR_FCOEM_S 12
482 #define FW_FILTER_WR_FCOEM_M 0x1
483 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
484 #define FW_FILTER_WR_FCOEM_G(x) \
485 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
486 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
487
488 #define FW_FILTER_WR_PORT_S 9
489 #define FW_FILTER_WR_PORT_M 0x7
490 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
491 #define FW_FILTER_WR_PORT_G(x) \
492 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
493
494 #define FW_FILTER_WR_PORTM_S 6
495 #define FW_FILTER_WR_PORTM_M 0x7
496 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
497 #define FW_FILTER_WR_PORTM_G(x) \
498 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
499
500 #define FW_FILTER_WR_MATCHTYPE_S 3
501 #define FW_FILTER_WR_MATCHTYPE_M 0x7
502 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
503 #define FW_FILTER_WR_MATCHTYPE_G(x) \
504 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
505
506 #define FW_FILTER_WR_MATCHTYPEM_S 0
507 #define FW_FILTER_WR_MATCHTYPEM_M 0x7
508 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
509 #define FW_FILTER_WR_MATCHTYPEM_G(x) \
510 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
511
512 struct fw_ulptx_wr {
513 __be32 op_to_compl;
514 __be32 flowid_len16;
515 u64 cookie;
516 };
517
518 #define FW_ULPTX_WR_DATA_S 28
519 #define FW_ULPTX_WR_DATA_M 0x1
520 #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S)
521 #define FW_ULPTX_WR_DATA_G(x) \
522 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
523 #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U)
524
525 struct fw_tp_wr {
526 __be32 op_to_immdlen;
527 __be32 flowid_len16;
528 u64 cookie;
529 };
530
531 struct fw_eth_tx_pkt_wr {
532 __be32 op_immdlen;
533 __be32 equiq_to_len16;
534 __be64 r3;
535 };
536
537 struct fw_ofld_connection_wr {
538 __be32 op_compl;
539 __be32 len16_pkd;
540 __u64 cookie;
541 __be64 r2;
542 __be64 r3;
543 struct fw_ofld_connection_le {
544 __be32 version_cpl;
545 __be32 filter;
546 __be32 r1;
547 __be16 lport;
548 __be16 pport;
549 union fw_ofld_connection_leip {
550 struct fw_ofld_connection_le_ipv4 {
551 __be32 pip;
552 __be32 lip;
553 __be64 r0;
554 __be64 r1;
555 __be64 r2;
556 } ipv4;
557 struct fw_ofld_connection_le_ipv6 {
558 __be64 pip_hi;
559 __be64 pip_lo;
560 __be64 lip_hi;
561 __be64 lip_lo;
562 } ipv6;
563 } u;
564 } le;
565 struct fw_ofld_connection_tcb {
566 __be32 t_state_to_astid;
567 __be16 cplrxdataack_cplpassacceptrpl;
568 __be16 rcv_adv;
569 __be32 rcv_nxt;
570 __be32 tx_max;
571 __be64 opt0;
572 __be32 opt2;
573 __be32 r1;
574 __be64 r2;
575 __be64 r3;
576 } tcb;
577 };
578
579 #define FW_OFLD_CONNECTION_WR_VERSION_S 31
580 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
581 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
582 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
583 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
584 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
585 FW_OFLD_CONNECTION_WR_VERSION_M)
586 #define FW_OFLD_CONNECTION_WR_VERSION_F \
587 FW_OFLD_CONNECTION_WR_VERSION_V(1U)
588
589 #define FW_OFLD_CONNECTION_WR_CPL_S 30
590 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1
591 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
592 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
593 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
594 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
595
596 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28
597 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
598 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
599 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
600 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
601 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
602 FW_OFLD_CONNECTION_WR_T_STATE_M)
603
604 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
605 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
606 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
607 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
608 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
609 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
610 FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
611
612 #define FW_OFLD_CONNECTION_WR_ASTID_S 0
613 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
614 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
615 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
616 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
617 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
618
619 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
620 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
621 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
622 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
623 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
624 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
625 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
626 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
627 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
628
629 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
630 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
631 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
632 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
633 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
634 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
635 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
636 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
637 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
638
639 enum fw_flowc_mnem_tcpstate {
640 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */
641 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */
642 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */
643 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
644 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
645 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
646 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
647 * will resend FIN - equiv ESTAB
648 */
649 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and
650 * will resend FIN but have
651 * received FIN
652 */
653 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and
654 * will resend FIN but have
655 * received FIN
656 */
657 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
658 * waiting for FIN
659 */
660 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
661 };
662
663 enum fw_flowc_mnem {
664 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
665 FW_FLOWC_MNEM_CH,
666 FW_FLOWC_MNEM_PORT,
667 FW_FLOWC_MNEM_IQID,
668 FW_FLOWC_MNEM_SNDNXT,
669 FW_FLOWC_MNEM_RCVNXT,
670 FW_FLOWC_MNEM_SNDBUF,
671 FW_FLOWC_MNEM_MSS,
672 FW_FLOWC_MNEM_TXDATAPLEN_MAX,
673 FW_FLOWC_MNEM_TCPSTATE,
674 FW_FLOWC_MNEM_EOSTATE,
675 FW_FLOWC_MNEM_SCHEDCLASS,
676 FW_FLOWC_MNEM_DCBPRIO,
677 FW_FLOWC_MNEM_SND_SCALE,
678 FW_FLOWC_MNEM_RCV_SCALE,
679 FW_FLOWC_MNEM_ULD_MODE,
680 FW_FLOWC_MNEM_MAX,
681 };
682
683 struct fw_flowc_mnemval {
684 u8 mnemonic;
685 u8 r4[3];
686 __be32 val;
687 };
688
689 struct fw_flowc_wr {
690 __be32 op_to_nparams;
691 __be32 flowid_len16;
692 struct fw_flowc_mnemval mnemval[0];
693 };
694
695 #define FW_FLOWC_WR_NPARAMS_S 0
696 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
697
698 struct fw_ofld_tx_data_wr {
699 __be32 op_to_immdlen;
700 __be32 flowid_len16;
701 __be32 plen;
702 __be32 tunnel_to_proxy;
703 };
704
705 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30
706 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
707 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
708
709 #define FW_OFLD_TX_DATA_WR_SHOVE_S 29
710 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
711 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
712
713 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
714 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
715
716 #define FW_OFLD_TX_DATA_WR_SAVE_S 18
717 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
718
719 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17
720 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
721 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
722
723 #define FW_OFLD_TX_DATA_WR_URGENT_S 16
724 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
725
726 #define FW_OFLD_TX_DATA_WR_MORE_S 15
727 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
728
729 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
730 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
731
732 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
733 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
734 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
735
736 struct fw_cmd_wr {
737 __be32 op_dma;
738 __be32 len16_pkd;
739 __be64 cookie_daddr;
740 };
741
742 #define FW_CMD_WR_DMA_S 17
743 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
744
745 struct fw_eth_tx_pkt_vm_wr {
746 __be32 op_immdlen;
747 __be32 equiq_to_len16;
748 __be32 r3[2];
749 u8 ethmacdst[6];
750 u8 ethmacsrc[6];
751 __be16 ethtype;
752 __be16 vlantci;
753 };
754
755 #define FW_CMD_MAX_TIMEOUT 10000
756
757 /*
758 * If a host driver does a HELLO and discovers that there's already a MASTER
759 * selected, we may have to wait for that MASTER to finish issuing RESET,
760 * configuration and INITIALIZE commands. Also, there's a possibility that
761 * our own HELLO may get lost if it happens right as the MASTER is issuign a
762 * RESET command, so we need to be willing to make a few retries of our HELLO.
763 */
764 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
765 #define FW_CMD_HELLO_RETRIES 3
766
767
768 enum fw_cmd_opcodes {
769 FW_LDST_CMD = 0x01,
770 FW_RESET_CMD = 0x03,
771 FW_HELLO_CMD = 0x04,
772 FW_BYE_CMD = 0x05,
773 FW_INITIALIZE_CMD = 0x06,
774 FW_CAPS_CONFIG_CMD = 0x07,
775 FW_PARAMS_CMD = 0x08,
776 FW_PFVF_CMD = 0x09,
777 FW_IQ_CMD = 0x10,
778 FW_EQ_MNGT_CMD = 0x11,
779 FW_EQ_ETH_CMD = 0x12,
780 FW_EQ_CTRL_CMD = 0x13,
781 FW_EQ_OFLD_CMD = 0x21,
782 FW_VI_CMD = 0x14,
783 FW_VI_MAC_CMD = 0x15,
784 FW_VI_RXMODE_CMD = 0x16,
785 FW_VI_ENABLE_CMD = 0x17,
786 FW_ACL_MAC_CMD = 0x18,
787 FW_ACL_VLAN_CMD = 0x19,
788 FW_VI_STATS_CMD = 0x1a,
789 FW_PORT_CMD = 0x1b,
790 FW_PORT_STATS_CMD = 0x1c,
791 FW_PORT_LB_STATS_CMD = 0x1d,
792 FW_PORT_TRACE_CMD = 0x1e,
793 FW_PORT_TRACE_MMAP_CMD = 0x1f,
794 FW_RSS_IND_TBL_CMD = 0x20,
795 FW_RSS_GLB_CONFIG_CMD = 0x22,
796 FW_RSS_VI_CONFIG_CMD = 0x23,
797 FW_SCHED_CMD = 0x24,
798 FW_DEVLOG_CMD = 0x25,
799 FW_CLIP_CMD = 0x28,
800 FW_PTP_CMD = 0x3e,
801 FW_HMA_CMD = 0x3f,
802 FW_LASTC2E_CMD = 0x40,
803 FW_ERROR_CMD = 0x80,
804 FW_DEBUG_CMD = 0x81,
805 };
806
807 enum fw_cmd_cap {
808 FW_CMD_CAP_PF = 0x01,
809 FW_CMD_CAP_DMAQ = 0x02,
810 FW_CMD_CAP_PORT = 0x04,
811 FW_CMD_CAP_PORTPROMISC = 0x08,
812 FW_CMD_CAP_PORTSTATS = 0x10,
813 FW_CMD_CAP_VF = 0x80,
814 };
815
816 /*
817 * Generic command header flit0
818 */
819 struct fw_cmd_hdr {
820 __be32 hi;
821 __be32 lo;
822 };
823
824 #define FW_CMD_OP_S 24
825 #define FW_CMD_OP_M 0xff
826 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
827 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
828
829 #define FW_CMD_REQUEST_S 23
830 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
831 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
832
833 #define FW_CMD_READ_S 22
834 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
835 #define FW_CMD_READ_F FW_CMD_READ_V(1U)
836
837 #define FW_CMD_WRITE_S 21
838 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
839 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
840
841 #define FW_CMD_EXEC_S 20
842 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
843 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
844
845 #define FW_CMD_RAMASK_S 20
846 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
847
848 #define FW_CMD_RETVAL_S 8
849 #define FW_CMD_RETVAL_M 0xff
850 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
851 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
852
853 #define FW_CMD_LEN16_S 0
854 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
855
856 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
857
858 enum fw_ldst_addrspc {
859 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
860 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
861 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
862 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
863 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
864 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
865 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
866 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
867 FW_LDST_ADDRSPC_MDIO = 0x0018,
868 FW_LDST_ADDRSPC_MPS = 0x0020,
869 FW_LDST_ADDRSPC_FUNC = 0x0028,
870 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
871 FW_LDST_ADDRSPC_I2C = 0x0038,
872 };
873
874 enum fw_ldst_mps_fid {
875 FW_LDST_MPS_ATRB,
876 FW_LDST_MPS_RPLC
877 };
878
879 enum fw_ldst_func_access_ctl {
880 FW_LDST_FUNC_ACC_CTL_VIID,
881 FW_LDST_FUNC_ACC_CTL_FID
882 };
883
884 enum fw_ldst_func_mod_index {
885 FW_LDST_FUNC_MPS
886 };
887
888 struct fw_ldst_cmd {
889 __be32 op_to_addrspace;
890 __be32 cycles_to_len16;
891 union fw_ldst {
892 struct fw_ldst_addrval {
893 __be32 addr;
894 __be32 val;
895 } addrval;
896 struct fw_ldst_idctxt {
897 __be32 physid;
898 __be32 msg_ctxtflush;
899 __be32 ctxt_data7;
900 __be32 ctxt_data6;
901 __be32 ctxt_data5;
902 __be32 ctxt_data4;
903 __be32 ctxt_data3;
904 __be32 ctxt_data2;
905 __be32 ctxt_data1;
906 __be32 ctxt_data0;
907 } idctxt;
908 struct fw_ldst_mdio {
909 __be16 paddr_mmd;
910 __be16 raddr;
911 __be16 vctl;
912 __be16 rval;
913 } mdio;
914 struct fw_ldst_cim_rq {
915 u8 req_first64[8];
916 u8 req_second64[8];
917 u8 resp_first64[8];
918 u8 resp_second64[8];
919 __be32 r3[2];
920 } cim_rq;
921 union fw_ldst_mps {
922 struct fw_ldst_mps_rplc {
923 __be16 fid_idx;
924 __be16 rplcpf_pkd;
925 __be32 rplc255_224;
926 __be32 rplc223_192;
927 __be32 rplc191_160;
928 __be32 rplc159_128;
929 __be32 rplc127_96;
930 __be32 rplc95_64;
931 __be32 rplc63_32;
932 __be32 rplc31_0;
933 } rplc;
934 struct fw_ldst_mps_atrb {
935 __be16 fid_mpsid;
936 __be16 r2[3];
937 __be32 r3[2];
938 __be32 r4;
939 __be32 atrb;
940 __be16 vlan[16];
941 } atrb;
942 } mps;
943 struct fw_ldst_func {
944 u8 access_ctl;
945 u8 mod_index;
946 __be16 ctl_id;
947 __be32 offset;
948 __be64 data0;
949 __be64 data1;
950 } func;
951 struct fw_ldst_pcie {
952 u8 ctrl_to_fn;
953 u8 bnum;
954 u8 r;
955 u8 ext_r;
956 u8 select_naccess;
957 u8 pcie_fn;
958 __be16 nset_pkd;
959 __be32 data[12];
960 } pcie;
961 struct fw_ldst_i2c_deprecated {
962 u8 pid_pkd;
963 u8 base;
964 u8 boffset;
965 u8 data;
966 __be32 r9;
967 } i2c_deprecated;
968 struct fw_ldst_i2c {
969 u8 pid;
970 u8 did;
971 u8 boffset;
972 u8 blen;
973 __be32 r9;
974 __u8 data[48];
975 } i2c;
976 struct fw_ldst_le {
977 __be32 index;
978 __be32 r9;
979 u8 val[33];
980 u8 r11[7];
981 } le;
982 } u;
983 };
984
985 #define FW_LDST_CMD_ADDRSPACE_S 0
986 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)
987
988 #define FW_LDST_CMD_MSG_S 31
989 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)
990
991 #define FW_LDST_CMD_CTXTFLUSH_S 30
992 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S)
993 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U)
994
995 #define FW_LDST_CMD_PADDR_S 8
996 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)
997
998 #define FW_LDST_CMD_MMD_S 0
999 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)
1000
1001 #define FW_LDST_CMD_FID_S 15
1002 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)
1003
1004 #define FW_LDST_CMD_IDX_S 0
1005 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)
1006
1007 #define FW_LDST_CMD_RPLCPF_S 0
1008 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
1009
1010 #define FW_LDST_CMD_LC_S 4
1011 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)
1012 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U)
1013
1014 #define FW_LDST_CMD_FN_S 0
1015 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)
1016
1017 #define FW_LDST_CMD_NACCESS_S 0
1018 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)
1019
1020 struct fw_reset_cmd {
1021 __be32 op_to_write;
1022 __be32 retval_len16;
1023 __be32 val;
1024 __be32 halt_pkd;
1025 };
1026
1027 #define FW_RESET_CMD_HALT_S 31
1028 #define FW_RESET_CMD_HALT_M 0x1
1029 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)
1030 #define FW_RESET_CMD_HALT_G(x) \
1031 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1032 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U)
1033
1034 enum fw_hellow_cmd {
1035 fw_hello_cmd_stage_os = 0x0
1036 };
1037
1038 struct fw_hello_cmd {
1039 __be32 op_to_write;
1040 __be32 retval_len16;
1041 __be32 err_to_clearinit;
1042 __be32 fwrev;
1043 };
1044
1045 #define FW_HELLO_CMD_ERR_S 31
1046 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)
1047 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U)
1048
1049 #define FW_HELLO_CMD_INIT_S 30
1050 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)
1051 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U)
1052
1053 #define FW_HELLO_CMD_MASTERDIS_S 29
1054 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)
1055
1056 #define FW_HELLO_CMD_MASTERFORCE_S 28
1057 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)
1058
1059 #define FW_HELLO_CMD_MBMASTER_S 24
1060 #define FW_HELLO_CMD_MBMASTER_M 0xfU
1061 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)
1062 #define FW_HELLO_CMD_MBMASTER_G(x) \
1063 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1064
1065 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23
1066 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1067
1068 #define FW_HELLO_CMD_MBASYNCNOT_S 20
1069 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1070
1071 #define FW_HELLO_CMD_STAGE_S 17
1072 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)
1073
1074 #define FW_HELLO_CMD_CLEARINIT_S 16
1075 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)
1076 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U)
1077
1078 struct fw_bye_cmd {
1079 __be32 op_to_write;
1080 __be32 retval_len16;
1081 __be64 r3;
1082 };
1083
1084 struct fw_initialize_cmd {
1085 __be32 op_to_write;
1086 __be32 retval_len16;
1087 __be64 r3;
1088 };
1089
1090 enum fw_caps_config_hm {
1091 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
1092 FW_CAPS_CONFIG_HM_PL = 0x00000002,
1093 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
1094 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
1095 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
1096 FW_CAPS_CONFIG_HM_TP = 0x00000020,
1097 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
1098 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
1099 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
1100 FW_CAPS_CONFIG_HM_MC = 0x00000200,
1101 FW_CAPS_CONFIG_HM_LE = 0x00000400,
1102 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
1103 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
1104 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
1105 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
1106 FW_CAPS_CONFIG_HM_MI = 0x00008000,
1107 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
1108 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
1109 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
1110 FW_CAPS_CONFIG_HM_MA = 0x00080000,
1111 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
1112 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
1113 FW_CAPS_CONFIG_HM_UART = 0x00400000,
1114 FW_CAPS_CONFIG_HM_SF = 0x00800000,
1115 };
1116
1117 enum fw_caps_config_nbm {
1118 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
1119 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
1120 };
1121
1122 enum fw_caps_config_link {
1123 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
1124 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
1125 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
1126 };
1127
1128 enum fw_caps_config_switch {
1129 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
1130 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
1131 };
1132
1133 enum fw_caps_config_nic {
1134 FW_CAPS_CONFIG_NIC = 0x00000001,
1135 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
1136 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
1137 };
1138
1139 enum fw_caps_config_ofld {
1140 FW_CAPS_CONFIG_OFLD = 0x00000001,
1141 };
1142
1143 enum fw_caps_config_rdma {
1144 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
1145 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
1146 };
1147
1148 enum fw_caps_config_iscsi {
1149 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1150 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1151 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1152 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1153 };
1154
1155 enum fw_caps_config_crypto {
1156 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
1157 FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
1158 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1159 };
1160
1161 enum fw_caps_config_fcoe {
1162 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
1163 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
1164 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
1165 };
1166
1167 enum fw_memtype_cf {
1168 FW_MEMTYPE_CF_EDC0 = 0x0,
1169 FW_MEMTYPE_CF_EDC1 = 0x1,
1170 FW_MEMTYPE_CF_EXTMEM = 0x2,
1171 FW_MEMTYPE_CF_FLASH = 0x4,
1172 FW_MEMTYPE_CF_INTERNAL = 0x5,
1173 FW_MEMTYPE_CF_EXTMEM1 = 0x6,
1174 FW_MEMTYPE_CF_HMA = 0x7,
1175 };
1176
1177 struct fw_caps_config_cmd {
1178 __be32 op_to_write;
1179 __be32 cfvalid_to_len16;
1180 __be32 r2;
1181 __be32 hwmbitmap;
1182 __be16 nbmcaps;
1183 __be16 linkcaps;
1184 __be16 switchcaps;
1185 __be16 r3;
1186 __be16 niccaps;
1187 __be16 ofldcaps;
1188 __be16 rdmacaps;
1189 __be16 cryptocaps;
1190 __be16 iscsicaps;
1191 __be16 fcoecaps;
1192 __be32 cfcsum;
1193 __be32 finiver;
1194 __be32 finicsum;
1195 };
1196
1197 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27
1198 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1199 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1200
1201 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24
1202 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \
1203 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1204
1205 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16
1206 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \
1207 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1208
1209 /*
1210 * params command mnemonics
1211 */
1212 enum fw_params_mnem {
1213 FW_PARAMS_MNEM_DEV = 1, /* device params */
1214 FW_PARAMS_MNEM_PFVF = 2, /* function params */
1215 FW_PARAMS_MNEM_REG = 3, /* limited register access */
1216 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
1217 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
1218 FW_PARAMS_MNEM_LAST
1219 };
1220
1221 /*
1222 * device parameters
1223 */
1224 enum fw_params_param_dev {
1225 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
1226 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
1227 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
1228 * allocated by the device's
1229 * Lookup Engine
1230 */
1231 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1232 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
1233 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1234 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1235 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
1236 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1237 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1238 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1239 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1240 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1241 FW_PARAMS_PARAM_DEV_CF = 0x0D,
1242 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1243 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1244 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1245 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1246 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1247 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1248 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1249 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1250 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
1251 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
1252 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
1253 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
1254 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1255 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
1256 };
1257
1258 /*
1259 * physical and virtual function parameters
1260 */
1261 enum fw_params_param_pfvf {
1262 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
1263 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1264 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1265 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1266 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1267 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1268 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1269 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1270 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1271 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1272 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1273 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1274 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1275 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1276 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1277 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1278 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
1279 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1280 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
1281 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1282 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1283 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1284 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
1285 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
1286 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
1287 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
1288 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
1289 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1290 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
1291 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
1292 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
1293 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
1294 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
1295 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1296 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1297 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
1298 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
1299 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1300 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1301 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1302 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1303 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1304 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1305 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1306 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
1307 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
1308 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1309 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1310 };
1311
1312 /*
1313 * dma queue parameters
1314 */
1315 enum fw_params_param_dmaq {
1316 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1317 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1318 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1319 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1320 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1321 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1322 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1323 };
1324
1325 enum fw_params_param_dev_phyfw {
1326 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1327 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1328 };
1329
1330 enum fw_params_param_dev_diag {
1331 FW_PARAM_DEV_DIAG_TMP = 0x00,
1332 FW_PARAM_DEV_DIAG_VDD = 0x01,
1333 };
1334
1335 enum fw_params_param_dev_fwcache {
1336 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
1337 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
1338 };
1339
1340 #define FW_PARAMS_MNEM_S 24
1341 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)
1342
1343 #define FW_PARAMS_PARAM_X_S 16
1344 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)
1345
1346 #define FW_PARAMS_PARAM_Y_S 8
1347 #define FW_PARAMS_PARAM_Y_M 0xffU
1348 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)
1349 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\
1350 FW_PARAMS_PARAM_Y_M)
1351
1352 #define FW_PARAMS_PARAM_Z_S 0
1353 #define FW_PARAMS_PARAM_Z_M 0xffu
1354 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)
1355 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\
1356 FW_PARAMS_PARAM_Z_M)
1357
1358 #define FW_PARAMS_PARAM_XYZ_S 0
1359 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)
1360
1361 #define FW_PARAMS_PARAM_YZ_S 0
1362 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)
1363
1364 struct fw_params_cmd {
1365 __be32 op_to_vfn;
1366 __be32 retval_len16;
1367 struct fw_params_param {
1368 __be32 mnem;
1369 __be32 val;
1370 } param[7];
1371 };
1372
1373 #define FW_PARAMS_CMD_PFN_S 8
1374 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)
1375
1376 #define FW_PARAMS_CMD_VFN_S 0
1377 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)
1378
1379 struct fw_pfvf_cmd {
1380 __be32 op_to_vfn;
1381 __be32 retval_len16;
1382 __be32 niqflint_niq;
1383 __be32 type_to_neq;
1384 __be32 tc_to_nexactf;
1385 __be32 r_caps_to_nethctrl;
1386 __be16 nricq;
1387 __be16 nriqp;
1388 __be32 r4;
1389 };
1390
1391 #define FW_PFVF_CMD_PFN_S 8
1392 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)
1393
1394 #define FW_PFVF_CMD_VFN_S 0
1395 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)
1396
1397 #define FW_PFVF_CMD_NIQFLINT_S 20
1398 #define FW_PFVF_CMD_NIQFLINT_M 0xfff
1399 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)
1400 #define FW_PFVF_CMD_NIQFLINT_G(x) \
1401 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1402
1403 #define FW_PFVF_CMD_NIQ_S 0
1404 #define FW_PFVF_CMD_NIQ_M 0xfffff
1405 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)
1406 #define FW_PFVF_CMD_NIQ_G(x) \
1407 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1408
1409 #define FW_PFVF_CMD_TYPE_S 31
1410 #define FW_PFVF_CMD_TYPE_M 0x1
1411 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)
1412 #define FW_PFVF_CMD_TYPE_G(x) \
1413 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1414 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U)
1415
1416 #define FW_PFVF_CMD_CMASK_S 24
1417 #define FW_PFVF_CMD_CMASK_M 0xf
1418 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)
1419 #define FW_PFVF_CMD_CMASK_G(x) \
1420 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1421
1422 #define FW_PFVF_CMD_PMASK_S 20
1423 #define FW_PFVF_CMD_PMASK_M 0xf
1424 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)
1425 #define FW_PFVF_CMD_PMASK_G(x) \
1426 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1427
1428 #define FW_PFVF_CMD_NEQ_S 0
1429 #define FW_PFVF_CMD_NEQ_M 0xfffff
1430 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)
1431 #define FW_PFVF_CMD_NEQ_G(x) \
1432 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1433
1434 #define FW_PFVF_CMD_TC_S 24
1435 #define FW_PFVF_CMD_TC_M 0xff
1436 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)
1437 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1438
1439 #define FW_PFVF_CMD_NVI_S 16
1440 #define FW_PFVF_CMD_NVI_M 0xff
1441 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)
1442 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1443
1444 #define FW_PFVF_CMD_NEXACTF_S 0
1445 #define FW_PFVF_CMD_NEXACTF_M 0xffff
1446 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)
1447 #define FW_PFVF_CMD_NEXACTF_G(x) \
1448 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1449
1450 #define FW_PFVF_CMD_R_CAPS_S 24
1451 #define FW_PFVF_CMD_R_CAPS_M 0xff
1452 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1453 #define FW_PFVF_CMD_R_CAPS_G(x) \
1454 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1455
1456 #define FW_PFVF_CMD_WX_CAPS_S 16
1457 #define FW_PFVF_CMD_WX_CAPS_M 0xff
1458 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)
1459 #define FW_PFVF_CMD_WX_CAPS_G(x) \
1460 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1461
1462 #define FW_PFVF_CMD_NETHCTRL_S 0
1463 #define FW_PFVF_CMD_NETHCTRL_M 0xffff
1464 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)
1465 #define FW_PFVF_CMD_NETHCTRL_G(x) \
1466 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1467
1468 enum fw_iq_type {
1469 FW_IQ_TYPE_FL_INT_CAP,
1470 FW_IQ_TYPE_NO_FL_INT_CAP
1471 };
1472
1473 struct fw_iq_cmd {
1474 __be32 op_to_vfn;
1475 __be32 alloc_to_len16;
1476 __be16 physiqid;
1477 __be16 iqid;
1478 __be16 fl0id;
1479 __be16 fl1id;
1480 __be32 type_to_iqandstindex;
1481 __be16 iqdroprss_to_iqesize;
1482 __be16 iqsize;
1483 __be64 iqaddr;
1484 __be32 iqns_to_fl0congen;
1485 __be16 fl0dcaen_to_fl0cidxfthresh;
1486 __be16 fl0size;
1487 __be64 fl0addr;
1488 __be32 fl1cngchmap_to_fl1congen;
1489 __be16 fl1dcaen_to_fl1cidxfthresh;
1490 __be16 fl1size;
1491 __be64 fl1addr;
1492 };
1493
1494 #define FW_IQ_CMD_PFN_S 8
1495 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)
1496
1497 #define FW_IQ_CMD_VFN_S 0
1498 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)
1499
1500 #define FW_IQ_CMD_ALLOC_S 31
1501 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)
1502 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U)
1503
1504 #define FW_IQ_CMD_FREE_S 30
1505 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)
1506 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U)
1507
1508 #define FW_IQ_CMD_MODIFY_S 29
1509 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)
1510 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U)
1511
1512 #define FW_IQ_CMD_IQSTART_S 28
1513 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)
1514 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U)
1515
1516 #define FW_IQ_CMD_IQSTOP_S 27
1517 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)
1518 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U)
1519
1520 #define FW_IQ_CMD_TYPE_S 29
1521 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)
1522
1523 #define FW_IQ_CMD_IQASYNCH_S 28
1524 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1525
1526 #define FW_IQ_CMD_VIID_S 16
1527 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)
1528
1529 #define FW_IQ_CMD_IQANDST_S 15
1530 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)
1531
1532 #define FW_IQ_CMD_IQANUS_S 14
1533 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)
1534
1535 #define FW_IQ_CMD_IQANUD_S 12
1536 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)
1537
1538 #define FW_IQ_CMD_IQANDSTINDEX_S 0
1539 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1540
1541 #define FW_IQ_CMD_IQDROPRSS_S 15
1542 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)
1543 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U)
1544
1545 #define FW_IQ_CMD_IQGTSMODE_S 14
1546 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)
1547 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U)
1548
1549 #define FW_IQ_CMD_IQPCIECH_S 12
1550 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1551
1552 #define FW_IQ_CMD_IQDCAEN_S 11
1553 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)
1554
1555 #define FW_IQ_CMD_IQDCACPU_S 6
1556 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1557
1558 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4
1559 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1560
1561 #define FW_IQ_CMD_IQO_S 3
1562 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)
1563 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U)
1564
1565 #define FW_IQ_CMD_IQCPRIO_S 2
1566 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)
1567
1568 #define FW_IQ_CMD_IQESIZE_S 0
1569 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)
1570
1571 #define FW_IQ_CMD_IQNS_S 31
1572 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)
1573
1574 #define FW_IQ_CMD_IQRO_S 30
1575 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)
1576
1577 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28
1578 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1579
1580 #define FW_IQ_CMD_IQFLINTCONGEN_S 27
1581 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1582 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1583
1584 #define FW_IQ_CMD_IQFLINTISCSIC_S 26
1585 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1586
1587 #define FW_IQ_CMD_FL0CNGCHMAP_S 20
1588 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1589
1590 #define FW_IQ_CMD_FL0CACHELOCK_S 15
1591 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1592
1593 #define FW_IQ_CMD_FL0DBP_S 14
1594 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)
1595
1596 #define FW_IQ_CMD_FL0DATANS_S 13
1597 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)
1598
1599 #define FW_IQ_CMD_FL0DATARO_S 12
1600 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)
1601 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U)
1602
1603 #define FW_IQ_CMD_FL0CONGCIF_S 11
1604 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1605 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U)
1606
1607 #define FW_IQ_CMD_FL0ONCHIP_S 10
1608 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1609
1610 #define FW_IQ_CMD_FL0STATUSPGNS_S 9
1611 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1612
1613 #define FW_IQ_CMD_FL0STATUSPGRO_S 8
1614 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1615
1616 #define FW_IQ_CMD_FL0FETCHNS_S 7
1617 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1618
1619 #define FW_IQ_CMD_FL0FETCHRO_S 6
1620 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1621 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U)
1622
1623 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4
1624 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1625
1626 #define FW_IQ_CMD_FL0CPRIO_S 3
1627 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1628
1629 #define FW_IQ_CMD_FL0PADEN_S 2
1630 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1631 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U)
1632
1633 #define FW_IQ_CMD_FL0PACKEN_S 1
1634 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)
1635 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U)
1636
1637 #define FW_IQ_CMD_FL0CONGEN_S 0
1638 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)
1639 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U)
1640
1641 #define FW_IQ_CMD_FL0DCAEN_S 15
1642 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1643
1644 #define FW_IQ_CMD_FL0DCACPU_S 10
1645 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)
1646
1647 #define FW_IQ_CMD_FL0FBMIN_S 7
1648 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1649
1650 #define FW_IQ_CMD_FL0FBMAX_S 4
1651 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1652
1653 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3
1654 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1655 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1656
1657 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0
1658 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1659
1660 #define FW_IQ_CMD_FL1CNGCHMAP_S 20
1661 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1662
1663 #define FW_IQ_CMD_FL1CACHELOCK_S 15
1664 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1665
1666 #define FW_IQ_CMD_FL1DBP_S 14
1667 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)
1668
1669 #define FW_IQ_CMD_FL1DATANS_S 13
1670 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)
1671
1672 #define FW_IQ_CMD_FL1DATARO_S 12
1673 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)
1674
1675 #define FW_IQ_CMD_FL1CONGCIF_S 11
1676 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1677
1678 #define FW_IQ_CMD_FL1ONCHIP_S 10
1679 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1680
1681 #define FW_IQ_CMD_FL1STATUSPGNS_S 9
1682 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1683
1684 #define FW_IQ_CMD_FL1STATUSPGRO_S 8
1685 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1686
1687 #define FW_IQ_CMD_FL1FETCHNS_S 7
1688 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1689
1690 #define FW_IQ_CMD_FL1FETCHRO_S 6
1691 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1692
1693 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4
1694 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1695
1696 #define FW_IQ_CMD_FL1CPRIO_S 3
1697 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1698
1699 #define FW_IQ_CMD_FL1PADEN_S 2
1700 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1701 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U)
1702
1703 #define FW_IQ_CMD_FL1PACKEN_S 1
1704 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)
1705 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U)
1706
1707 #define FW_IQ_CMD_FL1CONGEN_S 0
1708 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)
1709 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U)
1710
1711 #define FW_IQ_CMD_FL1DCAEN_S 15
1712 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1713
1714 #define FW_IQ_CMD_FL1DCACPU_S 10
1715 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)
1716
1717 #define FW_IQ_CMD_FL1FBMIN_S 7
1718 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1719
1720 #define FW_IQ_CMD_FL1FBMAX_S 4
1721 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1722
1723 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3
1724 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1725 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1726
1727 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0
1728 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1729
1730 struct fw_eq_eth_cmd {
1731 __be32 op_to_vfn;
1732 __be32 alloc_to_len16;
1733 __be32 eqid_pkd;
1734 __be32 physeqid_pkd;
1735 __be32 fetchszm_to_iqid;
1736 __be32 dcaen_to_eqsize;
1737 __be64 eqaddr;
1738 __be32 viid_pkd;
1739 __be32 r8_lo;
1740 __be64 r9;
1741 };
1742
1743 #define FW_EQ_ETH_CMD_PFN_S 8
1744 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)
1745
1746 #define FW_EQ_ETH_CMD_VFN_S 0
1747 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)
1748
1749 #define FW_EQ_ETH_CMD_ALLOC_S 31
1750 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1751 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U)
1752
1753 #define FW_EQ_ETH_CMD_FREE_S 30
1754 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1755 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U)
1756
1757 #define FW_EQ_ETH_CMD_MODIFY_S 29
1758 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1759 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U)
1760
1761 #define FW_EQ_ETH_CMD_EQSTART_S 28
1762 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1763 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1764
1765 #define FW_EQ_ETH_CMD_EQSTOP_S 27
1766 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1767 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
1768
1769 #define FW_EQ_ETH_CMD_EQID_S 0
1770 #define FW_EQ_ETH_CMD_EQID_M 0xfffff
1771 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1772 #define FW_EQ_ETH_CMD_EQID_G(x) \
1773 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1774
1775 #define FW_EQ_ETH_CMD_PHYSEQID_S 0
1776 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff
1777 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1778 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \
1779 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1780
1781 #define FW_EQ_ETH_CMD_FETCHSZM_S 26
1782 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1783 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1784
1785 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25
1786 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1787
1788 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24
1789 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1790
1791 #define FW_EQ_ETH_CMD_FETCHNS_S 23
1792 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1793
1794 #define FW_EQ_ETH_CMD_FETCHRO_S 22
1795 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1796 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U)
1797
1798 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20
1799 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1800
1801 #define FW_EQ_ETH_CMD_CPRIO_S 19
1802 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1803
1804 #define FW_EQ_ETH_CMD_ONCHIP_S 18
1805 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1806
1807 #define FW_EQ_ETH_CMD_PCIECHN_S 16
1808 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1809
1810 #define FW_EQ_ETH_CMD_IQID_S 0
1811 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1812
1813 #define FW_EQ_ETH_CMD_DCAEN_S 31
1814 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1815
1816 #define FW_EQ_ETH_CMD_DCACPU_S 26
1817 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1818
1819 #define FW_EQ_ETH_CMD_FBMIN_S 23
1820 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1821
1822 #define FW_EQ_ETH_CMD_FBMAX_S 20
1823 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1824
1825 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19
1826 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1827
1828 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16
1829 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1830
1831 #define FW_EQ_ETH_CMD_EQSIZE_S 0
1832 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1833
1834 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30
1835 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1836 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1837
1838 #define FW_EQ_ETH_CMD_VIID_S 16
1839 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1840
1841 struct fw_eq_ctrl_cmd {
1842 __be32 op_to_vfn;
1843 __be32 alloc_to_len16;
1844 __be32 cmpliqid_eqid;
1845 __be32 physeqid_pkd;
1846 __be32 fetchszm_to_iqid;
1847 __be32 dcaen_to_eqsize;
1848 __be64 eqaddr;
1849 };
1850
1851 #define FW_EQ_CTRL_CMD_PFN_S 8
1852 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1853
1854 #define FW_EQ_CTRL_CMD_VFN_S 0
1855 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1856
1857 #define FW_EQ_CTRL_CMD_ALLOC_S 31
1858 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1859 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U)
1860
1861 #define FW_EQ_CTRL_CMD_FREE_S 30
1862 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)
1863 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U)
1864
1865 #define FW_EQ_CTRL_CMD_MODIFY_S 29
1866 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1867 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U)
1868
1869 #define FW_EQ_CTRL_CMD_EQSTART_S 28
1870 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1871 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U)
1872
1873 #define FW_EQ_CTRL_CMD_EQSTOP_S 27
1874 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1875 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1876
1877 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20
1878 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1879
1880 #define FW_EQ_CTRL_CMD_EQID_S 0
1881 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff
1882 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
1883 #define FW_EQ_CTRL_CMD_EQID_G(x) \
1884 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1885
1886 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0
1887 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff
1888 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \
1889 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1890
1891 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26
1892 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1893 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1894
1895 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25
1896 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1897 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1898
1899 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24
1900 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1901 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1902
1903 #define FW_EQ_CTRL_CMD_FETCHNS_S 23
1904 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1905 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1906
1907 #define FW_EQ_CTRL_CMD_FETCHRO_S 22
1908 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1909 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1910
1911 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20
1912 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1913
1914 #define FW_EQ_CTRL_CMD_CPRIO_S 19
1915 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1916
1917 #define FW_EQ_CTRL_CMD_ONCHIP_S 18
1918 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1919
1920 #define FW_EQ_CTRL_CMD_PCIECHN_S 16
1921 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1922
1923 #define FW_EQ_CTRL_CMD_IQID_S 0
1924 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S)
1925
1926 #define FW_EQ_CTRL_CMD_DCAEN_S 31
1927 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1928
1929 #define FW_EQ_CTRL_CMD_DCACPU_S 26
1930 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1931
1932 #define FW_EQ_CTRL_CMD_FBMIN_S 23
1933 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1934
1935 #define FW_EQ_CTRL_CMD_FBMAX_S 20
1936 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1937
1938 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19
1939 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \
1940 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1941
1942 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16
1943 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1944
1945 #define FW_EQ_CTRL_CMD_EQSIZE_S 0
1946 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1947
1948 struct fw_eq_ofld_cmd {
1949 __be32 op_to_vfn;
1950 __be32 alloc_to_len16;
1951 __be32 eqid_pkd;
1952 __be32 physeqid_pkd;
1953 __be32 fetchszm_to_iqid;
1954 __be32 dcaen_to_eqsize;
1955 __be64 eqaddr;
1956 };
1957
1958 #define FW_EQ_OFLD_CMD_PFN_S 8
1959 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1960
1961 #define FW_EQ_OFLD_CMD_VFN_S 0
1962 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1963
1964 #define FW_EQ_OFLD_CMD_ALLOC_S 31
1965 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1966 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U)
1967
1968 #define FW_EQ_OFLD_CMD_FREE_S 30
1969 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S)
1970 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U)
1971
1972 #define FW_EQ_OFLD_CMD_MODIFY_S 29
1973 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1974 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U)
1975
1976 #define FW_EQ_OFLD_CMD_EQSTART_S 28
1977 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1978 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U)
1979
1980 #define FW_EQ_OFLD_CMD_EQSTOP_S 27
1981 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1982 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1983
1984 #define FW_EQ_OFLD_CMD_EQID_S 0
1985 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff
1986 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S)
1987 #define FW_EQ_OFLD_CMD_EQID_G(x) \
1988 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1989
1990 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0
1991 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff
1992 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \
1993 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1994
1995 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26
1996 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1997
1998 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25
1999 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2000
2001 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24
2002 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2003
2004 #define FW_EQ_OFLD_CMD_FETCHNS_S 23
2005 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2006
2007 #define FW_EQ_OFLD_CMD_FETCHRO_S 22
2008 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2009 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2010
2011 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20
2012 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2013
2014 #define FW_EQ_OFLD_CMD_CPRIO_S 19
2015 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2016
2017 #define FW_EQ_OFLD_CMD_ONCHIP_S 18
2018 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2019
2020 #define FW_EQ_OFLD_CMD_PCIECHN_S 16
2021 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2022
2023 #define FW_EQ_OFLD_CMD_IQID_S 0
2024 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S)
2025
2026 #define FW_EQ_OFLD_CMD_DCAEN_S 31
2027 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2028
2029 #define FW_EQ_OFLD_CMD_DCACPU_S 26
2030 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2031
2032 #define FW_EQ_OFLD_CMD_FBMIN_S 23
2033 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2034
2035 #define FW_EQ_OFLD_CMD_FBMAX_S 20
2036 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2037
2038 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19
2039 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \
2040 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2041
2042 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16
2043 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2044
2045 #define FW_EQ_OFLD_CMD_EQSIZE_S 0
2046 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2047
2048 /*
2049 * Macros for VIID parsing:
2050 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
2051 */
2052
2053 #define FW_VIID_PFN_S 8
2054 #define FW_VIID_PFN_M 0x7
2055 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2056
2057 #define FW_VIID_VIVLD_S 7
2058 #define FW_VIID_VIVLD_M 0x1
2059 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2060
2061 #define FW_VIID_VIN_S 0
2062 #define FW_VIID_VIN_M 0x7F
2063 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2064
2065 struct fw_vi_cmd {
2066 __be32 op_to_vfn;
2067 __be32 alloc_to_len16;
2068 __be16 type_viid;
2069 u8 mac[6];
2070 u8 portid_pkd;
2071 u8 nmac;
2072 u8 nmac0[6];
2073 __be16 rsssize_pkd;
2074 u8 nmac1[6];
2075 __be16 idsiiq_pkd;
2076 u8 nmac2[6];
2077 __be16 idseiq_pkd;
2078 u8 nmac3[6];
2079 __be64 r9;
2080 __be64 r10;
2081 };
2082
2083 #define FW_VI_CMD_PFN_S 8
2084 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S)
2085
2086 #define FW_VI_CMD_VFN_S 0
2087 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S)
2088
2089 #define FW_VI_CMD_ALLOC_S 31
2090 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S)
2091 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U)
2092
2093 #define FW_VI_CMD_FREE_S 30
2094 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S)
2095 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U)
2096
2097 #define FW_VI_CMD_VIID_S 0
2098 #define FW_VI_CMD_VIID_M 0xfff
2099 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S)
2100 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2101
2102 #define FW_VI_CMD_PORTID_S 4
2103 #define FW_VI_CMD_PORTID_M 0xf
2104 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S)
2105 #define FW_VI_CMD_PORTID_G(x) \
2106 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2107
2108 #define FW_VI_CMD_RSSSIZE_S 0
2109 #define FW_VI_CMD_RSSSIZE_M 0x7ff
2110 #define FW_VI_CMD_RSSSIZE_G(x) \
2111 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2112
2113 /* Special VI_MAC command index ids */
2114 #define FW_VI_MAC_ADD_MAC 0x3FF
2115 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
2116 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
2117 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
2118 #define FW_CLS_TCAM_NUM_ENTRIES 336
2119
2120 enum fw_vi_mac_smac {
2121 FW_VI_MAC_MPS_TCAM_ENTRY,
2122 FW_VI_MAC_MPS_TCAM_ONLY,
2123 FW_VI_MAC_SMT_ONLY,
2124 FW_VI_MAC_SMT_AND_MPSTCAM
2125 };
2126
2127 enum fw_vi_mac_result {
2128 FW_VI_MAC_R_SUCCESS,
2129 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2130 FW_VI_MAC_R_SMAC_FAIL,
2131 FW_VI_MAC_R_F_ACL_CHECK
2132 };
2133
2134 enum fw_vi_mac_entry_types {
2135 FW_VI_MAC_TYPE_EXACTMAC,
2136 FW_VI_MAC_TYPE_HASHVEC,
2137 FW_VI_MAC_TYPE_RAW,
2138 FW_VI_MAC_TYPE_EXACTMAC_VNI,
2139 };
2140
2141 struct fw_vi_mac_cmd {
2142 __be32 op_to_viid;
2143 __be32 freemacs_to_len16;
2144 union fw_vi_mac {
2145 struct fw_vi_mac_exact {
2146 __be16 valid_to_idx;
2147 u8 macaddr[6];
2148 } exact[7];
2149 struct fw_vi_mac_hash {
2150 __be64 hashvec;
2151 } hash;
2152 struct fw_vi_mac_raw {
2153 __be32 raw_idx_pkd;
2154 __be32 data0_pkd;
2155 __be32 data1[2];
2156 __be64 data0m_pkd;
2157 __be32 data1m[2];
2158 } raw;
2159 } u;
2160 };
2161
2162 #define FW_VI_MAC_CMD_VIID_S 0
2163 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2164
2165 #define FW_VI_MAC_CMD_FREEMACS_S 31
2166 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2167
2168 #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23
2169 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7
2170 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2171 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \
2172 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2173
2174 #define FW_VI_MAC_CMD_HASHVECEN_S 23
2175 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2176 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U)
2177
2178 #define FW_VI_MAC_CMD_HASHUNIEN_S 22
2179 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2180
2181 #define FW_VI_MAC_CMD_VALID_S 15
2182 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S)
2183 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U)
2184
2185 #define FW_VI_MAC_CMD_PRIO_S 12
2186 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2187
2188 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10
2189 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3
2190 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2191 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \
2192 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2193
2194 #define FW_VI_MAC_CMD_IDX_S 0
2195 #define FW_VI_MAC_CMD_IDX_M 0x3ff
2196 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S)
2197 #define FW_VI_MAC_CMD_IDX_G(x) \
2198 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2199
2200 #define FW_VI_MAC_CMD_RAW_IDX_S 16
2201 #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff
2202 #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2203 #define FW_VI_MAC_CMD_RAW_IDX_G(x) \
2204 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2205
2206 #define FW_RXMODE_MTU_NO_CHG 65535
2207
2208 struct fw_vi_rxmode_cmd {
2209 __be32 op_to_viid;
2210 __be32 retval_len16;
2211 __be32 mtu_to_vlanexen;
2212 __be32 r4_lo;
2213 };
2214
2215 #define FW_VI_RXMODE_CMD_VIID_S 0
2216 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S)
2217
2218 #define FW_VI_RXMODE_CMD_MTU_S 16
2219 #define FW_VI_RXMODE_CMD_MTU_M 0xffff
2220 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S)
2221
2222 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14
2223 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3
2224 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2225
2226 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12
2227 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3
2228 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \
2229 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2230
2231 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10
2232 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3
2233 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \
2234 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2235
2236 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8
2237 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3
2238 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2239
2240 struct fw_vi_enable_cmd {
2241 __be32 op_to_viid;
2242 __be32 ien_to_len16;
2243 __be16 blinkdur;
2244 __be16 r3;
2245 __be32 r4;
2246 };
2247
2248 #define FW_VI_ENABLE_CMD_VIID_S 0
2249 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S)
2250
2251 #define FW_VI_ENABLE_CMD_IEN_S 31
2252 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S)
2253
2254 #define FW_VI_ENABLE_CMD_EEN_S 30
2255 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S)
2256
2257 #define FW_VI_ENABLE_CMD_LED_S 29
2258 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S)
2259 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U)
2260
2261 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28
2262 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2263
2264 /* VI VF stats offset definitions */
2265 #define VI_VF_NUM_STATS 16
2266 enum fw_vi_stats_vf_index {
2267 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2268 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2269 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2270 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2271 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2272 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2273 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2274 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2275 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2276 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2277 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2278 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2279 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2280 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2281 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2282 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2283 };
2284
2285 /* VI PF stats offset definitions */
2286 #define VI_PF_NUM_STATS 17
2287 enum fw_vi_stats_pf_index {
2288 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2289 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2290 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2291 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2292 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2293 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2294 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2295 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2296 FW_VI_PF_STAT_RX_BYTES_IX,
2297 FW_VI_PF_STAT_RX_FRAMES_IX,
2298 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2299 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2300 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2301 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2302 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2303 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2304 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2305 };
2306
2307 struct fw_vi_stats_cmd {
2308 __be32 op_to_viid;
2309 __be32 retval_len16;
2310 union fw_vi_stats {
2311 struct fw_vi_stats_ctl {
2312 __be16 nstats_ix;
2313 __be16 r6;
2314 __be32 r7;
2315 __be64 stat0;
2316 __be64 stat1;
2317 __be64 stat2;
2318 __be64 stat3;
2319 __be64 stat4;
2320 __be64 stat5;
2321 } ctl;
2322 struct fw_vi_stats_pf {
2323 __be64 tx_bcast_bytes;
2324 __be64 tx_bcast_frames;
2325 __be64 tx_mcast_bytes;
2326 __be64 tx_mcast_frames;
2327 __be64 tx_ucast_bytes;
2328 __be64 tx_ucast_frames;
2329 __be64 tx_offload_bytes;
2330 __be64 tx_offload_frames;
2331 __be64 rx_pf_bytes;
2332 __be64 rx_pf_frames;
2333 __be64 rx_bcast_bytes;
2334 __be64 rx_bcast_frames;
2335 __be64 rx_mcast_bytes;
2336 __be64 rx_mcast_frames;
2337 __be64 rx_ucast_bytes;
2338 __be64 rx_ucast_frames;
2339 __be64 rx_err_frames;
2340 } pf;
2341 struct fw_vi_stats_vf {
2342 __be64 tx_bcast_bytes;
2343 __be64 tx_bcast_frames;
2344 __be64 tx_mcast_bytes;
2345 __be64 tx_mcast_frames;
2346 __be64 tx_ucast_bytes;
2347 __be64 tx_ucast_frames;
2348 __be64 tx_drop_frames;
2349 __be64 tx_offload_bytes;
2350 __be64 tx_offload_frames;
2351 __be64 rx_bcast_bytes;
2352 __be64 rx_bcast_frames;
2353 __be64 rx_mcast_bytes;
2354 __be64 rx_mcast_frames;
2355 __be64 rx_ucast_bytes;
2356 __be64 rx_ucast_frames;
2357 __be64 rx_err_frames;
2358 } vf;
2359 } u;
2360 };
2361
2362 #define FW_VI_STATS_CMD_VIID_S 0
2363 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S)
2364
2365 #define FW_VI_STATS_CMD_NSTATS_S 12
2366 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S)
2367
2368 #define FW_VI_STATS_CMD_IX_S 0
2369 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2370
2371 struct fw_acl_mac_cmd {
2372 __be32 op_to_vfn;
2373 __be32 en_to_len16;
2374 u8 nmac;
2375 u8 r3[7];
2376 __be16 r4;
2377 u8 macaddr0[6];
2378 __be16 r5;
2379 u8 macaddr1[6];
2380 __be16 r6;
2381 u8 macaddr2[6];
2382 __be16 r7;
2383 u8 macaddr3[6];
2384 };
2385
2386 #define FW_ACL_MAC_CMD_PFN_S 8
2387 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2388
2389 #define FW_ACL_MAC_CMD_VFN_S 0
2390 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2391
2392 #define FW_ACL_MAC_CMD_EN_S 31
2393 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S)
2394
2395 struct fw_acl_vlan_cmd {
2396 __be32 op_to_vfn;
2397 __be32 en_to_len16;
2398 u8 nvlan;
2399 u8 dropnovlan_fm;
2400 u8 r3_lo[6];
2401 __be16 vlanid[16];
2402 };
2403
2404 #define FW_ACL_VLAN_CMD_PFN_S 8
2405 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S)
2406
2407 #define FW_ACL_VLAN_CMD_VFN_S 0
2408 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S)
2409
2410 #define FW_ACL_VLAN_CMD_EN_S 31
2411 #define FW_ACL_VLAN_CMD_EN_M 0x1
2412 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2413 #define FW_ACL_VLAN_CMD_EN_G(x) \
2414 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2415 #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U)
2416
2417 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
2418 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2419
2420 #define FW_ACL_VLAN_CMD_FM_S 6
2421 #define FW_ACL_VLAN_CMD_FM_M 0x1
2422 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2423 #define FW_ACL_VLAN_CMD_FM_G(x) \
2424 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2425 #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U)
2426
2427 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2428 enum fw_port_cap {
2429 FW_PORT_CAP_SPEED_100M = 0x0001,
2430 FW_PORT_CAP_SPEED_1G = 0x0002,
2431 FW_PORT_CAP_SPEED_25G = 0x0004,
2432 FW_PORT_CAP_SPEED_10G = 0x0008,
2433 FW_PORT_CAP_SPEED_40G = 0x0010,
2434 FW_PORT_CAP_SPEED_100G = 0x0020,
2435 FW_PORT_CAP_FC_RX = 0x0040,
2436 FW_PORT_CAP_FC_TX = 0x0080,
2437 FW_PORT_CAP_ANEG = 0x0100,
2438 FW_PORT_CAP_MDIX = 0x0200,
2439 FW_PORT_CAP_MDIAUTO = 0x0400,
2440 FW_PORT_CAP_FEC_RS = 0x0800,
2441 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
2442 FW_PORT_CAP_FEC_RESERVED = 0x2000,
2443 FW_PORT_CAP_802_3_PAUSE = 0x4000,
2444 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
2445 };
2446
2447 #define FW_PORT_CAP_SPEED_S 0
2448 #define FW_PORT_CAP_SPEED_M 0x3f
2449 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S)
2450 #define FW_PORT_CAP_SPEED_G(x) \
2451 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2452
2453 enum fw_port_mdi {
2454 FW_PORT_CAP_MDI_UNCHANGED,
2455 FW_PORT_CAP_MDI_AUTO,
2456 FW_PORT_CAP_MDI_F_STRAIGHT,
2457 FW_PORT_CAP_MDI_F_CROSSOVER
2458 };
2459
2460 #define FW_PORT_CAP_MDI_S 9
2461 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2462
2463 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2464 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
2465 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
2466 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
2467 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
2468 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
2469 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
2470 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
2471 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL
2472 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL
2473 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
2474 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
2475 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
2476 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL
2477 #define FW_PORT_CAP32_FC_RX 0x00010000UL
2478 #define FW_PORT_CAP32_FC_TX 0x00020000UL
2479 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
2480 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
2481 #define FW_PORT_CAP32_ANEG 0x00100000UL
2482 #define FW_PORT_CAP32_MDIX 0x00200000UL
2483 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL
2484 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
2485 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
2486 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
2487 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
2488 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
2489 #define FW_PORT_CAP32_RESERVED2 0xf0000000UL
2490
2491 #define FW_PORT_CAP32_SPEED_S 0
2492 #define FW_PORT_CAP32_SPEED_M 0xfff
2493 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S)
2494 #define FW_PORT_CAP32_SPEED_G(x) \
2495 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2496
2497 #define FW_PORT_CAP32_FC_S 16
2498 #define FW_PORT_CAP32_FC_M 0x3
2499 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S)
2500 #define FW_PORT_CAP32_FC_G(x) \
2501 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2502
2503 #define FW_PORT_CAP32_802_3_S 18
2504 #define FW_PORT_CAP32_802_3_M 0x3
2505 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S)
2506 #define FW_PORT_CAP32_802_3_G(x) \
2507 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2508
2509 #define FW_PORT_CAP32_ANEG_S 20
2510 #define FW_PORT_CAP32_ANEG_M 0x1
2511 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)
2512 #define FW_PORT_CAP32_ANEG_G(x) \
2513 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2514
2515 enum fw_port_mdi32 {
2516 FW_PORT_CAP32_MDI_UNCHANGED,
2517 FW_PORT_CAP32_MDI_AUTO,
2518 FW_PORT_CAP32_MDI_F_STRAIGHT,
2519 FW_PORT_CAP32_MDI_F_CROSSOVER
2520 };
2521
2522 #define FW_PORT_CAP32_MDI_S 21
2523 #define FW_PORT_CAP32_MDI_M 3
2524 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2525 #define FW_PORT_CAP32_MDI_G(x) \
2526 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2527
2528 #define FW_PORT_CAP32_FEC_S 23
2529 #define FW_PORT_CAP32_FEC_M 0x1f
2530 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S)
2531 #define FW_PORT_CAP32_FEC_G(x) \
2532 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2533
2534 /* macros to isolate various 32-bit Port Capabilities sub-fields */
2535 #define CAP32_SPEED(__cap32) \
2536 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2537
2538 #define CAP32_FEC(__cap32) \
2539 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2540
2541 enum fw_port_action {
2542 FW_PORT_ACTION_L1_CFG = 0x0001,
2543 FW_PORT_ACTION_L2_CFG = 0x0002,
2544 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
2545 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
2546 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
2547 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
2548 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
2549 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
2550 FW_PORT_ACTION_L1_CFG32 = 0x0009,
2551 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
2552 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2553 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
2554 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
2555 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
2556 FW_PORT_ACTION_L1_LPBK = 0x0021,
2557 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
2558 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
2559 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2560 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2561 FW_PORT_ACTION_PHY_RESET = 0x0040,
2562 FW_PORT_ACTION_PMA_RESET = 0x0041,
2563 FW_PORT_ACTION_PCS_RESET = 0x0042,
2564 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
2565 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
2566 FW_PORT_ACTION_AN_RESET = 0x0045
2567 };
2568
2569 enum fw_port_l2cfg_ctlbf {
2570 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2571 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2572 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2573 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2574 FW_PORT_L2_CTLBF_IVLAN = 0x10,
2575 FW_PORT_L2_CTLBF_TXIPG = 0x20
2576 };
2577
2578 enum fw_port_dcb_versions {
2579 FW_PORT_DCB_VER_UNKNOWN,
2580 FW_PORT_DCB_VER_CEE1D0,
2581 FW_PORT_DCB_VER_CEE1D01,
2582 FW_PORT_DCB_VER_IEEE,
2583 FW_PORT_DCB_VER_AUTO = 7
2584 };
2585
2586 enum fw_port_dcb_cfg {
2587 FW_PORT_DCB_CFG_PG = 0x01,
2588 FW_PORT_DCB_CFG_PFC = 0x02,
2589 FW_PORT_DCB_CFG_APPL = 0x04
2590 };
2591
2592 enum fw_port_dcb_cfg_rc {
2593 FW_PORT_DCB_CFG_SUCCESS = 0x0,
2594 FW_PORT_DCB_CFG_ERROR = 0x1
2595 };
2596
2597 enum fw_port_dcb_type {
2598 FW_PORT_DCB_TYPE_PGID = 0x00,
2599 FW_PORT_DCB_TYPE_PGRATE = 0x01,
2600 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
2601 FW_PORT_DCB_TYPE_PFC = 0x03,
2602 FW_PORT_DCB_TYPE_APP_ID = 0x04,
2603 FW_PORT_DCB_TYPE_CONTROL = 0x05,
2604 };
2605
2606 enum fw_port_dcb_feature_state {
2607 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2608 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2609 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2610 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2611 };
2612
2613 struct fw_port_cmd {
2614 __be32 op_to_portid;
2615 __be32 action_to_len16;
2616 union fw_port {
2617 struct fw_port_l1cfg {
2618 __be32 rcap;
2619 __be32 r;
2620 } l1cfg;
2621 struct fw_port_l2cfg {
2622 __u8 ctlbf;
2623 __u8 ovlan3_to_ivlan0;
2624 __be16 ivlantype;
2625 __be16 txipg_force_pinfo;
2626 __be16 mtu;
2627 __be16 ovlan0mask;
2628 __be16 ovlan0type;
2629 __be16 ovlan1mask;
2630 __be16 ovlan1type;
2631 __be16 ovlan2mask;
2632 __be16 ovlan2type;
2633 __be16 ovlan3mask;
2634 __be16 ovlan3type;
2635 } l2cfg;
2636 struct fw_port_info {
2637 __be32 lstatus_to_modtype;
2638 __be16 pcap;
2639 __be16 acap;
2640 __be16 mtu;
2641 __u8 cbllen;
2642 __u8 auxlinfo;
2643 __u8 dcbxdis_pkd;
2644 __u8 r8_lo;
2645 __be16 lpacap;
2646 __be64 r9;
2647 } info;
2648 struct fw_port_diags {
2649 __u8 diagop;
2650 __u8 r[3];
2651 __be32 diagval;
2652 } diags;
2653 union fw_port_dcb {
2654 struct fw_port_dcb_pgid {
2655 __u8 type;
2656 __u8 apply_pkd;
2657 __u8 r10_lo[2];
2658 __be32 pgid;
2659 __be64 r11;
2660 } pgid;
2661 struct fw_port_dcb_pgrate {
2662 __u8 type;
2663 __u8 apply_pkd;
2664 __u8 r10_lo[5];
2665 __u8 num_tcs_supported;
2666 __u8 pgrate[8];
2667 __u8 tsa[8];
2668 } pgrate;
2669 struct fw_port_dcb_priorate {
2670 __u8 type;
2671 __u8 apply_pkd;
2672 __u8 r10_lo[6];
2673 __u8 strict_priorate[8];
2674 } priorate;
2675 struct fw_port_dcb_pfc {
2676 __u8 type;
2677 __u8 pfcen;
2678 __u8 r10[5];
2679 __u8 max_pfc_tcs;
2680 __be64 r11;
2681 } pfc;
2682 struct fw_port_app_priority {
2683 __u8 type;
2684 __u8 r10[2];
2685 __u8 idx;
2686 __u8 user_prio_map;
2687 __u8 sel_field;
2688 __be16 protocolid;
2689 __be64 r12;
2690 } app_priority;
2691 struct fw_port_dcb_control {
2692 __u8 type;
2693 __u8 all_syncd_pkd;
2694 __be16 dcb_version_to_app_state;
2695 __be32 r11;
2696 __be64 r12;
2697 } control;
2698 } dcb;
2699 struct fw_port_l1cfg32 {
2700 __be32 rcap32;
2701 __be32 r;
2702 } l1cfg32;
2703 struct fw_port_info32 {
2704 __be32 lstatus32_to_cbllen32;
2705 __be32 auxlinfo32_mtu32;
2706 __be32 linkattr32;
2707 __be32 pcaps32;
2708 __be32 acaps32;
2709 __be32 lpacaps32;
2710 } info32;
2711 } u;
2712 };
2713
2714 #define FW_PORT_CMD_READ_S 22
2715 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S)
2716 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U)
2717
2718 #define FW_PORT_CMD_PORTID_S 0
2719 #define FW_PORT_CMD_PORTID_M 0xf
2720 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2721 #define FW_PORT_CMD_PORTID_G(x) \
2722 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2723
2724 #define FW_PORT_CMD_ACTION_S 16
2725 #define FW_PORT_CMD_ACTION_M 0xffff
2726 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2727 #define FW_PORT_CMD_ACTION_G(x) \
2728 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2729
2730 #define FW_PORT_CMD_OVLAN3_S 7
2731 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2732
2733 #define FW_PORT_CMD_OVLAN2_S 6
2734 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2735
2736 #define FW_PORT_CMD_OVLAN1_S 5
2737 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2738
2739 #define FW_PORT_CMD_OVLAN0_S 4
2740 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2741
2742 #define FW_PORT_CMD_IVLAN0_S 3
2743 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2744
2745 #define FW_PORT_CMD_TXIPG_S 3
2746 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S)
2747
2748 #define FW_PORT_CMD_LSTATUS_S 31
2749 #define FW_PORT_CMD_LSTATUS_M 0x1
2750 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S)
2751 #define FW_PORT_CMD_LSTATUS_G(x) \
2752 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2753 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U)
2754
2755 #define FW_PORT_CMD_LSPEED_S 24
2756 #define FW_PORT_CMD_LSPEED_M 0x3f
2757 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2758 #define FW_PORT_CMD_LSPEED_G(x) \
2759 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2760
2761 #define FW_PORT_CMD_TXPAUSE_S 23
2762 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S)
2763 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U)
2764
2765 #define FW_PORT_CMD_RXPAUSE_S 22
2766 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S)
2767 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U)
2768
2769 #define FW_PORT_CMD_MDIOCAP_S 21
2770 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S)
2771 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U)
2772
2773 #define FW_PORT_CMD_MDIOADDR_S 16
2774 #define FW_PORT_CMD_MDIOADDR_M 0x1f
2775 #define FW_PORT_CMD_MDIOADDR_G(x) \
2776 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2777
2778 #define FW_PORT_CMD_LPTXPAUSE_S 15
2779 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2780 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2781
2782 #define FW_PORT_CMD_LPRXPAUSE_S 14
2783 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2784 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2785
2786 #define FW_PORT_CMD_PTYPE_S 8
2787 #define FW_PORT_CMD_PTYPE_M 0x1f
2788 #define FW_PORT_CMD_PTYPE_G(x) \
2789 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2790
2791 #define FW_PORT_CMD_LINKDNRC_S 5
2792 #define FW_PORT_CMD_LINKDNRC_M 0x7
2793 #define FW_PORT_CMD_LINKDNRC_G(x) \
2794 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2795
2796 #define FW_PORT_CMD_MODTYPE_S 0
2797 #define FW_PORT_CMD_MODTYPE_M 0x1f
2798 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S)
2799 #define FW_PORT_CMD_MODTYPE_G(x) \
2800 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2801
2802 #define FW_PORT_CMD_DCBXDIS_S 7
2803 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S)
2804 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U)
2805
2806 #define FW_PORT_CMD_APPLY_S 7
2807 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S)
2808 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U)
2809
2810 #define FW_PORT_CMD_ALL_SYNCD_S 7
2811 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2812 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2813
2814 #define FW_PORT_CMD_DCB_VERSION_S 12
2815 #define FW_PORT_CMD_DCB_VERSION_M 0x7
2816 #define FW_PORT_CMD_DCB_VERSION_G(x) \
2817 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2818
2819 #define FW_PORT_CMD_LSTATUS32_S 31
2820 #define FW_PORT_CMD_LSTATUS32_M 0x1
2821 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S)
2822 #define FW_PORT_CMD_LSTATUS32_G(x) \
2823 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
2824 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U)
2825
2826 #define FW_PORT_CMD_LINKDNRC32_S 28
2827 #define FW_PORT_CMD_LINKDNRC32_M 0x7
2828 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S)
2829 #define FW_PORT_CMD_LINKDNRC32_G(x) \
2830 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
2831
2832 #define FW_PORT_CMD_DCBXDIS32_S 27
2833 #define FW_PORT_CMD_DCBXDIS32_M 0x1
2834 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S)
2835 #define FW_PORT_CMD_DCBXDIS32_G(x) \
2836 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
2837 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U)
2838
2839 #define FW_PORT_CMD_MDIOCAP32_S 26
2840 #define FW_PORT_CMD_MDIOCAP32_M 0x1
2841 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S)
2842 #define FW_PORT_CMD_MDIOCAP32_G(x) \
2843 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
2844 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U)
2845
2846 #define FW_PORT_CMD_MDIOADDR32_S 21
2847 #define FW_PORT_CMD_MDIOADDR32_M 0x1f
2848 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S)
2849 #define FW_PORT_CMD_MDIOADDR32_G(x) \
2850 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
2851
2852 #define FW_PORT_CMD_PORTTYPE32_S 13
2853 #define FW_PORT_CMD_PORTTYPE32_M 0xff
2854 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S)
2855 #define FW_PORT_CMD_PORTTYPE32_G(x) \
2856 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
2857
2858 #define FW_PORT_CMD_MODTYPE32_S 8
2859 #define FW_PORT_CMD_MODTYPE32_M 0x1f
2860 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S)
2861 #define FW_PORT_CMD_MODTYPE32_G(x) \
2862 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
2863
2864 #define FW_PORT_CMD_CBLLEN32_S 0
2865 #define FW_PORT_CMD_CBLLEN32_M 0xff
2866 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S)
2867 #define FW_PORT_CMD_CBLLEN32_G(x) \
2868 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
2869
2870 #define FW_PORT_CMD_AUXLINFO32_S 24
2871 #define FW_PORT_CMD_AUXLINFO32_M 0xff
2872 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S)
2873 #define FW_PORT_CMD_AUXLINFO32_G(x) \
2874 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
2875
2876 #define FW_PORT_AUXLINFO32_KX4_S 2
2877 #define FW_PORT_AUXLINFO32_KX4_M 0x1
2878 #define FW_PORT_AUXLINFO32_KX4_V(x) \
2879 ((x) << FW_PORT_AUXLINFO32_KX4_S)
2880 #define FW_PORT_AUXLINFO32_KX4_G(x) \
2881 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
2882 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U)
2883
2884 #define FW_PORT_AUXLINFO32_KR_S 1
2885 #define FW_PORT_AUXLINFO32_KR_M 0x1
2886 #define FW_PORT_AUXLINFO32_KR_V(x) \
2887 ((x) << FW_PORT_AUXLINFO32_KR_S)
2888 #define FW_PORT_AUXLINFO32_KR_G(x) \
2889 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
2890 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U)
2891
2892 #define FW_PORT_CMD_MTU32_S 0
2893 #define FW_PORT_CMD_MTU32_M 0xffff
2894 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S)
2895 #define FW_PORT_CMD_MTU32_G(x) \
2896 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
2897
2898 enum fw_port_type {
2899 FW_PORT_TYPE_FIBER_XFI,
2900 FW_PORT_TYPE_FIBER_XAUI,
2901 FW_PORT_TYPE_BT_SGMII,
2902 FW_PORT_TYPE_BT_XFI,
2903 FW_PORT_TYPE_BT_XAUI,
2904 FW_PORT_TYPE_KX4,
2905 FW_PORT_TYPE_CX4,
2906 FW_PORT_TYPE_KX,
2907 FW_PORT_TYPE_KR,
2908 FW_PORT_TYPE_SFP,
2909 FW_PORT_TYPE_BP_AP,
2910 FW_PORT_TYPE_BP4_AP,
2911 FW_PORT_TYPE_QSFP_10G,
2912 FW_PORT_TYPE_QSA,
2913 FW_PORT_TYPE_QSFP,
2914 FW_PORT_TYPE_BP40_BA,
2915 FW_PORT_TYPE_KR4_100G,
2916 FW_PORT_TYPE_CR4_QSFP,
2917 FW_PORT_TYPE_CR_QSFP,
2918 FW_PORT_TYPE_CR2_QSFP,
2919 FW_PORT_TYPE_SFP28,
2920 FW_PORT_TYPE_KR_SFP28,
2921 FW_PORT_TYPE_KR_XLAUI,
2922
2923 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2924 };
2925
2926 enum fw_port_module_type {
2927 FW_PORT_MOD_TYPE_NA,
2928 FW_PORT_MOD_TYPE_LR,
2929 FW_PORT_MOD_TYPE_SR,
2930 FW_PORT_MOD_TYPE_ER,
2931 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2932 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2933 FW_PORT_MOD_TYPE_LRM,
2934 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3,
2935 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2,
2936 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1,
2937
2938 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2939 };
2940
2941 enum fw_port_mod_sub_type {
2942 FW_PORT_MOD_SUB_TYPE_NA,
2943 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2944 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2945 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2946 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2947 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2948 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2949
2950 /* The following will never been in the VPD. They are TWINAX cable
2951 * lengths decoded from SFP+ module i2c PROMs. These should
2952 * almost certainly go somewhere else ...
2953 */
2954 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2955 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2956 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2957 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2958 };
2959
2960 enum fw_port_stats_tx_index {
2961 FW_STAT_TX_PORT_BYTES_IX = 0,
2962 FW_STAT_TX_PORT_FRAMES_IX,
2963 FW_STAT_TX_PORT_BCAST_IX,
2964 FW_STAT_TX_PORT_MCAST_IX,
2965 FW_STAT_TX_PORT_UCAST_IX,
2966 FW_STAT_TX_PORT_ERROR_IX,
2967 FW_STAT_TX_PORT_64B_IX,
2968 FW_STAT_TX_PORT_65B_127B_IX,
2969 FW_STAT_TX_PORT_128B_255B_IX,
2970 FW_STAT_TX_PORT_256B_511B_IX,
2971 FW_STAT_TX_PORT_512B_1023B_IX,
2972 FW_STAT_TX_PORT_1024B_1518B_IX,
2973 FW_STAT_TX_PORT_1519B_MAX_IX,
2974 FW_STAT_TX_PORT_DROP_IX,
2975 FW_STAT_TX_PORT_PAUSE_IX,
2976 FW_STAT_TX_PORT_PPP0_IX,
2977 FW_STAT_TX_PORT_PPP1_IX,
2978 FW_STAT_TX_PORT_PPP2_IX,
2979 FW_STAT_TX_PORT_PPP3_IX,
2980 FW_STAT_TX_PORT_PPP4_IX,
2981 FW_STAT_TX_PORT_PPP5_IX,
2982 FW_STAT_TX_PORT_PPP6_IX,
2983 FW_STAT_TX_PORT_PPP7_IX,
2984 FW_NUM_PORT_TX_STATS
2985 };
2986
2987 enum fw_port_stat_rx_index {
2988 FW_STAT_RX_PORT_BYTES_IX = 0,
2989 FW_STAT_RX_PORT_FRAMES_IX,
2990 FW_STAT_RX_PORT_BCAST_IX,
2991 FW_STAT_RX_PORT_MCAST_IX,
2992 FW_STAT_RX_PORT_UCAST_IX,
2993 FW_STAT_RX_PORT_MTU_ERROR_IX,
2994 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2995 FW_STAT_RX_PORT_CRC_ERROR_IX,
2996 FW_STAT_RX_PORT_LEN_ERROR_IX,
2997 FW_STAT_RX_PORT_SYM_ERROR_IX,
2998 FW_STAT_RX_PORT_64B_IX,
2999 FW_STAT_RX_PORT_65B_127B_IX,
3000 FW_STAT_RX_PORT_128B_255B_IX,
3001 FW_STAT_RX_PORT_256B_511B_IX,
3002 FW_STAT_RX_PORT_512B_1023B_IX,
3003 FW_STAT_RX_PORT_1024B_1518B_IX,
3004 FW_STAT_RX_PORT_1519B_MAX_IX,
3005 FW_STAT_RX_PORT_PAUSE_IX,
3006 FW_STAT_RX_PORT_PPP0_IX,
3007 FW_STAT_RX_PORT_PPP1_IX,
3008 FW_STAT_RX_PORT_PPP2_IX,
3009 FW_STAT_RX_PORT_PPP3_IX,
3010 FW_STAT_RX_PORT_PPP4_IX,
3011 FW_STAT_RX_PORT_PPP5_IX,
3012 FW_STAT_RX_PORT_PPP6_IX,
3013 FW_STAT_RX_PORT_PPP7_IX,
3014 FW_STAT_RX_PORT_LESS_64B_IX,
3015 FW_STAT_RX_PORT_MAC_ERROR_IX,
3016 FW_NUM_PORT_RX_STATS
3017 };
3018
3019 /* port stats */
3020 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3021
3022 struct fw_port_stats_cmd {
3023 __be32 op_to_portid;
3024 __be32 retval_len16;
3025 union fw_port_stats {
3026 struct fw_port_stats_ctl {
3027 u8 nstats_bg_bm;
3028 u8 tx_ix;
3029 __be16 r6;
3030 __be32 r7;
3031 __be64 stat0;
3032 __be64 stat1;
3033 __be64 stat2;
3034 __be64 stat3;
3035 __be64 stat4;
3036 __be64 stat5;
3037 } ctl;
3038 struct fw_port_stats_all {
3039 __be64 tx_bytes;
3040 __be64 tx_frames;
3041 __be64 tx_bcast;
3042 __be64 tx_mcast;
3043 __be64 tx_ucast;
3044 __be64 tx_error;
3045 __be64 tx_64b;
3046 __be64 tx_65b_127b;
3047 __be64 tx_128b_255b;
3048 __be64 tx_256b_511b;
3049 __be64 tx_512b_1023b;
3050 __be64 tx_1024b_1518b;
3051 __be64 tx_1519b_max;
3052 __be64 tx_drop;
3053 __be64 tx_pause;
3054 __be64 tx_ppp0;
3055 __be64 tx_ppp1;
3056 __be64 tx_ppp2;
3057 __be64 tx_ppp3;
3058 __be64 tx_ppp4;
3059 __be64 tx_ppp5;
3060 __be64 tx_ppp6;
3061 __be64 tx_ppp7;
3062 __be64 rx_bytes;
3063 __be64 rx_frames;
3064 __be64 rx_bcast;
3065 __be64 rx_mcast;
3066 __be64 rx_ucast;
3067 __be64 rx_mtu_error;
3068 __be64 rx_mtu_crc_error;
3069 __be64 rx_crc_error;
3070 __be64 rx_len_error;
3071 __be64 rx_sym_error;
3072 __be64 rx_64b;
3073 __be64 rx_65b_127b;
3074 __be64 rx_128b_255b;
3075 __be64 rx_256b_511b;
3076 __be64 rx_512b_1023b;
3077 __be64 rx_1024b_1518b;
3078 __be64 rx_1519b_max;
3079 __be64 rx_pause;
3080 __be64 rx_ppp0;
3081 __be64 rx_ppp1;
3082 __be64 rx_ppp2;
3083 __be64 rx_ppp3;
3084 __be64 rx_ppp4;
3085 __be64 rx_ppp5;
3086 __be64 rx_ppp6;
3087 __be64 rx_ppp7;
3088 __be64 rx_less_64b;
3089 __be64 rx_bg_drop;
3090 __be64 rx_bg_trunc;
3091 } all;
3092 } u;
3093 };
3094
3095 /* port loopback stats */
3096 #define FW_NUM_LB_STATS 16
3097 enum fw_port_lb_stats_index {
3098 FW_STAT_LB_PORT_BYTES_IX,
3099 FW_STAT_LB_PORT_FRAMES_IX,
3100 FW_STAT_LB_PORT_BCAST_IX,
3101 FW_STAT_LB_PORT_MCAST_IX,
3102 FW_STAT_LB_PORT_UCAST_IX,
3103 FW_STAT_LB_PORT_ERROR_IX,
3104 FW_STAT_LB_PORT_64B_IX,
3105 FW_STAT_LB_PORT_65B_127B_IX,
3106 FW_STAT_LB_PORT_128B_255B_IX,
3107 FW_STAT_LB_PORT_256B_511B_IX,
3108 FW_STAT_LB_PORT_512B_1023B_IX,
3109 FW_STAT_LB_PORT_1024B_1518B_IX,
3110 FW_STAT_LB_PORT_1519B_MAX_IX,
3111 FW_STAT_LB_PORT_DROP_FRAMES_IX
3112 };
3113
3114 struct fw_port_lb_stats_cmd {
3115 __be32 op_to_lbport;
3116 __be32 retval_len16;
3117 union fw_port_lb_stats {
3118 struct fw_port_lb_stats_ctl {
3119 u8 nstats_bg_bm;
3120 u8 ix_pkd;
3121 __be16 r6;
3122 __be32 r7;
3123 __be64 stat0;
3124 __be64 stat1;
3125 __be64 stat2;
3126 __be64 stat3;
3127 __be64 stat4;
3128 __be64 stat5;
3129 } ctl;
3130 struct fw_port_lb_stats_all {
3131 __be64 tx_bytes;
3132 __be64 tx_frames;
3133 __be64 tx_bcast;
3134 __be64 tx_mcast;
3135 __be64 tx_ucast;
3136 __be64 tx_error;
3137 __be64 tx_64b;
3138 __be64 tx_65b_127b;
3139 __be64 tx_128b_255b;
3140 __be64 tx_256b_511b;
3141 __be64 tx_512b_1023b;
3142 __be64 tx_1024b_1518b;
3143 __be64 tx_1519b_max;
3144 __be64 rx_lb_drop;
3145 __be64 rx_lb_trunc;
3146 } all;
3147 } u;
3148 };
3149
3150 enum fw_ptp_subop {
3151 /* none */
3152 FW_PTP_SC_INIT_TIMER = 0x00,
3153 FW_PTP_SC_TX_TYPE = 0x01,
3154 /* init */
3155 FW_PTP_SC_RXTIME_STAMP = 0x08,
3156 FW_PTP_SC_RDRX_TYPE = 0x09,
3157 /* ts */
3158 FW_PTP_SC_ADJ_FREQ = 0x10,
3159 FW_PTP_SC_ADJ_TIME = 0x11,
3160 FW_PTP_SC_ADJ_FTIME = 0x12,
3161 FW_PTP_SC_WALL_CLOCK = 0x13,
3162 FW_PTP_SC_GET_TIME = 0x14,
3163 FW_PTP_SC_SET_TIME = 0x15,
3164 };
3165
3166 struct fw_ptp_cmd {
3167 __be32 op_to_portid;
3168 __be32 retval_len16;
3169 union fw_ptp {
3170 struct fw_ptp_sc {
3171 __u8 sc;
3172 __u8 r3[7];
3173 } scmd;
3174 struct fw_ptp_init {
3175 __u8 sc;
3176 __u8 txchan;
3177 __be16 absid;
3178 __be16 mode;
3179 __be16 r3;
3180 } init;
3181 struct fw_ptp_ts {
3182 __u8 sc;
3183 __u8 sign;
3184 __be16 r3;
3185 __be32 ppb;
3186 __be64 tm;
3187 } ts;
3188 } u;
3189 __be64 r3;
3190 };
3191
3192 #define FW_PTP_CMD_PORTID_S 0
3193 #define FW_PTP_CMD_PORTID_M 0xf
3194 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S)
3195 #define FW_PTP_CMD_PORTID_G(x) \
3196 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3197
3198 struct fw_rss_ind_tbl_cmd {
3199 __be32 op_to_viid;
3200 __be32 retval_len16;
3201 __be16 niqid;
3202 __be16 startidx;
3203 __be32 r3;
3204 __be32 iq0_to_iq2;
3205 __be32 iq3_to_iq5;
3206 __be32 iq6_to_iq8;
3207 __be32 iq9_to_iq11;
3208 __be32 iq12_to_iq14;
3209 __be32 iq15_to_iq17;
3210 __be32 iq18_to_iq20;
3211 __be32 iq21_to_iq23;
3212 __be32 iq24_to_iq26;
3213 __be32 iq27_to_iq29;
3214 __be32 iq30_iq31;
3215 __be32 r15_lo;
3216 };
3217
3218 #define FW_RSS_IND_TBL_CMD_VIID_S 0
3219 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3220
3221 #define FW_RSS_IND_TBL_CMD_IQ0_S 20
3222 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3223
3224 #define FW_RSS_IND_TBL_CMD_IQ1_S 10
3225 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3226
3227 #define FW_RSS_IND_TBL_CMD_IQ2_S 0
3228 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3229
3230 struct fw_rss_glb_config_cmd {
3231 __be32 op_to_write;
3232 __be32 retval_len16;
3233 union fw_rss_glb_config {
3234 struct fw_rss_glb_config_manual {
3235 __be32 mode_pkd;
3236 __be32 r3;
3237 __be64 r4;
3238 __be64 r5;
3239 } manual;
3240 struct fw_rss_glb_config_basicvirtual {
3241 __be32 mode_pkd;
3242 __be32 synmapen_to_hashtoeplitz;
3243 __be64 r8;
3244 __be64 r9;
3245 } basicvirtual;
3246 } u;
3247 };
3248
3249 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28
3250 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf
3251 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3252 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
3253 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3254
3255 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
3256 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
3257
3258 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8
3259 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \
3260 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3261 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \
3262 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3263
3264 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7
3265 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \
3266 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3267 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \
3268 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3269
3270 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6
3271 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \
3272 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3273 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \
3274 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3275
3276 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5
3277 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \
3278 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3279 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \
3280 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3281
3282 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4
3283 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \
3284 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3285 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \
3286 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3287
3288 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3
3289 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \
3290 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3291 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \
3292 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3293
3294 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2
3295 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \
3296 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3297 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \
3298 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3299
3300 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1
3301 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \
3302 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3303 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \
3304 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3305
3306 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0
3307 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
3308 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3309 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \
3310 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3311
3312 struct fw_rss_vi_config_cmd {
3313 __be32 op_to_viid;
3314 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3315 __be32 retval_len16;
3316 union fw_rss_vi_config {
3317 struct fw_rss_vi_config_manual {
3318 __be64 r3;
3319 __be64 r4;
3320 __be64 r5;
3321 } manual;
3322 struct fw_rss_vi_config_basicvirtual {
3323 __be32 r6;
3324 __be32 defaultq_to_udpen;
3325 __be64 r9;
3326 __be64 r10;
3327 } basicvirtual;
3328 } u;
3329 };
3330
3331 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0
3332 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3333
3334 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16
3335 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff
3336 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \
3337 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3338 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \
3339 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3340 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3341
3342 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4
3343 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \
3344 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3345 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \
3346 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3347
3348 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3
3349 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \
3350 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3351 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \
3352 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3353
3354 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2
3355 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \
3356 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3357 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \
3358 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3359
3360 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1
3361 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \
3362 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3363 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \
3364 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3365
3366 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0
3367 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3368 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3369
3370 enum fw_sched_sc {
3371 FW_SCHED_SC_PARAMS = 1,
3372 };
3373
3374 struct fw_sched_cmd {
3375 __be32 op_to_write;
3376 __be32 retval_len16;
3377 union fw_sched {
3378 struct fw_sched_config {
3379 __u8 sc;
3380 __u8 type;
3381 __u8 minmaxen;
3382 __u8 r3[5];
3383 __u8 nclasses[4];
3384 __be32 r4;
3385 } config;
3386 struct fw_sched_params {
3387 __u8 sc;
3388 __u8 type;
3389 __u8 level;
3390 __u8 mode;
3391 __u8 unit;
3392 __u8 rate;
3393 __u8 ch;
3394 __u8 cl;
3395 __be32 min;
3396 __be32 max;
3397 __be16 weight;
3398 __be16 pktsize;
3399 __be16 burstsize;
3400 __be16 r4;
3401 } params;
3402 } u;
3403 };
3404
3405 struct fw_clip_cmd {
3406 __be32 op_to_write;
3407 __be32 alloc_to_len16;
3408 __be64 ip_hi;
3409 __be64 ip_lo;
3410 __be32 r4[2];
3411 };
3412
3413 #define FW_CLIP_CMD_ALLOC_S 31
3414 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)
3415 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U)
3416
3417 #define FW_CLIP_CMD_FREE_S 30
3418 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)
3419 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U)
3420
3421 enum fw_error_type {
3422 FW_ERROR_TYPE_EXCEPTION = 0x0,
3423 FW_ERROR_TYPE_HWMODULE = 0x1,
3424 FW_ERROR_TYPE_WR = 0x2,
3425 FW_ERROR_TYPE_ACL = 0x3,
3426 };
3427
3428 struct fw_error_cmd {
3429 __be32 op_to_type;
3430 __be32 len16_pkd;
3431 union fw_error {
3432 struct fw_error_exception {
3433 __be32 info[6];
3434 } exception;
3435 struct fw_error_hwmodule {
3436 __be32 regaddr;
3437 __be32 regval;
3438 } hwmodule;
3439 struct fw_error_wr {
3440 __be16 cidx;
3441 __be16 pfn_vfn;
3442 __be32 eqid;
3443 u8 wrhdr[16];
3444 } wr;
3445 struct fw_error_acl {
3446 __be16 cidx;
3447 __be16 pfn_vfn;
3448 __be32 eqid;
3449 __be16 mv_pkd;
3450 u8 val[6];
3451 __be64 r4;
3452 } acl;
3453 } u;
3454 };
3455
3456 struct fw_debug_cmd {
3457 __be32 op_type;
3458 __be32 len16_pkd;
3459 union fw_debug {
3460 struct fw_debug_assert {
3461 __be32 fcid;
3462 __be32 line;
3463 __be32 x;
3464 __be32 y;
3465 u8 filename_0_7[8];
3466 u8 filename_8_15[8];
3467 __be64 r3;
3468 } assert;
3469 struct fw_debug_prt {
3470 __be16 dprtstridx;
3471 __be16 r3[3];
3472 __be32 dprtstrparam0;
3473 __be32 dprtstrparam1;
3474 __be32 dprtstrparam2;
3475 __be32 dprtstrparam3;
3476 } prt;
3477 } u;
3478 };
3479
3480 #define FW_DEBUG_CMD_TYPE_S 0
3481 #define FW_DEBUG_CMD_TYPE_M 0xff
3482 #define FW_DEBUG_CMD_TYPE_G(x) \
3483 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3484
3485 struct fw_hma_cmd {
3486 __be32 op_pkd;
3487 __be32 retval_len16;
3488 __be32 mode_to_pcie_params;
3489 __be32 naddr_size;
3490 __be32 addr_size_pkd;
3491 __be32 r6;
3492 __be64 phy_address[5];
3493 };
3494
3495 #define FW_HMA_CMD_MODE_S 31
3496 #define FW_HMA_CMD_MODE_M 0x1
3497 #define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S)
3498 #define FW_HMA_CMD_MODE_G(x) \
3499 (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3500 #define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U)
3501
3502 #define FW_HMA_CMD_SOC_S 30
3503 #define FW_HMA_CMD_SOC_M 0x1
3504 #define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S)
3505 #define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3506 #define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U)
3507
3508 #define FW_HMA_CMD_EOC_S 29
3509 #define FW_HMA_CMD_EOC_M 0x1
3510 #define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S)
3511 #define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3512 #define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U)
3513
3514 #define FW_HMA_CMD_PCIE_PARAMS_S 0
3515 #define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff
3516 #define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3517 #define FW_HMA_CMD_PCIE_PARAMS_G(x) \
3518 (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3519
3520 #define FW_HMA_CMD_NADDR_S 12
3521 #define FW_HMA_CMD_NADDR_M 0x3f
3522 #define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S)
3523 #define FW_HMA_CMD_NADDR_G(x) \
3524 (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3525
3526 #define FW_HMA_CMD_SIZE_S 0
3527 #define FW_HMA_CMD_SIZE_M 0xfff
3528 #define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S)
3529 #define FW_HMA_CMD_SIZE_G(x) \
3530 (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3531
3532 #define FW_HMA_CMD_ADDR_SIZE_S 11
3533 #define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff
3534 #define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S)
3535 #define FW_HMA_CMD_ADDR_SIZE_G(x) \
3536 (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3537
3538 enum pcie_fw_eval {
3539 PCIE_FW_EVAL_CRASH = 0,
3540 };
3541
3542 #define PCIE_FW_ERR_S 31
3543 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
3544 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
3545
3546 #define PCIE_FW_INIT_S 30
3547 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)
3548 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U)
3549
3550 #define PCIE_FW_HALT_S 29
3551 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)
3552 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U)
3553
3554 #define PCIE_FW_EVAL_S 24
3555 #define PCIE_FW_EVAL_M 0x7
3556 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3557
3558 #define PCIE_FW_MASTER_VLD_S 15
3559 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3560 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U)
3561
3562 #define PCIE_FW_MASTER_S 12
3563 #define PCIE_FW_MASTER_M 0x7
3564 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)
3565 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3566
3567 struct fw_hdr {
3568 u8 ver;
3569 u8 chip; /* terminator chip type */
3570 __be16 len512; /* bin length in units of 512-bytes */
3571 __be32 fw_ver; /* firmware version */
3572 __be32 tp_microcode_ver;
3573 u8 intfver_nic;
3574 u8 intfver_vnic;
3575 u8 intfver_ofld;
3576 u8 intfver_ri;
3577 u8 intfver_iscsipdu;
3578 u8 intfver_iscsi;
3579 u8 intfver_fcoepdu;
3580 u8 intfver_fcoe;
3581 __u32 reserved2;
3582 __u32 reserved3;
3583 __u32 reserved4;
3584 __be32 flags;
3585 __be32 reserved6[23];
3586 };
3587
3588 enum fw_hdr_chip {
3589 FW_HDR_CHIP_T4,
3590 FW_HDR_CHIP_T5,
3591 FW_HDR_CHIP_T6
3592 };
3593
3594 #define FW_HDR_FW_VER_MAJOR_S 24
3595 #define FW_HDR_FW_VER_MAJOR_M 0xff
3596 #define FW_HDR_FW_VER_MAJOR_V(x) \
3597 ((x) << FW_HDR_FW_VER_MAJOR_S)
3598 #define FW_HDR_FW_VER_MAJOR_G(x) \
3599 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3600
3601 #define FW_HDR_FW_VER_MINOR_S 16
3602 #define FW_HDR_FW_VER_MINOR_M 0xff
3603 #define FW_HDR_FW_VER_MINOR_V(x) \
3604 ((x) << FW_HDR_FW_VER_MINOR_S)
3605 #define FW_HDR_FW_VER_MINOR_G(x) \
3606 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3607
3608 #define FW_HDR_FW_VER_MICRO_S 8
3609 #define FW_HDR_FW_VER_MICRO_M 0xff
3610 #define FW_HDR_FW_VER_MICRO_V(x) \
3611 ((x) << FW_HDR_FW_VER_MICRO_S)
3612 #define FW_HDR_FW_VER_MICRO_G(x) \
3613 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3614
3615 #define FW_HDR_FW_VER_BUILD_S 0
3616 #define FW_HDR_FW_VER_BUILD_M 0xff
3617 #define FW_HDR_FW_VER_BUILD_V(x) \
3618 ((x) << FW_HDR_FW_VER_BUILD_S)
3619 #define FW_HDR_FW_VER_BUILD_G(x) \
3620 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3621
3622 enum fw_hdr_intfver {
3623 FW_HDR_INTFVER_NIC = 0x00,
3624 FW_HDR_INTFVER_VNIC = 0x00,
3625 FW_HDR_INTFVER_OFLD = 0x00,
3626 FW_HDR_INTFVER_RI = 0x00,
3627 FW_HDR_INTFVER_ISCSIPDU = 0x00,
3628 FW_HDR_INTFVER_ISCSI = 0x00,
3629 FW_HDR_INTFVER_FCOEPDU = 0x00,
3630 FW_HDR_INTFVER_FCOE = 0x00,
3631 };
3632
3633 enum fw_hdr_flags {
3634 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3635 };
3636
3637 /* length of the formatting string */
3638 #define FW_DEVLOG_FMT_LEN 192
3639
3640 /* maximum number of the formatting string parameters */
3641 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3642
3643 /* priority levels */
3644 enum fw_devlog_level {
3645 FW_DEVLOG_LEVEL_EMERG = 0x0,
3646 FW_DEVLOG_LEVEL_CRIT = 0x1,
3647 FW_DEVLOG_LEVEL_ERR = 0x2,
3648 FW_DEVLOG_LEVEL_NOTICE = 0x3,
3649 FW_DEVLOG_LEVEL_INFO = 0x4,
3650 FW_DEVLOG_LEVEL_DEBUG = 0x5,
3651 FW_DEVLOG_LEVEL_MAX = 0x5,
3652 };
3653
3654 /* facilities that may send a log message */
3655 enum fw_devlog_facility {
3656 FW_DEVLOG_FACILITY_CORE = 0x00,
3657 FW_DEVLOG_FACILITY_CF = 0x01,
3658 FW_DEVLOG_FACILITY_SCHED = 0x02,
3659 FW_DEVLOG_FACILITY_TIMER = 0x04,
3660 FW_DEVLOG_FACILITY_RES = 0x06,
3661 FW_DEVLOG_FACILITY_HW = 0x08,
3662 FW_DEVLOG_FACILITY_FLR = 0x10,
3663 FW_DEVLOG_FACILITY_DMAQ = 0x12,
3664 FW_DEVLOG_FACILITY_PHY = 0x14,
3665 FW_DEVLOG_FACILITY_MAC = 0x16,
3666 FW_DEVLOG_FACILITY_PORT = 0x18,
3667 FW_DEVLOG_FACILITY_VI = 0x1A,
3668 FW_DEVLOG_FACILITY_FILTER = 0x1C,
3669 FW_DEVLOG_FACILITY_ACL = 0x1E,
3670 FW_DEVLOG_FACILITY_TM = 0x20,
3671 FW_DEVLOG_FACILITY_QFC = 0x22,
3672 FW_DEVLOG_FACILITY_DCB = 0x24,
3673 FW_DEVLOG_FACILITY_ETH = 0x26,
3674 FW_DEVLOG_FACILITY_OFLD = 0x28,
3675 FW_DEVLOG_FACILITY_RI = 0x2A,
3676 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
3677 FW_DEVLOG_FACILITY_FCOE = 0x2E,
3678 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
3679 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
3680 FW_DEVLOG_FACILITY_CHNET = 0x34,
3681 FW_DEVLOG_FACILITY_MAX = 0x34,
3682 };
3683
3684 /* log message format */
3685 struct fw_devlog_e {
3686 __be64 timestamp;
3687 __be32 seqno;
3688 __be16 reserved1;
3689 __u8 level;
3690 __u8 facility;
3691 __u8 fmt[FW_DEVLOG_FMT_LEN];
3692 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
3693 __be32 reserved3[4];
3694 };
3695
3696 struct fw_devlog_cmd {
3697 __be32 op_to_write;
3698 __be32 retval_len16;
3699 __u8 level;
3700 __u8 r2[7];
3701 __be32 memtype_devlog_memaddr16_devlog;
3702 __be32 memsize_devlog;
3703 __be32 r3[2];
3704 };
3705
3706 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
3707 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
3708 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
3709 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3710 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3711
3712 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
3713 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
3714 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
3715 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3716 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3717
3718 /* P C I E F W P F 7 R E G I S T E R */
3719
3720 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3721 * access the "devlog" which needing to contact firmware. The encoding is
3722 * mostly the same as that returned by the DEVLOG command except for the size
3723 * which is encoded as the number of entries in multiples-1 of 128 here rather
3724 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
3725 * and 15 means 2048. This of course in turn constrains the allowed values
3726 * for the devlog size ...
3727 */
3728 #define PCIE_FW_PF_DEVLOG 7
3729
3730 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3731 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3732 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3733 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3734 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3735 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3736 PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3737
3738 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4
3739 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff
3740 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3741 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3742 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3743
3744 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
3745 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
3746 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3747 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3748 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3749
3750 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3751
3752 struct fw_crypto_lookaside_wr {
3753 __be32 op_to_cctx_size;
3754 __be32 len16_pkd;
3755 __be32 session_id;
3756 __be32 rx_chid_to_rx_q_id;
3757 __be32 key_addr;
3758 __be32 pld_size_hash_size;
3759 __be64 cookie;
3760 };
3761
3762 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3763 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3764 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3765 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3766 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3767 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3768 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3769
3770 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3771 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3772 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3773 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3774 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3775 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3776 FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3777 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3778
3779 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3780 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3781 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3782 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3783 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3784 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3785 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3786
3787 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3788 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3789 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3790 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3791 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3792 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3793 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3794
3795 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3796 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3797 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3798 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3799 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3800 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3801 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3802
3803 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3804 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3805 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3806 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3807 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3808 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3809 FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3810
3811 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3812 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3813 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3814 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3815 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3816 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3817 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3818
3819 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27
3820 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3
3821 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3822 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3823 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3824 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3825
3826 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3827 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3828 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3829 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3830 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3831 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3832 FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3833
3834 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23
3835 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3
3836 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3837 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3838 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3839 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3840
3841 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15
3842 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff
3843 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
3844 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
3845 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
3846 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
3847 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
3848
3849 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3850 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3851 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3852 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3853 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3854 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3855 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3856
3857 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3858 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3859 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3860 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3861 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3862 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3863 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3864
3865 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3866 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3867 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3868 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3869 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3870 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3871 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3872
3873 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3874 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3875 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3876 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3877 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3878 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3879 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3880
3881 struct fw_tlstx_data_wr {
3882 __be32 op_to_immdlen;
3883 __be32 flowid_len16;
3884 __be32 plen;
3885 __be32 lsodisable_to_flags;
3886 __be32 r5;
3887 __be32 ctxloc_to_exp;
3888 __be16 mfs;
3889 __be16 adjustedplen_pkd;
3890 __be16 expinplenmax_pkd;
3891 u8 pdusinplenmax_pkd;
3892 u8 r10;
3893 };
3894
3895 #define FW_TLSTX_DATA_WR_OPCODE_S 24
3896 #define FW_TLSTX_DATA_WR_OPCODE_M 0xff
3897 #define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
3898 #define FW_TLSTX_DATA_WR_OPCODE_G(x) \
3899 (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
3900
3901 #define FW_TLSTX_DATA_WR_COMPL_S 21
3902 #define FW_TLSTX_DATA_WR_COMPL_M 0x1
3903 #define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S)
3904 #define FW_TLSTX_DATA_WR_COMPL_G(x) \
3905 (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
3906 #define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1U)
3907
3908 #define FW_TLSTX_DATA_WR_IMMDLEN_S 0
3909 #define FW_TLSTX_DATA_WR_IMMDLEN_M 0xff
3910 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
3911 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \
3912 (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
3913
3914 #define FW_TLSTX_DATA_WR_FLOWID_S 8
3915 #define FW_TLSTX_DATA_WR_FLOWID_M 0xfffff
3916 #define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
3917 #define FW_TLSTX_DATA_WR_FLOWID_G(x) \
3918 (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
3919
3920 #define FW_TLSTX_DATA_WR_LEN16_S 0
3921 #define FW_TLSTX_DATA_WR_LEN16_M 0xff
3922 #define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S)
3923 #define FW_TLSTX_DATA_WR_LEN16_G(x) \
3924 (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
3925
3926 #define FW_TLSTX_DATA_WR_LSODISABLE_S 31
3927 #define FW_TLSTX_DATA_WR_LSODISABLE_M 0x1
3928 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
3929 ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
3930 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
3931 (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
3932 #define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
3933
3934 #define FW_TLSTX_DATA_WR_ALIGNPLD_S 30
3935 #define FW_TLSTX_DATA_WR_ALIGNPLD_M 0x1
3936 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
3937 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \
3938 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
3939 #define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
3940
3941 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
3942 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
3943 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
3944 ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
3945 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
3946 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
3947 FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
3948 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
3949
3950 #define FW_TLSTX_DATA_WR_FLAGS_S 0
3951 #define FW_TLSTX_DATA_WR_FLAGS_M 0xfffffff
3952 #define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
3953 #define FW_TLSTX_DATA_WR_FLAGS_G(x) \
3954 (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
3955
3956 #define FW_TLSTX_DATA_WR_CTXLOC_S 30
3957 #define FW_TLSTX_DATA_WR_CTXLOC_M 0x3
3958 #define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
3959 #define FW_TLSTX_DATA_WR_CTXLOC_G(x) \
3960 (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
3961
3962 #define FW_TLSTX_DATA_WR_IVDSGL_S 29
3963 #define FW_TLSTX_DATA_WR_IVDSGL_M 0x1
3964 #define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
3965 #define FW_TLSTX_DATA_WR_IVDSGL_G(x) \
3966 (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
3967 #define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1U)
3968
3969 #define FW_TLSTX_DATA_WR_KEYSIZE_S 24
3970 #define FW_TLSTX_DATA_WR_KEYSIZE_M 0x1f
3971 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
3972 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \
3973 (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
3974
3975 #define FW_TLSTX_DATA_WR_NUMIVS_S 14
3976 #define FW_TLSTX_DATA_WR_NUMIVS_M 0xff
3977 #define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
3978 #define FW_TLSTX_DATA_WR_NUMIVS_G(x) \
3979 (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
3980
3981 #define FW_TLSTX_DATA_WR_EXP_S 0
3982 #define FW_TLSTX_DATA_WR_EXP_M 0x3fff
3983 #define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S)
3984 #define FW_TLSTX_DATA_WR_EXP_G(x) \
3985 (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
3986
3987 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
3988 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
3989 ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
3990
3991 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
3992 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
3993 ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
3994
3995 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
3996 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
3997 ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
3998
3999 #endif /* _T4FW_INTERFACE_H_ */
Linux with added FPC-III support