?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
rtc: stm32: fix misspelling and misalignment issues
[linux/fpc-iii.git] / drivers / net / ethernet / stmicro / stmmac / dwmac1000_core.c
blobef10baf14186267a4c7cd11602258f3ec893b77d
1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
4 developing this code.
5
6 This only implements the mac core functions for this chip.
7
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
9
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
13
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24
25 #include <linux/crc32.h>
26 #include <linux/slab.h>
27 #include <linux/ethtool.h>
28 #include <net/dsa.h>
29 #include <asm/io.h>
30 #include "stmmac_pcs.h"
31 #include "dwmac1000.h"
32
33 static void dwmac1000_core_init(struct mac_device_info *hw,
34 struct net_device *dev)
35 {
36 void __iomem *ioaddr = hw->pcsr;
37 u32 value = readl(ioaddr + GMAC_CONTROL);
38 int mtu = dev->mtu;
39
40 /* Configure GMAC core */
41 value |= GMAC_CORE_INIT;
42
43 /* Clear ACS bit because Ethernet switch tagging formats such as
44 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
45 * hardware to truncate packets on reception.
46 */
47 if (netdev_uses_dsa(dev))
48 value &= ~GMAC_CONTROL_ACS;
49
50 if (mtu > 1500)
51 value |= GMAC_CONTROL_2K;
52 if (mtu > 2000)
53 value |= GMAC_CONTROL_JE;
54
55 if (hw->ps) {
56 value |= GMAC_CONTROL_TE;
57
58 value &= ~hw->link.speed_mask;
59 switch (hw->ps) {
60 case SPEED_1000:
61 value |= hw->link.speed1000;
62 break;
63 case SPEED_100:
64 value |= hw->link.speed100;
65 break;
66 case SPEED_10:
67 value |= hw->link.speed10;
68 break;
69 }
70 }
71
72 writel(value, ioaddr + GMAC_CONTROL);
73
74 /* Mask GMAC interrupts */
75 value = GMAC_INT_DEFAULT_MASK;
76
77 if (hw->pcs)
78 value &= ~GMAC_INT_DISABLE_PCS;
79
80 writel(value, ioaddr + GMAC_INT_MASK);
81
82 #ifdef STMMAC_VLAN_TAG_USED
83 /* Tag detection without filtering */
84 writel(0x0, ioaddr + GMAC_VLAN_TAG);
85 #endif
86 }
87
88 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
89 {
90 void __iomem *ioaddr = hw->pcsr;
91 u32 value = readl(ioaddr + GMAC_CONTROL);
92
93 if (hw->rx_csum)
94 value |= GMAC_CONTROL_IPC;
95 else
96 value &= ~GMAC_CONTROL_IPC;
97
98 writel(value, ioaddr + GMAC_CONTROL);
99
100 value = readl(ioaddr + GMAC_CONTROL);
101
102 return !!(value & GMAC_CONTROL_IPC);
103 }
104
105 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
106 {
107 void __iomem *ioaddr = hw->pcsr;
108 int i;
109
110 for (i = 0; i < 55; i++)
111 reg_space[i] = readl(ioaddr + i * 4);
112 }
113
114 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
115 unsigned char *addr,
116 unsigned int reg_n)
117 {
118 void __iomem *ioaddr = hw->pcsr;
119 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
120 GMAC_ADDR_LOW(reg_n));
121 }
122
123 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
124 unsigned char *addr,
125 unsigned int reg_n)
126 {
127 void __iomem *ioaddr = hw->pcsr;
128 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
129 GMAC_ADDR_LOW(reg_n));
130 }
131
132 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
133 int mcbitslog2)
134 {
135 int numhashregs, regs;
136
137 switch (mcbitslog2) {
138 case 6:
139 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
140 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
141 return;
142 break;
143 case 7:
144 numhashregs = 4;
145 break;
146 case 8:
147 numhashregs = 8;
148 break;
149 default:
150 pr_debug("STMMAC: err in setting multicast filter\n");
151 return;
152 break;
153 }
154 for (regs = 0; regs < numhashregs; regs++)
155 writel(mcfilterbits[regs],
156 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
157 }
158
159 static void dwmac1000_set_filter(struct mac_device_info *hw,
160 struct net_device *dev)
161 {
162 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
163 unsigned int value = 0;
164 unsigned int perfect_addr_number = hw->unicast_filter_entries;
165 u32 mc_filter[8];
166 int mcbitslog2 = hw->mcast_bits_log2;
167
168 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
169 netdev_mc_count(dev), netdev_uc_count(dev));
170
171 memset(mc_filter, 0, sizeof(mc_filter));
172
173 if (dev->flags & IFF_PROMISC) {
174 value = GMAC_FRAME_FILTER_PR;
175 } else if (dev->flags & IFF_ALLMULTI) {
176 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
177 } else if (!netdev_mc_empty(dev)) {
178 struct netdev_hw_addr *ha;
179
180 /* Hash filter for multicast */
181 value = GMAC_FRAME_FILTER_HMC;
182
183 netdev_for_each_mc_addr(ha, dev) {
184 /* The upper n bits of the calculated CRC are used to
185 * index the contents of the hash table. The number of
186 * bits used depends on the hardware configuration
187 * selected at core configuration time.
188 */
189 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
190 ETH_ALEN)) >>
191 (32 - mcbitslog2);
192 /* The most significant bit determines the register to
193 * use (H/L) while the other 5 bits determine the bit
194 * within the register.
195 */
196 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
197 }
198 }
199
200 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
201
202 /* Handle multiple unicast addresses (perfect filtering) */
203 if (netdev_uc_count(dev) > perfect_addr_number)
204 /* Switch to promiscuous mode if more than unicast
205 * addresses are requested than supported by hardware.
206 */
207 value |= GMAC_FRAME_FILTER_PR;
208 else {
209 int reg = 1;
210 struct netdev_hw_addr *ha;
211
212 netdev_for_each_uc_addr(ha, dev) {
213 stmmac_set_mac_addr(ioaddr, ha->addr,
214 GMAC_ADDR_HIGH(reg),
215 GMAC_ADDR_LOW(reg));
216 reg++;
217 }
218 }
219
220 #ifdef FRAME_FILTER_DEBUG
221 /* Enable Receive all mode (to debug filtering_fail errors) */
222 value |= GMAC_FRAME_FILTER_RA;
223 #endif
224 writel(value, ioaddr + GMAC_FRAME_FILTER);
225 }
226
227
228 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
229 unsigned int fc, unsigned int pause_time,
230 u32 tx_cnt)
231 {
232 void __iomem *ioaddr = hw->pcsr;
233 /* Set flow such that DZPQ in Mac Register 6 is 0,
234 * and unicast pause detect is enabled.
235 */
236 unsigned int flow = GMAC_FLOW_CTRL_UP;
237
238 pr_debug("GMAC Flow-Control:\n");
239 if (fc & FLOW_RX) {
240 pr_debug("\tReceive Flow-Control ON\n");
241 flow |= GMAC_FLOW_CTRL_RFE;
242 }
243 if (fc & FLOW_TX) {
244 pr_debug("\tTransmit Flow-Control ON\n");
245 flow |= GMAC_FLOW_CTRL_TFE;
246 }
247
248 if (duplex) {
249 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
250 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
251 }
252
253 writel(flow, ioaddr + GMAC_FLOW_CTRL);
254 }
255
256 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
257 {
258 void __iomem *ioaddr = hw->pcsr;
259 unsigned int pmt = 0;
260
261 if (mode & WAKE_MAGIC) {
262 pr_debug("GMAC: WOL Magic frame\n");
263 pmt |= power_down | magic_pkt_en;
264 }
265 if (mode & WAKE_UCAST) {
266 pr_debug("GMAC: WOL on global unicast\n");
267 pmt |= power_down | global_unicast | wake_up_frame_en;
268 }
269
270 writel(pmt, ioaddr + GMAC_PMT);
271 }
272
273 /* RGMII or SMII interface */
274 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
275 {
276 u32 status;
277
278 status = readl(ioaddr + GMAC_RGSMIIIS);
279 x->irq_rgmii_n++;
280
281 /* Check the link status */
282 if (status & GMAC_RGSMIIIS_LNKSTS) {
283 int speed_value;
284
285 x->pcs_link = 1;
286
287 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
288 GMAC_RGSMIIIS_SPEED_SHIFT);
289 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
290 x->pcs_speed = SPEED_1000;
291 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
292 x->pcs_speed = SPEED_100;
293 else
294 x->pcs_speed = SPEED_10;
295
296 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
297
298 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
299 x->pcs_duplex ? "Full" : "Half");
300 } else {
301 x->pcs_link = 0;
302 pr_info("Link is Down\n");
303 }
304 }
305
306 static int dwmac1000_irq_status(struct mac_device_info *hw,
307 struct stmmac_extra_stats *x)
308 {
309 void __iomem *ioaddr = hw->pcsr;
310 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
311 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
312 int ret = 0;
313
314 /* Discard masked bits */
315 intr_status &= ~intr_mask;
316
317 /* Not used events (e.g. MMC interrupts) are not handled. */
318 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
319 x->mmc_tx_irq_n++;
320 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
321 x->mmc_rx_irq_n++;
322 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
323 x->mmc_rx_csum_offload_irq_n++;
324 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
325 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
326 readl(ioaddr + GMAC_PMT);
327 x->irq_receive_pmt_irq_n++;
328 }
329
330 /* MAC tx/rx EEE LPI entry/exit interrupts */
331 if (intr_status & GMAC_INT_STATUS_LPIIS) {
332 /* Clean LPI interrupt by reading the Reg 12 */
333 ret = readl(ioaddr + LPI_CTRL_STATUS);
334
335 if (ret & LPI_CTRL_STATUS_TLPIEN)
336 x->irq_tx_path_in_lpi_mode_n++;
337 if (ret & LPI_CTRL_STATUS_TLPIEX)
338 x->irq_tx_path_exit_lpi_mode_n++;
339 if (ret & LPI_CTRL_STATUS_RLPIEN)
340 x->irq_rx_path_in_lpi_mode_n++;
341 if (ret & LPI_CTRL_STATUS_RLPIEX)
342 x->irq_rx_path_exit_lpi_mode_n++;
343 }
344
345 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
346
347 if (intr_status & PCS_RGSMIIIS_IRQ)
348 dwmac1000_rgsmii(ioaddr, x);
349
350 return ret;
351 }
352
353 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
354 bool en_tx_lpi_clockgating)
355 {
356 void __iomem *ioaddr = hw->pcsr;
357 u32 value;
358
359 /*TODO - en_tx_lpi_clockgating treatment */
360
361 /* Enable the link status receive on RGMII, SGMII ore SMII
362 * receive path and instruct the transmit to enter in LPI
363 * state.
364 */
365 value = readl(ioaddr + LPI_CTRL_STATUS);
366 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
367 writel(value, ioaddr + LPI_CTRL_STATUS);
368 }
369
370 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
371 {
372 void __iomem *ioaddr = hw->pcsr;
373 u32 value;
374
375 value = readl(ioaddr + LPI_CTRL_STATUS);
376 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
377 writel(value, ioaddr + LPI_CTRL_STATUS);
378 }
379
380 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
381 {
382 void __iomem *ioaddr = hw->pcsr;
383 u32 value;
384
385 value = readl(ioaddr + LPI_CTRL_STATUS);
386
387 if (link)
388 value |= LPI_CTRL_STATUS_PLS;
389 else
390 value &= ~LPI_CTRL_STATUS_PLS;
391
392 writel(value, ioaddr + LPI_CTRL_STATUS);
393 }
394
395 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
396 {
397 void __iomem *ioaddr = hw->pcsr;
398 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
399
400 /* Program the timers in the LPI timer control register:
401 * LS: minimum time (ms) for which the link
402 * status from PHY should be ok before transmitting
403 * the LPI pattern.
404 * TW: minimum time (us) for which the core waits
405 * after it has stopped transmitting the LPI pattern.
406 */
407 writel(value, ioaddr + LPI_TIMER_CTRL);
408 }
409
410 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
411 bool loopback)
412 {
413 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
414 }
415
416 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
417 {
418 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
419 }
420
421 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
422 {
423 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
424 }
425
426 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
427 u32 rx_queues, u32 tx_queues)
428 {
429 u32 value = readl(ioaddr + GMAC_DEBUG);
430
431 if (value & GMAC_DEBUG_TXSTSFSTS)
432 x->mtl_tx_status_fifo_full++;
433 if (value & GMAC_DEBUG_TXFSTS)
434 x->mtl_tx_fifo_not_empty++;
435 if (value & GMAC_DEBUG_TWCSTS)
436 x->mmtl_fifo_ctrl++;
437 if (value & GMAC_DEBUG_TRCSTS_MASK) {
438 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
439 >> GMAC_DEBUG_TRCSTS_SHIFT;
440 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
441 x->mtl_tx_fifo_read_ctrl_write++;
442 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
443 x->mtl_tx_fifo_read_ctrl_wait++;
444 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
445 x->mtl_tx_fifo_read_ctrl_read++;
446 else
447 x->mtl_tx_fifo_read_ctrl_idle++;
448 }
449 if (value & GMAC_DEBUG_TXPAUSED)
450 x->mac_tx_in_pause++;
451 if (value & GMAC_DEBUG_TFCSTS_MASK) {
452 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
453 >> GMAC_DEBUG_TFCSTS_SHIFT;
454
455 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
456 x->mac_tx_frame_ctrl_xfer++;
457 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
458 x->mac_tx_frame_ctrl_pause++;
459 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
460 x->mac_tx_frame_ctrl_wait++;
461 else
462 x->mac_tx_frame_ctrl_idle++;
463 }
464 if (value & GMAC_DEBUG_TPESTS)
465 x->mac_gmii_tx_proto_engine++;
466 if (value & GMAC_DEBUG_RXFSTS_MASK) {
467 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
468 >> GMAC_DEBUG_RRCSTS_SHIFT;
469
470 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
471 x->mtl_rx_fifo_fill_level_full++;
472 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
473 x->mtl_rx_fifo_fill_above_thresh++;
474 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
475 x->mtl_rx_fifo_fill_below_thresh++;
476 else
477 x->mtl_rx_fifo_fill_level_empty++;
478 }
479 if (value & GMAC_DEBUG_RRCSTS_MASK) {
480 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
481 GMAC_DEBUG_RRCSTS_SHIFT;
482
483 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
484 x->mtl_rx_fifo_read_ctrl_flush++;
485 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
486 x->mtl_rx_fifo_read_ctrl_read_data++;
487 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
488 x->mtl_rx_fifo_read_ctrl_status++;
489 else
490 x->mtl_rx_fifo_read_ctrl_idle++;
491 }
492 if (value & GMAC_DEBUG_RWCSTS)
493 x->mtl_rx_fifo_ctrl_active++;
494 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
495 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
496 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
497 if (value & GMAC_DEBUG_RPESTS)
498 x->mac_gmii_rx_proto_engine++;
499 }
500
501 static const struct stmmac_ops dwmac1000_ops = {
502 .core_init = dwmac1000_core_init,
503 .set_mac = stmmac_set_mac,
504 .rx_ipc = dwmac1000_rx_ipc_enable,
505 .dump_regs = dwmac1000_dump_regs,
506 .host_irq_status = dwmac1000_irq_status,
507 .set_filter = dwmac1000_set_filter,
508 .flow_ctrl = dwmac1000_flow_ctrl,
509 .pmt = dwmac1000_pmt,
510 .set_umac_addr = dwmac1000_set_umac_addr,
511 .get_umac_addr = dwmac1000_get_umac_addr,
512 .set_eee_mode = dwmac1000_set_eee_mode,
513 .reset_eee_mode = dwmac1000_reset_eee_mode,
514 .set_eee_timer = dwmac1000_set_eee_timer,
515 .set_eee_pls = dwmac1000_set_eee_pls,
516 .debug = dwmac1000_debug,
517 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
518 .pcs_rane = dwmac1000_rane,
519 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
520 };
521
522 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
523 int perfect_uc_entries,
524 int *synopsys_id)
525 {
526 struct mac_device_info *mac;
527 u32 hwid = readl(ioaddr + GMAC_VERSION);
528
529 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
530 if (!mac)
531 return NULL;
532
533 mac->pcsr = ioaddr;
534 mac->multicast_filter_bins = mcbins;
535 mac->unicast_filter_entries = perfect_uc_entries;
536 mac->mcast_bits_log2 = 0;
537
538 if (mac->multicast_filter_bins)
539 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
540
541 mac->mac = &dwmac1000_ops;
542 mac->dma = &dwmac1000_dma_ops;
543
544 mac->link.duplex = GMAC_CONTROL_DM;
545 mac->link.speed10 = GMAC_CONTROL_PS;
546 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
547 mac->link.speed1000 = 0;
548 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
549 mac->mii.addr = GMAC_MII_ADDR;
550 mac->mii.data = GMAC_MII_DATA;
551 mac->mii.addr_shift = 11;
552 mac->mii.addr_mask = 0x0000F800;
553 mac->mii.reg_shift = 6;
554 mac->mii.reg_mask = 0x000007C0;
555 mac->mii.clk_csr_shift = 2;
556 mac->mii.clk_csr_mask = GENMASK(5, 2);
557
558 /* Get and dump the chip ID */
559 *synopsys_id = stmmac_get_synopsys_id(hwid);
560
561 return mac;
562 }
Linux with added FPC-III support