x86/boot: Rename overlapping memcpy() to memmove()
[linux/fpc-iii.git] / arch / arm / mach-s3c24xx / include / mach / map.h
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1 /* arch/arm/mach-s3c2410/include/mach/map.h
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 - Memory map definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_MAP_H
14 #define __ASM_ARCH_MAP_H
16 #include <plat/map-base.h>
17 #include <plat/map-s3c.h>
20 * interrupt controller is the first thing we put in, to make
21 * the assembly code for the irq detection easier
23 #define S3C2410_PA_IRQ (0x4A000000)
24 #define S3C24XX_SZ_IRQ SZ_1M
26 /* memory controller registers */
27 #define S3C2410_PA_MEMCTRL (0x48000000)
28 #define S3C24XX_SZ_MEMCTRL SZ_1M
30 /* Timers */
31 #define S3C2410_PA_TIMER (0x51000000)
32 #define S3C24XX_SZ_TIMER SZ_1M
34 /* Clock and Power management */
35 #define S3C24XX_SZ_CLKPWR SZ_1M
37 /* USB Device port */
38 #define S3C2410_PA_USBDEV (0x52000000)
39 #define S3C24XX_SZ_USBDEV SZ_1M
41 /* Watchdog */
42 #define S3C2410_PA_WATCHDOG (0x53000000)
43 #define S3C24XX_SZ_WATCHDOG SZ_1M
45 /* Standard size definitions for peripheral blocks. */
47 #define S3C24XX_SZ_UART SZ_1M
48 #define S3C24XX_SZ_IIS SZ_1M
49 #define S3C24XX_SZ_ADC SZ_1M
50 #define S3C24XX_SZ_SPI SZ_1M
51 #define S3C24XX_SZ_SDI SZ_1M
52 #define S3C24XX_SZ_NAND SZ_1M
53 #define S3C24XX_SZ_GPIO SZ_1M
55 /* USB host controller */
56 #define S3C2410_PA_USBHOST (0x49000000)
58 /* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
59 #define S3C2416_PA_HSUDC (0x49800000)
60 #define S3C2416_SZ_HSUDC (SZ_4K)
62 /* DMA controller */
63 #define S3C2410_PA_DMA (0x4B000000)
64 #define S3C24XX_SZ_DMA SZ_1M
66 /* Clock and Power management */
67 #define S3C2410_PA_CLKPWR (0x4C000000)
69 /* LCD controller */
70 #define S3C2410_PA_LCD (0x4D000000)
71 #define S3C24XX_SZ_LCD SZ_1M
73 /* NAND flash controller */
74 #define S3C2410_PA_NAND (0x4E000000)
76 /* IIC hardware controller */
77 #define S3C2410_PA_IIC (0x54000000)
79 /* IIS controller */
80 #define S3C2410_PA_IIS (0x55000000)
82 /* RTC */
83 #define S3C2410_PA_RTC (0x57000000)
84 #define S3C24XX_SZ_RTC SZ_1M
86 /* ADC */
87 #define S3C2410_PA_ADC (0x58000000)
89 /* SPI */
90 #define S3C2410_PA_SPI (0x59000000)
91 #define S3C2443_PA_SPI0 (0x52000000)
92 #define S3C2443_PA_SPI1 S3C2410_PA_SPI
94 /* SDI */
95 #define S3C2410_PA_SDI (0x5A000000)
97 /* CAMIF */
98 #define S3C2440_PA_CAMIF (0x4F000000)
99 #define S3C2440_SZ_CAMIF SZ_1M
101 /* AC97 */
103 #define S3C2440_PA_AC97 (0x5B000000)
104 #define S3C2440_SZ_AC97 SZ_1M
106 /* S3C2443/S3C2416 High-speed SD/MMC */
107 #define S3C2443_PA_HSMMC (0x4A800000)
108 #define S3C2416_PA_HSMMC0 (0x4AC00000)
110 #define S3C2443_PA_FB (0x4C800000)
112 /* S3C2412 memory and IO controls */
113 #define S3C2412_PA_SSMC (0x4F000000)
115 #define S3C2412_PA_EBI (0x48800000)
117 /* physical addresses of all the chip-select areas */
119 #define S3C2410_CS0 (0x00000000)
120 #define S3C2410_CS1 (0x08000000)
121 #define S3C2410_CS2 (0x10000000)
122 #define S3C2410_CS3 (0x18000000)
123 #define S3C2410_CS4 (0x20000000)
124 #define S3C2410_CS5 (0x28000000)
125 #define S3C2410_CS6 (0x30000000)
126 #define S3C2410_CS7 (0x38000000)
128 #define S3C2410_SDRAM_PA (S3C2410_CS6)
130 /* Use a single interface for common resources between S3C24XX cpus */
132 #define S3C24XX_PA_IRQ S3C2410_PA_IRQ
133 #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
134 #define S3C24XX_PA_DMA S3C2410_PA_DMA
135 #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
136 #define S3C24XX_PA_LCD S3C2410_PA_LCD
137 #define S3C24XX_PA_TIMER S3C2410_PA_TIMER
138 #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
139 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
140 #define S3C24XX_PA_IIS S3C2410_PA_IIS
141 #define S3C24XX_PA_RTC S3C2410_PA_RTC
142 #define S3C24XX_PA_ADC S3C2410_PA_ADC
143 #define S3C24XX_PA_SPI S3C2410_PA_SPI
144 #define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1)
145 #define S3C24XX_PA_SDI S3C2410_PA_SDI
146 #define S3C24XX_PA_NAND S3C2410_PA_NAND
148 #define S3C_PA_FB S3C2443_PA_FB
149 #define S3C_PA_IIC S3C2410_PA_IIC
150 #define S3C_PA_USBHOST S3C2410_PA_USBHOST
151 #define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
152 #define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
153 #define S3C_PA_WDT S3C2410_PA_WATCHDOG
154 #define S3C_PA_NAND S3C24XX_PA_NAND
156 #define S3C_PA_SPI0 S3C2443_PA_SPI0
157 #define S3C_PA_SPI1 S3C2443_PA_SPI1
159 #define SAMSUNG_PA_TIMER S3C2410_PA_TIMER
161 #endif /* __ASM_ARCH_MAP_H */