x86/boot: Rename overlapping memcpy() to memmove()
[linux/fpc-iii.git] / arch / arm / mach-s3c64xx / include / mach / pm-core.h
blob4a285e97afff3dbaeecdcec9fa725e3c329c79b1
1 /* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #ifndef __MACH_S3C64XX_PM_CORE_H
16 #define __MACH_S3C64XX_PM_CORE_H __FILE__
18 #include <linux/serial_s3c.h>
19 #include <linux/delay.h>
21 #include <mach/regs-gpio.h>
22 #include <mach/regs-clock.h>
23 #include <mach/map.h>
25 static inline void s3c_pm_debug_init_uart(void)
27 u32 tmp = __raw_readl(S3C_PCLK_GATE);
29 /* As a note, since the S3C64XX UARTs generally have multiple
30 * clock sources, we simply enable PCLK at the moment and hope
31 * that the resume settings for the UART are suitable for the
32 * use with PCLK.
35 tmp |= S3C_CLKCON_PCLK_UART0;
36 tmp |= S3C_CLKCON_PCLK_UART1;
37 tmp |= S3C_CLKCON_PCLK_UART2;
38 tmp |= S3C_CLKCON_PCLK_UART3;
40 __raw_writel(tmp, S3C_PCLK_GATE);
41 udelay(10);
44 static inline void s3c_pm_arch_prepare_irqs(void)
46 /* VIC should have already been taken care of */
48 /* clear any pending EINT0 interrupts */
49 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
52 static inline void s3c_pm_arch_stop_clocks(void)
56 static inline void s3c_pm_arch_show_resume_irqs(void)
60 /* make these defines, we currently do not have any need to change
61 * the IRQ wake controls depending on the CPU we are running on */
62 #ifdef CONFIG_PM_SLEEP
63 #define s3c_irqwake_eintallow ((1 << 28) - 1)
64 #define s3c_irqwake_intallow (~0)
65 #else
66 #define s3c_irqwake_eintallow 0
67 #define s3c_irqwake_intallow 0
68 #endif
70 static inline void s3c_pm_arch_update_uart(void __iomem *regs,
71 struct pm_uart_save *save)
73 u32 ucon = __raw_readl(regs + S3C2410_UCON);
74 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
75 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
76 u32 new_ucon;
77 u32 delta;
79 /* S3C64XX UART blocks only support level interrupts, so ensure that
80 * when we restore unused UART blocks we force the level interrupt
81 * settigs. */
82 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
84 /* We have a constraint on changing the clock type of the UART
85 * between UCLKx and PCLK, so ensure that when we restore UCON
86 * that the CLK field is correctly modified if the bootloader
87 * has changed anything.
89 if (ucon_clk != save_clk) {
90 new_ucon = save->ucon;
91 delta = ucon_clk ^ save_clk;
93 /* change from UCLKx => wrong PCLK,
94 * either UCLK can be tested for by a bit-test
95 * with UCLK0 */
96 if (ucon_clk & S3C6400_UCON_UCLK0 &&
97 !(save_clk & S3C6400_UCON_UCLK0) &&
98 delta & S3C6400_UCON_PCLK2) {
99 new_ucon &= ~S3C6400_UCON_UCLK0;
100 } else if (delta == S3C6400_UCON_PCLK2) {
101 /* as an precaution, don't change from
102 * PCLK2 => PCLK or vice-versa */
103 new_ucon ^= S3C6400_UCON_PCLK2;
106 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
107 ucon, new_ucon, save->ucon);
108 save->ucon = new_ucon;
112 static inline void s3c_pm_restored_gpios(void)
114 /* ensure sleep mode has been cleared from the system */
116 __raw_writel(0, S3C64XX_SLPEN);
119 static inline void samsung_pm_saved_gpios(void)
121 /* turn on the sleep mode and keep it there, as it seems that during
122 * suspend the xCON registers get re-set and thus you can end up with
123 * problems between going to sleep and resuming.
126 __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
128 #endif /* __MACH_S3C64XX_PM_CORE_H */