arch/mips/pci/pci-rt3883.c

   1 /*
   2  *  Ralink RT3662/RT3883 SoC PCI support
   3  *
   4  *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/pci.h>
  15 #include <linux/io.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_pci.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <asm/mach-ralink/rt3883.h>
  26 #include <asm/mach-ralink/ralink_regs.h>
  27
  28 #define RT3883_MEMORY_BASE              0x00000000
  29 #define RT3883_MEMORY_SIZE              0x02000000
  30
  31 #define RT3883_PCI_REG_PCICFG           0x00
  32 #define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  33 #define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  34 #define   RT3883_PCICFG_PCIRST          BIT(1)
  35 #define RT3883_PCI_REG_PCIRAW           0x04
  36 #define RT3883_PCI_REG_PCIINT           0x08
  37 #define RT3883_PCI_REG_PCIENA           0x0c
  38
  39 #define RT3883_PCI_REG_CFGADDR          0x20
  40 #define RT3883_PCI_REG_CFGDATA          0x24
  41 #define RT3883_PCI_REG_MEMBASE          0x28
  42 #define RT3883_PCI_REG_IOBASE           0x2c
  43 #define RT3883_PCI_REG_ARBCTL           0x80
  44
  45 #define RT3883_PCI_REG_BASE(_x)         (0x1000 + (_x) * 0x1000)
  46 #define RT3883_PCI_REG_BAR0SETUP(_x)    (RT3883_PCI_REG_BASE((_x)) + 0x10)
  47 #define RT3883_PCI_REG_IMBASEBAR0(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x18)
  48 #define RT3883_PCI_REG_ID(_x)           (RT3883_PCI_REG_BASE((_x)) + 0x30)
  49 #define RT3883_PCI_REG_CLASS(_x)        (RT3883_PCI_REG_BASE((_x)) + 0x34)
  50 #define RT3883_PCI_REG_SUBID(_x)        (RT3883_PCI_REG_BASE((_x)) + 0x38)
  51 #define RT3883_PCI_REG_STATUS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x50)
  52
  53 #define RT3883_PCI_MODE_NONE    0
  54 #define RT3883_PCI_MODE_PCI     BIT(0)
  55 #define RT3883_PCI_MODE_PCIE    BIT(1)
  56 #define RT3883_PCI_MODE_BOTH    (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  57
  58 #define RT3883_PCI_IRQ_COUNT    32
  59
  60 #define RT3883_P2P_BR_DEVNUM    1
  61
  62 struct rt3883_pci_controller {
  63         void __iomem *base;
  64
  65         struct device_node *intc_of_node;
  66         struct irq_domain *irq_domain;
  67
  68         struct pci_controller pci_controller;
  69         struct resource io_res;
  70         struct resource mem_res;
  71
  72         bool pcie_ready;
  73 };
  74
  75 static inline struct rt3883_pci_controller *
  76 pci_bus_to_rt3883_controller(struct pci_bus *bus)
  77 {
  78         struct pci_controller *hose;
  79
  80         hose = (struct pci_controller *) bus->sysdata;
  81         return container_of(hose, struct rt3883_pci_controller, pci_controller);
  82 }
  83
  84 static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
  85                                  unsigned reg)
  86 {
  87         return ioread32(rpc->base + reg);
  88 }
  89
  90 static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
  91                                   u32 val, unsigned reg)
  92 {
  93         iowrite32(val, rpc->base + reg);
  94 }
  95
  96 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  97                                          unsigned int func, unsigned int where)
  98 {
  99         return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
 100                0x80000000;
 101 }
 102
 103 static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 104                                unsigned bus, unsigned slot,
 105                                unsigned func, unsigned reg)
 106 {
 107         unsigned long flags;
 108         u32 address;
 109         u32 ret;
 110
 111         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 112
 113         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 114         ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 115
 116         return ret;
 117 }
 118
 119 static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 120                                  unsigned bus, unsigned slot,
 121                                  unsigned func, unsigned reg, u32 val)
 122 {
 123         unsigned long flags;
 124         u32 address;
 125
 126         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 127
 128         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 129         rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
 130 }
 131
 132 static void rt3883_pci_irq_handler(struct irq_desc *desc)
 133 {
 134         struct rt3883_pci_controller *rpc;
 135         u32 pending;
 136
 137         rpc = irq_desc_get_handler_data(desc);
 138
 139         pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
 140                   rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 141
 142         if (!pending) {
 143                 spurious_interrupt();
 144                 return;
 145         }
 146
 147         while (pending) {
 148                 unsigned irq, bit = __ffs(pending);
 149
 150                 irq = irq_find_mapping(rpc->irq_domain, bit);
 151                 generic_handle_irq(irq);
 152
 153                 pending &= ~BIT(bit);
 154         }
 155 }
 156
 157 static void rt3883_pci_irq_unmask(struct irq_data *d)
 158 {
 159         struct rt3883_pci_controller *rpc;
 160         u32 t;
 161
 162         rpc = irq_data_get_irq_chip_data(d);
 163
 164         t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 165         rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 166         /* flush write */
 167         rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 168 }
 169
 170 static void rt3883_pci_irq_mask(struct irq_data *d)
 171 {
 172         struct rt3883_pci_controller *rpc;
 173         u32 t;
 174
 175         rpc = irq_data_get_irq_chip_data(d);
 176
 177         t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 178         rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 179         /* flush write */
 180         rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 181 }
 182
 183 static struct irq_chip rt3883_pci_irq_chip = {
 184         .name           = "RT3883 PCI",
 185         .irq_mask       = rt3883_pci_irq_mask,
 186         .irq_unmask     = rt3883_pci_irq_unmask,
 187         .irq_mask_ack   = rt3883_pci_irq_mask,
 188 };
 189
 190 static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
 191                               irq_hw_number_t hw)
 192 {
 193         irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
 194         irq_set_chip_data(irq, d->host_data);
 195
 196         return 0;
 197 }
 198
 199 static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
 200         .map = rt3883_pci_irq_map,
 201         .xlate = irq_domain_xlate_onecell,
 202 };
 203
 204 static int rt3883_pci_irq_init(struct device *dev,
 205                                struct rt3883_pci_controller *rpc)
 206 {
 207         int irq;
 208
 209         irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
 210         if (irq == 0) {
 211                 dev_err(dev, "%s has no IRQ",
 212                         of_node_full_name(rpc->intc_of_node));
 213                 return -EINVAL;
 214         }
 215
 216         /* disable all interrupts */
 217         rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 218
 219         rpc->irq_domain =
 220                 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
 221                                       &rt3883_pci_irq_domain_ops,
 222                                       rpc);
 223         if (!rpc->irq_domain) {
 224                 dev_err(dev, "unable to add IRQ domain\n");
 225                 return -ENODEV;
 226         }
 227
 228         irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
 229
 230         return 0;
 231 }
 232
 233 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 234                                   int where, int size, u32 *val)
 235 {
 236         struct rt3883_pci_controller *rpc;
 237         unsigned long flags;
 238         u32 address;
 239         u32 data;
 240
 241         rpc = pci_bus_to_rt3883_controller(bus);
 242
 243         if (!rpc->pcie_ready && bus->number == 1)
 244                 return PCIBIOS_DEVICE_NOT_FOUND;
 245
 246         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 247                                          PCI_FUNC(devfn), where);
 248
 249         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 250         data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 251
 252         switch (size) {
 253         case 1:
 254                 *val = (data >> ((where & 3) << 3)) & 0xff;
 255                 break;
 256         case 2:
 257                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 258                 break;
 259         case 4:
 260                 *val = data;
 261                 break;
 262         }
 263
 264         return PCIBIOS_SUCCESSFUL;
 265 }
 266
 267 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 268                                    int where, int size, u32 val)
 269 {
 270         struct rt3883_pci_controller *rpc;
 271         unsigned long flags;
 272         u32 address;
 273         u32 data;
 274
 275         rpc = pci_bus_to_rt3883_controller(bus);
 276
 277         if (!rpc->pcie_ready && bus->number == 1)
 278                 return PCIBIOS_DEVICE_NOT_FOUND;
 279
 280         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 281                                          PCI_FUNC(devfn), where);
 282
 283         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 284         data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 285
 286         switch (size) {
 287         case 1:
 288                 data = (data & ~(0xff << ((where & 3) << 3))) |
 289                        (val << ((where & 3) << 3));
 290                 break;
 291         case 2:
 292                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 293                        (val << ((where & 3) << 3));
 294                 break;
 295         case 4:
 296                 data = val;
 297                 break;
 298         }
 299
 300         rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
 301
 302         return PCIBIOS_SUCCESSFUL;
 303 }
 304
 305 static struct pci_ops rt3883_pci_ops = {
 306         .read   = rt3883_pci_config_read,
 307         .write  = rt3883_pci_config_write,
 308 };
 309
 310 static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
 311 {
 312         u32 syscfg1;
 313         u32 rstctrl;
 314         u32 clkcfg1;
 315         u32 t;
 316
 317         rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 318         syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 319         clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 320
 321         if (mode & RT3883_PCI_MODE_PCIE) {
 322                 rstctrl |= RT3883_RSTCTRL_PCIE;
 323                 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 324
 325                 /* setup PCI PAD drive mode */
 326                 syscfg1 &= ~(0x30);
 327                 syscfg1 |= (2 << 4);
 328                 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 329
 330                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 331                 t &= ~BIT(31);
 332                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 333
 334                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 335                 t &= 0x80ffffff;
 336                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 337
 338                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 339                 t |= 0xa << 24;
 340                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 341
 342                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 343                 t |= BIT(31);
 344                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 345
 346                 msleep(50);
 347
 348                 rstctrl &= ~RT3883_RSTCTRL_PCIE;
 349                 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 350         }
 351
 352         syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
 353
 354         clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
 355
 356         if (mode & RT3883_PCI_MODE_PCI) {
 357                 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 358                 rstctrl &= ~RT3883_RSTCTRL_PCI;
 359         }
 360
 361         if (mode & RT3883_PCI_MODE_PCIE) {
 362                 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 363                 rstctrl &= ~RT3883_RSTCTRL_PCIE;
 364         }
 365
 366         rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 367         rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 368         rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 369
 370         msleep(500);
 371
 372         /*
 373          * setup the device number of the P2P bridge
 374          * and de-assert the reset line
 375          */
 376         t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
 377         rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
 378
 379         /* flush write */
 380         rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
 381         msleep(500);
 382
 383         if (mode & RT3883_PCI_MODE_PCIE) {
 384                 msleep(500);
 385
 386                 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
 387
 388                 rpc->pcie_ready = t & BIT(0);
 389
 390                 if (!rpc->pcie_ready) {
 391                         /* reset the PCIe block */
 392                         t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 393                         t |= RT3883_RSTCTRL_PCIE;
 394                         rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 395                         t &= ~RT3883_RSTCTRL_PCIE;
 396                         rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 397
 398                         /* turn off PCIe clock */
 399                         t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 400                         t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
 401                         rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 402
 403                         t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 404                         t &= ~0xf000c080;
 405                         rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 406                 }
 407         }
 408
 409         /* enable PCI arbiter */
 410         rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 411 }
 412
 413 static int rt3883_pci_probe(struct platform_device *pdev)
 414 {
 415         struct rt3883_pci_controller *rpc;
 416         struct device *dev = &pdev->dev;
 417         struct device_node *np = dev->of_node;
 418         struct resource *res;
 419         struct device_node *child;
 420         u32 val;
 421         int err;
 422         int mode;
 423
 424         rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 425         if (!rpc)
 426                 return -ENOMEM;
 427
 428         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 429         rpc->base = devm_ioremap_resource(dev, res);
 430         if (IS_ERR(rpc->base))
 431                 return PTR_ERR(rpc->base);
 432
 433         /* find the interrupt controller child node */
 434         for_each_child_of_node(np, child) {
 435                 if (of_get_property(child, "interrupt-controller", NULL)) {
 436                         rpc->intc_of_node = child;
 437                         break;
 438                 }
 439         }
 440
 441         if (!rpc->intc_of_node) {
 442                 dev_err(dev, "%s has no %s child node",
 443                         of_node_full_name(rpc->intc_of_node),
 444                         "interrupt controller");
 445                 return -EINVAL;
 446         }
 447
 448         /* find the PCI host bridge child node */
 449         for_each_child_of_node(np, child) {
 450                 if (child->type &&
 451                     of_node_cmp(child->type, "pci") == 0) {
 452                         rpc->pci_controller.of_node = child;
 453                         break;
 454                 }
 455         }
 456
 457         if (!rpc->pci_controller.of_node) {
 458                 dev_err(dev, "%s has no %s child node",
 459                         of_node_full_name(rpc->intc_of_node),
 460                         "PCI host bridge");
 461                 err = -EINVAL;
 462                 goto err_put_intc_node;
 463         }
 464
 465         mode = RT3883_PCI_MODE_NONE;
 466         for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
 467                 int devfn;
 468
 469                 if (!child->type ||
 470                     of_node_cmp(child->type, "pci") != 0)
 471                         continue;
 472
 473                 devfn = of_pci_get_devfn(child);
 474                 if (devfn < 0)
 475                         continue;
 476
 477                 switch (PCI_SLOT(devfn)) {
 478                 case 1:
 479                         mode |= RT3883_PCI_MODE_PCIE;
 480                         break;
 481
 482                 case 17:
 483                 case 18:
 484                         mode |= RT3883_PCI_MODE_PCI;
 485                         break;
 486                 }
 487         }
 488
 489         if (mode == RT3883_PCI_MODE_NONE) {
 490                 dev_err(dev, "unable to determine PCI mode\n");
 491                 err = -EINVAL;
 492                 goto err_put_hb_node;
 493         }
 494
 495         dev_info(dev, "mode:%s%s\n",
 496                  (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
 497                  (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
 498
 499         rt3883_pci_preinit(rpc, mode);
 500
 501         rpc->pci_controller.pci_ops = &rt3883_pci_ops;
 502         rpc->pci_controller.io_resource = &rpc->io_res;
 503         rpc->pci_controller.mem_resource = &rpc->mem_res;
 504
 505         /* Load PCI I/O and memory resources from DT */
 506         pci_load_of_ranges(&rpc->pci_controller,
 507                            rpc->pci_controller.of_node);
 508
 509         rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
 510         rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
 511
 512         ioport_resource.start = rpc->io_res.start;
 513         ioport_resource.end = rpc->io_res.end;
 514
 515         /* PCI */
 516         rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
 517         rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
 518         rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
 519         rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
 520         rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
 521
 522         /* PCIe */
 523         rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
 524         rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
 525         rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
 526         rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
 527         rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
 528
 529         err = rt3883_pci_irq_init(dev, rpc);
 530         if (err)
 531                 goto err_put_hb_node;
 532
 533         /* PCIe */
 534         val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
 535         val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 536         rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
 537
 538         /* PCI */
 539         val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
 540         val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 541         rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
 542
 543         if (mode == RT3883_PCI_MODE_PCIE) {
 544                 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
 545                 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
 546
 547                 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 548                                        PCI_BASE_ADDRESS_0,
 549                                        RT3883_MEMORY_BASE);
 550                 /* flush write */
 551                 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 552                                       PCI_BASE_ADDRESS_0);
 553         } else {
 554                 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 555                                        PCI_IO_BASE, 0x00000101);
 556         }
 557
 558         register_pci_controller(&rpc->pci_controller);
 559
 560         return 0;
 561
 562 err_put_hb_node:
 563         of_node_put(rpc->pci_controller.of_node);
 564 err_put_intc_node:
 565         of_node_put(rpc->intc_of_node);
 566         return err;
 567 }
 568
 569 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 570 {
 571         return of_irq_parse_and_map_pci(dev, slot, pin);
 572 }
 573
 574 int pcibios_plat_dev_init(struct pci_dev *dev)
 575 {
 576         return 0;
 577 }
 578
 579 static const struct of_device_id rt3883_pci_ids[] = {
 580         { .compatible = "ralink,rt3883-pci" },
 581         {},
 582 };
 583 MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
 584
 585 static struct platform_driver rt3883_pci_driver = {
 586         .probe = rt3883_pci_probe,
 587         .driver = {
 588                 .name = "rt3883-pci",
 589                 .of_match_table = of_match_ptr(rt3883_pci_ids),
 590         },
 591 };
 592
 593 static int __init rt3883_pci_init(void)
 594 {
 595         return platform_driver_register(&rt3883_pci_driver);
 596 }
 597
 598 postcore_initcall(rt3883_pci_init);