x86/boot: Rename overlapping memcpy() to memmove()
[linux/fpc-iii.git] / arch / mips / pci / pci-xlr.c
blob26d2dabef28152541b709b11d2257cb563fe0349
1 /*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/types.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/msi.h>
40 #include <linux/mm.h>
41 #include <linux/irq.h>
42 #include <linux/irqdesc.h>
43 #include <linux/console.h>
44 #include <linux/pci_regs.h>
46 #include <asm/io.h>
48 #include <asm/netlogic/interrupt.h>
49 #include <asm/netlogic/haldefs.h>
50 #include <asm/netlogic/common.h>
52 #include <asm/netlogic/xlr/msidef.h>
53 #include <asm/netlogic/xlr/iomap.h>
54 #include <asm/netlogic/xlr/pic.h>
55 #include <asm/netlogic/xlr/xlr.h>
57 static void *pci_config_base;
59 #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
61 /* PCI ops */
62 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
63 int where)
65 u32 data;
66 u32 *cfgaddr;
68 cfgaddr = (u32 *)(pci_config_base +
69 pci_cfg_addr(bus->number, devfn, where & ~3));
70 data = *cfgaddr;
71 return cpu_to_le32(data);
74 static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
75 int where, u32 data)
77 u32 *cfgaddr;
79 cfgaddr = (u32 *)(pci_config_base +
80 pci_cfg_addr(bus->number, devfn, where & ~3));
81 *cfgaddr = cpu_to_le32(data);
84 static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
85 int where, int size, u32 *val)
87 u32 data;
89 if ((size == 2) && (where & 1))
90 return PCIBIOS_BAD_REGISTER_NUMBER;
91 else if ((size == 4) && (where & 3))
92 return PCIBIOS_BAD_REGISTER_NUMBER;
94 data = pci_cfg_read_32bit(bus, devfn, where);
96 if (size == 1)
97 *val = (data >> ((where & 3) << 3)) & 0xff;
98 else if (size == 2)
99 *val = (data >> ((where & 3) << 3)) & 0xffff;
100 else
101 *val = data;
103 return PCIBIOS_SUCCESSFUL;
107 static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
108 int where, int size, u32 val)
110 u32 data;
112 if ((size == 2) && (where & 1))
113 return PCIBIOS_BAD_REGISTER_NUMBER;
114 else if ((size == 4) && (where & 3))
115 return PCIBIOS_BAD_REGISTER_NUMBER;
117 data = pci_cfg_read_32bit(bus, devfn, where);
119 if (size == 1)
120 data = (data & ~(0xff << ((where & 3) << 3))) |
121 (val << ((where & 3) << 3));
122 else if (size == 2)
123 data = (data & ~(0xffff << ((where & 3) << 3))) |
124 (val << ((where & 3) << 3));
125 else
126 data = val;
128 pci_cfg_write_32bit(bus, devfn, where, data);
130 return PCIBIOS_SUCCESSFUL;
133 struct pci_ops nlm_pci_ops = {
134 .read = nlm_pcibios_read,
135 .write = nlm_pcibios_write
138 static struct resource nlm_pci_mem_resource = {
139 .name = "XLR PCI MEM",
140 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
141 .end = 0xdfffffffUL,
142 .flags = IORESOURCE_MEM,
145 static struct resource nlm_pci_io_resource = {
146 .name = "XLR IO MEM",
147 .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
148 .end = 0x100fffffUL,
149 .flags = IORESOURCE_IO,
152 struct pci_controller nlm_pci_controller = {
153 .index = 0,
154 .pci_ops = &nlm_pci_ops,
155 .mem_resource = &nlm_pci_mem_resource,
156 .mem_offset = 0x00000000UL,
157 .io_resource = &nlm_pci_io_resource,
158 .io_offset = 0x00000000UL,
162 * The top level PCIe links on the XLS PCIe controller appear as
163 * bridges. Given a device, this function finds which link it is
164 * on.
166 static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev)
168 struct pci_bus *bus, *p;
170 /* Find the bridge on bus 0 */
171 bus = dev->bus;
172 for (p = bus->parent; p && p->number != 0; p = p->parent)
173 bus = p;
175 return p ? bus->self : NULL;
178 static int nlm_pci_link_to_irq(int link)
180 switch (link) {
181 case 0:
182 return PIC_PCIE_LINK0_IRQ;
183 case 1:
184 return PIC_PCIE_LINK1_IRQ;
185 case 2:
186 if (nlm_chip_is_xls_b())
187 return PIC_PCIE_XLSB0_LINK2_IRQ;
188 else
189 return PIC_PCIE_LINK2_IRQ;
190 case 3:
191 if (nlm_chip_is_xls_b())
192 return PIC_PCIE_XLSB0_LINK3_IRQ;
193 else
194 return PIC_PCIE_LINK3_IRQ;
196 WARN(1, "Unexpected link %d\n", link);
197 return 0;
200 static int get_irq_vector(const struct pci_dev *dev)
202 struct pci_dev *lnk;
203 int link;
205 if (!nlm_chip_is_xls())
206 return PIC_PCIX_IRQ; /* for XLR just one IRQ */
208 lnk = xls_get_pcie_link(dev);
209 if (lnk == NULL)
210 return 0;
212 link = PCI_SLOT(lnk->devfn);
213 return nlm_pci_link_to_irq(link);
216 #ifdef CONFIG_PCI_MSI
217 void arch_teardown_msi_irq(unsigned int irq)
221 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
223 struct msi_msg msg;
224 struct pci_dev *lnk;
225 int irq, ret;
226 u16 val;
228 /* MSI not supported on XLR */
229 if (!nlm_chip_is_xls())
230 return 1;
233 * Enable MSI on the XLS PCIe controller bridge which was disabled
234 * at enumeration, the bridge MSI capability is at 0x50
236 lnk = xls_get_pcie_link(dev);
237 if (lnk == NULL)
238 return 1;
240 pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val);
241 if ((val & PCI_MSI_FLAGS_ENABLE) == 0) {
242 val |= PCI_MSI_FLAGS_ENABLE;
243 pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val);
246 irq = get_irq_vector(dev);
247 if (irq <= 0)
248 return 1;
250 msg.address_hi = MSI_ADDR_BASE_HI;
251 msg.address_lo = MSI_ADDR_BASE_LO |
252 MSI_ADDR_DEST_MODE_PHYSICAL |
253 MSI_ADDR_REDIRECTION_CPU;
255 msg.data = MSI_DATA_TRIGGER_EDGE |
256 MSI_DATA_LEVEL_ASSERT |
257 MSI_DATA_DELIVERY_FIXED;
259 ret = irq_set_msi_desc(irq, desc);
260 if (ret < 0)
261 return ret;
263 pci_write_msi_msg(irq, &msg);
264 return 0;
266 #endif
268 /* Extra ACK needed for XLR on chip PCI controller */
269 static void xlr_pci_ack(struct irq_data *d)
271 uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
273 nlm_read_reg(pcibase, (0x140 >> 2));
276 /* Extra ACK needed for XLS on chip PCIe controller */
277 static void xls_pcie_ack(struct irq_data *d)
279 uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
281 switch (d->irq) {
282 case PIC_PCIE_LINK0_IRQ:
283 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
284 break;
285 case PIC_PCIE_LINK1_IRQ:
286 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
287 break;
288 case PIC_PCIE_LINK2_IRQ:
289 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
290 break;
291 case PIC_PCIE_LINK3_IRQ:
292 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
293 break;
297 /* For XLS B silicon, the 3,4 PCI interrupts are different */
298 static void xls_pcie_ack_b(struct irq_data *d)
300 uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
302 switch (d->irq) {
303 case PIC_PCIE_LINK0_IRQ:
304 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
305 break;
306 case PIC_PCIE_LINK1_IRQ:
307 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
308 break;
309 case PIC_PCIE_XLSB0_LINK2_IRQ:
310 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
311 break;
312 case PIC_PCIE_XLSB0_LINK3_IRQ:
313 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
314 break;
318 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
320 return get_irq_vector(dev);
323 /* Do platform specific device initialization at pci_enable_device() time */
324 int pcibios_plat_dev_init(struct pci_dev *dev)
326 return 0;
329 static int __init pcibios_init(void)
331 void (*extra_ack)(struct irq_data *);
332 int link, irq;
334 /* PSB assigns PCI resources */
335 pci_set_flags(PCI_PROBE_ONLY);
336 pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
338 /* Extend IO port for memory mapped io */
339 ioport_resource.start = 0;
340 ioport_resource.end = ~0;
342 set_io_port_base(CKSEG1);
343 nlm_pci_controller.io_map_base = CKSEG1;
345 pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
346 register_pci_controller(&nlm_pci_controller);
349 * For PCI interrupts, we need to ack the PCI controller too, overload
350 * irq handler data to do this
352 if (!nlm_chip_is_xls()) {
353 /* XLR PCI controller ACK */
354 nlm_set_pic_extra_ack(0, PIC_PCIX_IRQ, xlr_pci_ack);
355 } else {
356 if (nlm_chip_is_xls_b())
357 extra_ack = xls_pcie_ack_b;
358 else
359 extra_ack = xls_pcie_ack;
360 for (link = 0; link < 4; link++) {
361 irq = nlm_pci_link_to_irq(link);
362 nlm_set_pic_extra_ack(0, irq, extra_ack);
365 return 0;
368 arch_initcall(pcibios_init);