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x86/boot: Rename overlapping memcpy() to memmove()
[linux/fpc-iii.git] / drivers / video / fbdev / omap2 / omapfb / dss / venc.c
blob26e0ee30adf85b1c7a0f81fe3045272d8fa5b47c
1 /*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #define DSS_SUBSYS_NAME "VENC"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/of.h>
38 #include <linux/component.h>
39
40 #include <video/omapdss.h>
41
42 #include "dss.h"
43 #include "dss_features.h"
44
45 /* Venc registers */
46 #define VENC_REV_ID 0x00
47 #define VENC_STATUS 0x04
48 #define VENC_F_CONTROL 0x08
49 #define VENC_VIDOUT_CTRL 0x10
50 #define VENC_SYNC_CTRL 0x14
51 #define VENC_LLEN 0x1C
52 #define VENC_FLENS 0x20
53 #define VENC_HFLTR_CTRL 0x24
54 #define VENC_CC_CARR_WSS_CARR 0x28
55 #define VENC_C_PHASE 0x2C
56 #define VENC_GAIN_U 0x30
57 #define VENC_GAIN_V 0x34
58 #define VENC_GAIN_Y 0x38
59 #define VENC_BLACK_LEVEL 0x3C
60 #define VENC_BLANK_LEVEL 0x40
61 #define VENC_X_COLOR 0x44
62 #define VENC_M_CONTROL 0x48
63 #define VENC_BSTAMP_WSS_DATA 0x4C
64 #define VENC_S_CARR 0x50
65 #define VENC_LINE21 0x54
66 #define VENC_LN_SEL 0x58
67 #define VENC_L21__WC_CTL 0x5C
68 #define VENC_HTRIGGER_VTRIGGER 0x60
69 #define VENC_SAVID__EAVID 0x64
70 #define VENC_FLEN__FAL 0x68
71 #define VENC_LAL__PHASE_RESET 0x6C
72 #define VENC_HS_INT_START_STOP_X 0x70
73 #define VENC_HS_EXT_START_STOP_X 0x74
74 #define VENC_VS_INT_START_X 0x78
75 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
76 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
77 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
78 #define VENC_VS_EXT_STOP_Y 0x88
79 #define VENC_AVID_START_STOP_X 0x90
80 #define VENC_AVID_START_STOP_Y 0x94
81 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
82 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
83 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
84 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
85 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
86 #define VENC_GEN_CTRL 0xB8
87 #define VENC_OUTPUT_CONTROL 0xC4
88 #define VENC_OUTPUT_TEST 0xC8
89 #define VENC_DAC_B__DAC_C 0xC8
90
91 struct venc_config {
92 u32 f_control;
93 u32 vidout_ctrl;
94 u32 sync_ctrl;
95 u32 llen;
96 u32 flens;
97 u32 hfltr_ctrl;
98 u32 cc_carr_wss_carr;
99 u32 c_phase;
100 u32 gain_u;
101 u32 gain_v;
102 u32 gain_y;
103 u32 black_level;
104 u32 blank_level;
105 u32 x_color;
106 u32 m_control;
107 u32 bstamp_wss_data;
108 u32 s_carr;
109 u32 line21;
110 u32 ln_sel;
111 u32 l21__wc_ctl;
112 u32 htrigger_vtrigger;
113 u32 savid__eavid;
114 u32 flen__fal;
115 u32 lal__phase_reset;
116 u32 hs_int_start_stop_x;
117 u32 hs_ext_start_stop_x;
118 u32 vs_int_start_x;
119 u32 vs_int_stop_x__vs_int_start_y;
120 u32 vs_int_stop_y__vs_ext_start_x;
121 u32 vs_ext_stop_x__vs_ext_start_y;
122 u32 vs_ext_stop_y;
123 u32 avid_start_stop_x;
124 u32 avid_start_stop_y;
125 u32 fid_int_start_x__fid_int_start_y;
126 u32 fid_int_offset_y__fid_ext_start_x;
127 u32 fid_ext_start_y__fid_ext_offset_y;
128 u32 tvdetgp_int_start_stop_x;
129 u32 tvdetgp_int_start_stop_y;
130 u32 gen_ctrl;
131 };
132
133 /* from TRM */
134 static const struct venc_config venc_config_pal_trm = {
135 .f_control = 0,
136 .vidout_ctrl = 1,
137 .sync_ctrl = 0x40,
138 .llen = 0x35F, /* 863 */
139 .flens = 0x270, /* 624 */
140 .hfltr_ctrl = 0,
141 .cc_carr_wss_carr = 0x2F7225ED,
142 .c_phase = 0,
143 .gain_u = 0x111,
144 .gain_v = 0x181,
145 .gain_y = 0x140,
146 .black_level = 0x3B,
147 .blank_level = 0x3B,
148 .x_color = 0x7,
149 .m_control = 0x2,
150 .bstamp_wss_data = 0x3F,
151 .s_carr = 0x2A098ACB,
152 .line21 = 0,
153 .ln_sel = 0x01290015,
154 .l21__wc_ctl = 0x0000F603,
155 .htrigger_vtrigger = 0,
156
157 .savid__eavid = 0x06A70108,
158 .flen__fal = 0x00180270,
159 .lal__phase_reset = 0x00040135,
160 .hs_int_start_stop_x = 0x00880358,
161 .hs_ext_start_stop_x = 0x000F035F,
162 .vs_int_start_x = 0x01A70000,
163 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
166 .vs_ext_stop_y = 0x00000025,
167 .avid_start_stop_x = 0x03530083,
168 .avid_start_stop_y = 0x026C002E,
169 .fid_int_start_x__fid_int_start_y = 0x0001008A,
170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
172
173 .tvdetgp_int_start_stop_x = 0x00140001,
174 .tvdetgp_int_start_stop_y = 0x00010001,
175 .gen_ctrl = 0x00FF0000,
176 };
177
178 /* from TRM */
179 static const struct venc_config venc_config_ntsc_trm = {
180 .f_control = 0,
181 .vidout_ctrl = 1,
182 .sync_ctrl = 0x8040,
183 .llen = 0x359,
184 .flens = 0x20C,
185 .hfltr_ctrl = 0,
186 .cc_carr_wss_carr = 0x043F2631,
187 .c_phase = 0,
188 .gain_u = 0x102,
189 .gain_v = 0x16C,
190 .gain_y = 0x12F,
191 .black_level = 0x43,
192 .blank_level = 0x38,
193 .x_color = 0x7,
194 .m_control = 0x1,
195 .bstamp_wss_data = 0x38,
196 .s_carr = 0x21F07C1F,
197 .line21 = 0,
198 .ln_sel = 0x01310011,
199 .l21__wc_ctl = 0x0000F003,
200 .htrigger_vtrigger = 0,
201
202 .savid__eavid = 0x069300F4,
203 .flen__fal = 0x0016020C,
204 .lal__phase_reset = 0x00060107,
205 .hs_int_start_stop_x = 0x008E0350,
206 .hs_ext_start_stop_x = 0x000F0359,
207 .vs_int_start_x = 0x01A00000,
208 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
211 .vs_ext_stop_y = 0x00000006,
212 .avid_start_stop_x = 0x03480078,
213 .avid_start_stop_y = 0x02060024,
214 .fid_int_start_x__fid_int_start_y = 0x0001008A,
215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
217
218 .tvdetgp_int_start_stop_x = 0x00140001,
219 .tvdetgp_int_start_stop_y = 0x00010001,
220 .gen_ctrl = 0x00F90000,
221 };
222
223 static const struct venc_config venc_config_pal_bdghi = {
224 .f_control = 0,
225 .vidout_ctrl = 0,
226 .sync_ctrl = 0,
227 .hfltr_ctrl = 0,
228 .x_color = 0,
229 .line21 = 0,
230 .ln_sel = 21,
231 .htrigger_vtrigger = 0,
232 .tvdetgp_int_start_stop_x = 0x00140001,
233 .tvdetgp_int_start_stop_y = 0x00010001,
234 .gen_ctrl = 0x00FB0000,
235
236 .llen = 864-1,
237 .flens = 625-1,
238 .cc_carr_wss_carr = 0x2F7625ED,
239 .c_phase = 0xDF,
240 .gain_u = 0x111,
241 .gain_v = 0x181,
242 .gain_y = 0x140,
243 .black_level = 0x3e,
244 .blank_level = 0x3e,
245 .m_control = 0<<2 | 1<<1,
246 .bstamp_wss_data = 0x42,
247 .s_carr = 0x2a098acb,
248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
249 .savid__eavid = 0x06A70108,
250 .flen__fal = 23<<16 | 624<<0,
251 .lal__phase_reset = 2<<17 | 310<<0,
252 .hs_int_start_stop_x = 0x00920358,
253 .hs_ext_start_stop_x = 0x000F035F,
254 .vs_int_start_x = 0x1a7<<16,
255 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
258 .vs_ext_stop_y = 0x05,
259 .avid_start_stop_x = 0x03530082,
260 .avid_start_stop_y = 0x0270002E,
261 .fid_int_start_x__fid_int_start_y = 0x0005008A,
262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
264 };
265
266 const struct omap_video_timings omap_dss_pal_timings = {
267 .x_res = 720,
268 .y_res = 574,
269 .pixelclock = 13500000,
270 .hsw = 64,
271 .hfp = 12,
272 .hbp = 68,
273 .vsw = 5,
274 .vfp = 5,
275 .vbp = 41,
276
277 .interlace = true,
278 };
279 EXPORT_SYMBOL(omap_dss_pal_timings);
280
281 const struct omap_video_timings omap_dss_ntsc_timings = {
282 .x_res = 720,
283 .y_res = 482,
284 .pixelclock = 13500000,
285 .hsw = 64,
286 .hfp = 16,
287 .hbp = 58,
288 .vsw = 6,
289 .vfp = 6,
290 .vbp = 31,
291
292 .interlace = true,
293 };
294 EXPORT_SYMBOL(omap_dss_ntsc_timings);
295
296 static struct {
297 struct platform_device *pdev;
298 void __iomem *base;
299 struct mutex venc_lock;
300 u32 wss_data;
301 struct regulator *vdda_dac_reg;
302
303 struct clk *tv_dac_clk;
304
305 struct omap_video_timings timings;
306 enum omap_dss_venc_type type;
307 bool invert_polarity;
308
309 struct omap_dss_device output;
310 } venc;
311
312 static inline void venc_write_reg(int idx, u32 val)
313 {
314 __raw_writel(val, venc.base + idx);
315 }
316
317 static inline u32 venc_read_reg(int idx)
318 {
319 u32 l = __raw_readl(venc.base + idx);
320 return l;
321 }
322
323 static void venc_write_config(const struct venc_config *config)
324 {
325 DSSDBG("write venc conf\n");
326
327 venc_write_reg(VENC_LLEN, config->llen);
328 venc_write_reg(VENC_FLENS, config->flens);
329 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
330 venc_write_reg(VENC_C_PHASE, config->c_phase);
331 venc_write_reg(VENC_GAIN_U, config->gain_u);
332 venc_write_reg(VENC_GAIN_V, config->gain_v);
333 venc_write_reg(VENC_GAIN_Y, config->gain_y);
334 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
335 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
336 venc_write_reg(VENC_M_CONTROL, config->m_control);
337 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
338 venc.wss_data);
339 venc_write_reg(VENC_S_CARR, config->s_carr);
340 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
341 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
342 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
343 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
344 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
345 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
346 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
347 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
348 config->vs_int_stop_x__vs_int_start_y);
349 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
350 config->vs_int_stop_y__vs_ext_start_x);
351 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
352 config->vs_ext_stop_x__vs_ext_start_y);
353 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
354 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
355 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
356 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
357 config->fid_int_start_x__fid_int_start_y);
358 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
359 config->fid_int_offset_y__fid_ext_start_x);
360 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
361 config->fid_ext_start_y__fid_ext_offset_y);
362
363 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
364 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
365 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
366 venc_write_reg(VENC_X_COLOR, config->x_color);
367 venc_write_reg(VENC_LINE21, config->line21);
368 venc_write_reg(VENC_LN_SEL, config->ln_sel);
369 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
370 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
371 config->tvdetgp_int_start_stop_x);
372 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
373 config->tvdetgp_int_start_stop_y);
374 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
375 venc_write_reg(VENC_F_CONTROL, config->f_control);
376 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
377 }
378
379 static void venc_reset(void)
380 {
381 int t = 1000;
382
383 venc_write_reg(VENC_F_CONTROL, 1<<8);
384 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
385 if (--t == 0) {
386 DSSERR("Failed to reset venc\n");
387 return;
388 }
389 }
390
391 #ifdef CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
392 /* the magical sleep that makes things work */
393 /* XXX more info? What bug this circumvents? */
394 msleep(20);
395 #endif
396 }
397
398 static int venc_runtime_get(void)
399 {
400 int r;
401
402 DSSDBG("venc_runtime_get\n");
403
404 r = pm_runtime_get_sync(&venc.pdev->dev);
405 WARN_ON(r < 0);
406 return r < 0 ? r : 0;
407 }
408
409 static void venc_runtime_put(void)
410 {
411 int r;
412
413 DSSDBG("venc_runtime_put\n");
414
415 r = pm_runtime_put_sync(&venc.pdev->dev);
416 WARN_ON(r < 0 && r != -ENOSYS);
417 }
418
419 static const struct venc_config *venc_timings_to_config(
420 struct omap_video_timings *timings)
421 {
422 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
423 return &venc_config_pal_trm;
424
425 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
426 return &venc_config_ntsc_trm;
427
428 BUG();
429 return NULL;
430 }
431
432 static int venc_power_on(struct omap_dss_device *dssdev)
433 {
434 struct omap_overlay_manager *mgr = venc.output.manager;
435 u32 l;
436 int r;
437
438 r = venc_runtime_get();
439 if (r)
440 goto err0;
441
442 venc_reset();
443 venc_write_config(venc_timings_to_config(&venc.timings));
444
445 dss_set_venc_output(venc.type);
446 dss_set_dac_pwrdn_bgz(1);
447
448 l = 0;
449
450 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
451 l |= 1 << 1;
452 else /* S-Video */
453 l |= (1 << 0) | (1 << 2);
454
455 if (venc.invert_polarity == false)
456 l |= 1 << 3;
457
458 venc_write_reg(VENC_OUTPUT_CONTROL, l);
459
460 dss_mgr_set_timings(mgr, &venc.timings);
461
462 r = regulator_enable(venc.vdda_dac_reg);
463 if (r)
464 goto err1;
465
466 r = dss_mgr_enable(mgr);
467 if (r)
468 goto err2;
469
470 return 0;
471
472 err2:
473 regulator_disable(venc.vdda_dac_reg);
474 err1:
475 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
476 dss_set_dac_pwrdn_bgz(0);
477
478 venc_runtime_put();
479 err0:
480 return r;
481 }
482
483 static void venc_power_off(struct omap_dss_device *dssdev)
484 {
485 struct omap_overlay_manager *mgr = venc.output.manager;
486
487 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
488 dss_set_dac_pwrdn_bgz(0);
489
490 dss_mgr_disable(mgr);
491
492 regulator_disable(venc.vdda_dac_reg);
493
494 venc_runtime_put();
495 }
496
497 static int venc_display_enable(struct omap_dss_device *dssdev)
498 {
499 struct omap_dss_device *out = &venc.output;
500 int r;
501
502 DSSDBG("venc_display_enable\n");
503
504 mutex_lock(&venc.venc_lock);
505
506 if (out->manager == NULL) {
507 DSSERR("Failed to enable display: no output/manager\n");
508 r = -ENODEV;
509 goto err0;
510 }
511
512 r = venc_power_on(dssdev);
513 if (r)
514 goto err0;
515
516 venc.wss_data = 0;
517
518 mutex_unlock(&venc.venc_lock);
519
520 return 0;
521 err0:
522 mutex_unlock(&venc.venc_lock);
523 return r;
524 }
525
526 static void venc_display_disable(struct omap_dss_device *dssdev)
527 {
528 DSSDBG("venc_display_disable\n");
529
530 mutex_lock(&venc.venc_lock);
531
532 venc_power_off(dssdev);
533
534 mutex_unlock(&venc.venc_lock);
535 }
536
537 static void venc_set_timings(struct omap_dss_device *dssdev,
538 struct omap_video_timings *timings)
539 {
540 DSSDBG("venc_set_timings\n");
541
542 mutex_lock(&venc.venc_lock);
543
544 /* Reset WSS data when the TV standard changes. */
545 if (memcmp(&venc.timings, timings, sizeof(*timings)))
546 venc.wss_data = 0;
547
548 venc.timings = *timings;
549
550 dispc_set_tv_pclk(13500000);
551
552 mutex_unlock(&venc.venc_lock);
553 }
554
555 static int venc_check_timings(struct omap_dss_device *dssdev,
556 struct omap_video_timings *timings)
557 {
558 DSSDBG("venc_check_timings\n");
559
560 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
561 return 0;
562
563 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
564 return 0;
565
566 return -EINVAL;
567 }
568
569 static void venc_get_timings(struct omap_dss_device *dssdev,
570 struct omap_video_timings *timings)
571 {
572 mutex_lock(&venc.venc_lock);
573
574 *timings = venc.timings;
575
576 mutex_unlock(&venc.venc_lock);
577 }
578
579 static u32 venc_get_wss(struct omap_dss_device *dssdev)
580 {
581 /* Invert due to VENC_L21_WC_CTL:INV=1 */
582 return (venc.wss_data >> 8) ^ 0xfffff;
583 }
584
585 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
586 {
587 const struct venc_config *config;
588 int r;
589
590 DSSDBG("venc_set_wss\n");
591
592 mutex_lock(&venc.venc_lock);
593
594 config = venc_timings_to_config(&venc.timings);
595
596 /* Invert due to VENC_L21_WC_CTL:INV=1 */
597 venc.wss_data = (wss ^ 0xfffff) << 8;
598
599 r = venc_runtime_get();
600 if (r)
601 goto err;
602
603 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
604 venc.wss_data);
605
606 venc_runtime_put();
607
608 err:
609 mutex_unlock(&venc.venc_lock);
610
611 return r;
612 }
613
614 static void venc_set_type(struct omap_dss_device *dssdev,
615 enum omap_dss_venc_type type)
616 {
617 mutex_lock(&venc.venc_lock);
618
619 venc.type = type;
620
621 mutex_unlock(&venc.venc_lock);
622 }
623
624 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
625 bool invert_polarity)
626 {
627 mutex_lock(&venc.venc_lock);
628
629 venc.invert_polarity = invert_polarity;
630
631 mutex_unlock(&venc.venc_lock);
632 }
633
634 static int venc_init_regulator(void)
635 {
636 struct regulator *vdda_dac;
637
638 if (venc.vdda_dac_reg != NULL)
639 return 0;
640
641 if (venc.pdev->dev.of_node)
642 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
643 else
644 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
645
646 if (IS_ERR(vdda_dac)) {
647 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
648 DSSERR("can't get VDDA_DAC regulator\n");
649 return PTR_ERR(vdda_dac);
650 }
651
652 venc.vdda_dac_reg = vdda_dac;
653
654 return 0;
655 }
656
657 static void venc_dump_regs(struct seq_file *s)
658 {
659 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
660
661 if (venc_runtime_get())
662 return;
663
664 DUMPREG(VENC_F_CONTROL);
665 DUMPREG(VENC_VIDOUT_CTRL);
666 DUMPREG(VENC_SYNC_CTRL);
667 DUMPREG(VENC_LLEN);
668 DUMPREG(VENC_FLENS);
669 DUMPREG(VENC_HFLTR_CTRL);
670 DUMPREG(VENC_CC_CARR_WSS_CARR);
671 DUMPREG(VENC_C_PHASE);
672 DUMPREG(VENC_GAIN_U);
673 DUMPREG(VENC_GAIN_V);
674 DUMPREG(VENC_GAIN_Y);
675 DUMPREG(VENC_BLACK_LEVEL);
676 DUMPREG(VENC_BLANK_LEVEL);
677 DUMPREG(VENC_X_COLOR);
678 DUMPREG(VENC_M_CONTROL);
679 DUMPREG(VENC_BSTAMP_WSS_DATA);
680 DUMPREG(VENC_S_CARR);
681 DUMPREG(VENC_LINE21);
682 DUMPREG(VENC_LN_SEL);
683 DUMPREG(VENC_L21__WC_CTL);
684 DUMPREG(VENC_HTRIGGER_VTRIGGER);
685 DUMPREG(VENC_SAVID__EAVID);
686 DUMPREG(VENC_FLEN__FAL);
687 DUMPREG(VENC_LAL__PHASE_RESET);
688 DUMPREG(VENC_HS_INT_START_STOP_X);
689 DUMPREG(VENC_HS_EXT_START_STOP_X);
690 DUMPREG(VENC_VS_INT_START_X);
691 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
692 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
693 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
694 DUMPREG(VENC_VS_EXT_STOP_Y);
695 DUMPREG(VENC_AVID_START_STOP_X);
696 DUMPREG(VENC_AVID_START_STOP_Y);
697 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
698 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
699 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
700 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
701 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
702 DUMPREG(VENC_GEN_CTRL);
703 DUMPREG(VENC_OUTPUT_CONTROL);
704 DUMPREG(VENC_OUTPUT_TEST);
705
706 venc_runtime_put();
707
708 #undef DUMPREG
709 }
710
711 static int venc_get_clocks(struct platform_device *pdev)
712 {
713 struct clk *clk;
714
715 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
716 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
717 if (IS_ERR(clk)) {
718 DSSERR("can't get tv_dac_clk\n");
719 return PTR_ERR(clk);
720 }
721 } else {
722 clk = NULL;
723 }
724
725 venc.tv_dac_clk = clk;
726
727 return 0;
728 }
729
730 static int venc_connect(struct omap_dss_device *dssdev,
731 struct omap_dss_device *dst)
732 {
733 struct omap_overlay_manager *mgr;
734 int r;
735
736 r = venc_init_regulator();
737 if (r)
738 return r;
739
740 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
741 if (!mgr)
742 return -ENODEV;
743
744 r = dss_mgr_connect(mgr, dssdev);
745 if (r)
746 return r;
747
748 r = omapdss_output_set_device(dssdev, dst);
749 if (r) {
750 DSSERR("failed to connect output to new device: %s\n",
751 dst->name);
752 dss_mgr_disconnect(mgr, dssdev);
753 return r;
754 }
755
756 return 0;
757 }
758
759 static void venc_disconnect(struct omap_dss_device *dssdev,
760 struct omap_dss_device *dst)
761 {
762 WARN_ON(dst != dssdev->dst);
763
764 if (dst != dssdev->dst)
765 return;
766
767 omapdss_output_unset_device(dssdev);
768
769 if (dssdev->manager)
770 dss_mgr_disconnect(dssdev->manager, dssdev);
771 }
772
773 static const struct omapdss_atv_ops venc_ops = {
774 .connect = venc_connect,
775 .disconnect = venc_disconnect,
776
777 .enable = venc_display_enable,
778 .disable = venc_display_disable,
779
780 .check_timings = venc_check_timings,
781 .set_timings = venc_set_timings,
782 .get_timings = venc_get_timings,
783
784 .set_type = venc_set_type,
785 .invert_vid_out_polarity = venc_invert_vid_out_polarity,
786
787 .set_wss = venc_set_wss,
788 .get_wss = venc_get_wss,
789 };
790
791 static void venc_init_output(struct platform_device *pdev)
792 {
793 struct omap_dss_device *out = &venc.output;
794
795 out->dev = &pdev->dev;
796 out->id = OMAP_DSS_OUTPUT_VENC;
797 out->output_type = OMAP_DISPLAY_TYPE_VENC;
798 out->name = "venc.0";
799 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
800 out->ops.atv = &venc_ops;
801 out->owner = THIS_MODULE;
802
803 omapdss_register_output(out);
804 }
805
806 static void venc_uninit_output(struct platform_device *pdev)
807 {
808 struct omap_dss_device *out = &venc.output;
809
810 omapdss_unregister_output(out);
811 }
812
813 static int venc_probe_of(struct platform_device *pdev)
814 {
815 struct device_node *node = pdev->dev.of_node;
816 struct device_node *ep;
817 u32 channels;
818 int r;
819
820 ep = omapdss_of_get_first_endpoint(node);
821 if (!ep)
822 return 0;
823
824 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
825
826 r = of_property_read_u32(ep, "ti,channels", &channels);
827 if (r) {
828 dev_err(&pdev->dev,
829 "failed to read property 'ti,channels': %d\n", r);
830 goto err;
831 }
832
833 switch (channels) {
834 case 1:
835 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
836 break;
837 case 2:
838 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
839 break;
840 default:
841 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
842 r = -EINVAL;
843 goto err;
844 }
845
846 of_node_put(ep);
847
848 return 0;
849 err:
850 of_node_put(ep);
851
852 return 0;
853 }
854
855 /* VENC HW IP initialisation */
856 static int venc_bind(struct device *dev, struct device *master, void *data)
857 {
858 struct platform_device *pdev = to_platform_device(dev);
859 u8 rev_id;
860 struct resource *venc_mem;
861 int r;
862
863 venc.pdev = pdev;
864
865 mutex_init(&venc.venc_lock);
866
867 venc.wss_data = 0;
868
869 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
870 if (!venc_mem) {
871 DSSERR("can't get IORESOURCE_MEM VENC\n");
872 return -EINVAL;
873 }
874
875 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
876 resource_size(venc_mem));
877 if (!venc.base) {
878 DSSERR("can't ioremap VENC\n");
879 return -ENOMEM;
880 }
881
882 r = venc_get_clocks(pdev);
883 if (r)
884 return r;
885
886 pm_runtime_enable(&pdev->dev);
887
888 r = venc_runtime_get();
889 if (r)
890 goto err_runtime_get;
891
892 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
893 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
894
895 venc_runtime_put();
896
897 if (pdev->dev.of_node) {
898 r = venc_probe_of(pdev);
899 if (r) {
900 DSSERR("Invalid DT data\n");
901 goto err_probe_of;
902 }
903 }
904
905 dss_debugfs_create_file("venc", venc_dump_regs);
906
907 venc_init_output(pdev);
908
909 return 0;
910
911 err_probe_of:
912 err_runtime_get:
913 pm_runtime_disable(&pdev->dev);
914 return r;
915 }
916
917 static void venc_unbind(struct device *dev, struct device *master, void *data)
918 {
919 struct platform_device *pdev = to_platform_device(dev);
920
921 venc_uninit_output(pdev);
922
923 pm_runtime_disable(&pdev->dev);
924 }
925
926 static const struct component_ops venc_component_ops = {
927 .bind = venc_bind,
928 .unbind = venc_unbind,
929 };
930
931 static int venc_probe(struct platform_device *pdev)
932 {
933 return component_add(&pdev->dev, &venc_component_ops);
934 }
935
936 static int venc_remove(struct platform_device *pdev)
937 {
938 component_del(&pdev->dev, &venc_component_ops);
939 return 0;
940 }
941
942 static int venc_runtime_suspend(struct device *dev)
943 {
944 if (venc.tv_dac_clk)
945 clk_disable_unprepare(venc.tv_dac_clk);
946
947 dispc_runtime_put();
948
949 return 0;
950 }
951
952 static int venc_runtime_resume(struct device *dev)
953 {
954 int r;
955
956 r = dispc_runtime_get();
957 if (r < 0)
958 return r;
959
960 if (venc.tv_dac_clk)
961 clk_prepare_enable(venc.tv_dac_clk);
962
963 return 0;
964 }
965
966 static const struct dev_pm_ops venc_pm_ops = {
967 .runtime_suspend = venc_runtime_suspend,
968 .runtime_resume = venc_runtime_resume,
969 };
970
971 static const struct of_device_id venc_of_match[] = {
972 { .compatible = "ti,omap2-venc", },
973 { .compatible = "ti,omap3-venc", },
974 { .compatible = "ti,omap4-venc", },
975 {},
976 };
977
978 static struct platform_driver omap_venchw_driver = {
979 .probe = venc_probe,
980 .remove = venc_remove,
981 .driver = {
982 .name = "omapdss_venc",
983 .pm = &venc_pm_ops,
984 .of_match_table = venc_of_match,
985 .suppress_bind_attrs = true,
986 },
987 };
988
989 int __init venc_init_platform_driver(void)
990 {
991 return platform_driver_register(&omap_venchw_driver);
992 }
993
994 void venc_uninit_platform_driver(void)
995 {
996 platform_driver_unregister(&omap_venchw_driver);
997 }
Linux with added FPC-III support