?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ASoC: es8316: Add jack-detect support
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob1167ff0416cf7471d9fb372e2b32a1f086ec558f
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
46 #include <asm/apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
51 #include <asm/gart.h>
52 #include <asm/dma.h>
53
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
57
58 #define AMD_IOMMU_MAPPING_ERROR 0
59
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
62 #define LOOP_TIMEOUT 100000
63
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
86
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 }
158
159 static inline u16 get_pci_device_id(struct device *dev)
160 {
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 }
165
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168 {
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179 }
180
181 static inline int get_device_id(struct device *dev)
182 {
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191 }
192
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 {
195 return container_of(dom, struct protection_domain, domain);
196 }
197
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 {
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202 }
203
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 {
206 struct iommu_dev_data *dev_data;
207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
214
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
216 return dev_data;
217 }
218
219 static struct iommu_dev_data *search_dev_data(u16 devid)
220 {
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
223
224 if (llist_empty(&dev_data_list))
225 return NULL;
226
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
230 return dev_data;
231 }
232
233 return NULL;
234 }
235
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237 {
238 *(u16 *)data = alias;
239 return 0;
240 }
241
242 static u16 get_alias(struct device *dev)
243 {
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
249
250 /* For ACPI HID devices, we simply return the devid as such */
251 if (!dev_is_pci(dev))
252 return devid;
253
254 ivrs_alias = amd_iommu_alias_table[devid];
255
256 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
257
258 if (ivrs_alias == pci_alias)
259 return ivrs_alias;
260
261 /*
262 * DMA alias showdown
263 *
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
269 */
270 if (ivrs_alias == devid) {
271 if (!amd_iommu_rlookup_table[pci_alias]) {
272 amd_iommu_rlookup_table[pci_alias] =
273 amd_iommu_rlookup_table[devid];
274 memcpy(amd_iommu_dev_table[pci_alias].data,
275 amd_iommu_dev_table[devid].data,
276 sizeof(amd_iommu_dev_table[pci_alias].data));
277 }
278
279 return pci_alias;
280 }
281
282 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
285 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
286 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
287 PCI_FUNC(pci_alias));
288
289 /*
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
292 */
293 if (pci_alias == devid &&
294 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
295 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
296 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
298 dev_name(dev));
299 }
300
301 return ivrs_alias;
302 }
303
304 static struct iommu_dev_data *find_dev_data(u16 devid)
305 {
306 struct iommu_dev_data *dev_data;
307 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
308
309 dev_data = search_dev_data(devid);
310
311 if (dev_data == NULL) {
312 dev_data = alloc_dev_data(devid);
313 if (!dev_data)
314 return NULL;
315
316 if (translation_pre_enabled(iommu))
317 dev_data->defer_attach = true;
318 }
319
320 return dev_data;
321 }
322
323 struct iommu_dev_data *get_dev_data(struct device *dev)
324 {
325 return dev->archdata.iommu;
326 }
327 EXPORT_SYMBOL(get_dev_data);
328
329 /*
330 * Find or create an IOMMU group for a acpihid device.
331 */
332 static struct iommu_group *acpihid_device_group(struct device *dev)
333 {
334 struct acpihid_map_entry *p, *entry = NULL;
335 int devid;
336
337 devid = get_acpihid_device_id(dev, &entry);
338 if (devid < 0)
339 return ERR_PTR(devid);
340
341 list_for_each_entry(p, &acpihid_map, list) {
342 if ((devid == p->devid) && p->group)
343 entry->group = p->group;
344 }
345
346 if (!entry->group)
347 entry->group = generic_device_group(dev);
348 else
349 iommu_group_ref_get(entry->group);
350
351 return entry->group;
352 }
353
354 static bool pci_iommuv2_capable(struct pci_dev *pdev)
355 {
356 static const int caps[] = {
357 PCI_EXT_CAP_ID_ATS,
358 PCI_EXT_CAP_ID_PRI,
359 PCI_EXT_CAP_ID_PASID,
360 };
361 int i, pos;
362
363 if (pci_ats_disabled())
364 return false;
365
366 for (i = 0; i < 3; ++i) {
367 pos = pci_find_ext_capability(pdev, caps[i]);
368 if (pos == 0)
369 return false;
370 }
371
372 return true;
373 }
374
375 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
376 {
377 struct iommu_dev_data *dev_data;
378
379 dev_data = get_dev_data(&pdev->dev);
380
381 return dev_data->errata & (1 << erratum) ? true : false;
382 }
383
384 /*
385 * This function checks if the driver got a valid device from the caller to
386 * avoid dereferencing invalid pointers.
387 */
388 static bool check_device(struct device *dev)
389 {
390 int devid;
391
392 if (!dev || !dev->dma_mask)
393 return false;
394
395 devid = get_device_id(dev);
396 if (devid < 0)
397 return false;
398
399 /* Out of our scope? */
400 if (devid > amd_iommu_last_bdf)
401 return false;
402
403 if (amd_iommu_rlookup_table[devid] == NULL)
404 return false;
405
406 return true;
407 }
408
409 static void init_iommu_group(struct device *dev)
410 {
411 struct iommu_group *group;
412
413 group = iommu_group_get_for_dev(dev);
414 if (IS_ERR(group))
415 return;
416
417 iommu_group_put(group);
418 }
419
420 static int iommu_init_device(struct device *dev)
421 {
422 struct iommu_dev_data *dev_data;
423 struct amd_iommu *iommu;
424 int devid;
425
426 if (dev->archdata.iommu)
427 return 0;
428
429 devid = get_device_id(dev);
430 if (devid < 0)
431 return devid;
432
433 iommu = amd_iommu_rlookup_table[devid];
434
435 dev_data = find_dev_data(devid);
436 if (!dev_data)
437 return -ENOMEM;
438
439 dev_data->alias = get_alias(dev);
440
441 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
442 struct amd_iommu *iommu;
443
444 iommu = amd_iommu_rlookup_table[dev_data->devid];
445 dev_data->iommu_v2 = iommu->is_iommu_v2;
446 }
447
448 dev->archdata.iommu = dev_data;
449
450 iommu_device_link(&iommu->iommu, dev);
451
452 return 0;
453 }
454
455 static void iommu_ignore_device(struct device *dev)
456 {
457 u16 alias;
458 int devid;
459
460 devid = get_device_id(dev);
461 if (devid < 0)
462 return;
463
464 alias = get_alias(dev);
465
466 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
467 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
468
469 amd_iommu_rlookup_table[devid] = NULL;
470 amd_iommu_rlookup_table[alias] = NULL;
471 }
472
473 static void iommu_uninit_device(struct device *dev)
474 {
475 struct iommu_dev_data *dev_data;
476 struct amd_iommu *iommu;
477 int devid;
478
479 devid = get_device_id(dev);
480 if (devid < 0)
481 return;
482
483 iommu = amd_iommu_rlookup_table[devid];
484
485 dev_data = search_dev_data(devid);
486 if (!dev_data)
487 return;
488
489 if (dev_data->domain)
490 detach_device(dev);
491
492 iommu_device_unlink(&iommu->iommu, dev);
493
494 iommu_group_remove_device(dev);
495
496 /* Remove dma-ops */
497 dev->dma_ops = NULL;
498
499 /*
500 * We keep dev_data around for unplugged devices and reuse it when the
501 * device is re-plugged - not doing so would introduce a ton of races.
502 */
503 }
504
505 /****************************************************************************
506 *
507 * Interrupt handling functions
508 *
509 ****************************************************************************/
510
511 static void dump_dte_entry(u16 devid)
512 {
513 int i;
514
515 for (i = 0; i < 4; ++i)
516 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
517 amd_iommu_dev_table[devid].data[i]);
518 }
519
520 static void dump_command(unsigned long phys_addr)
521 {
522 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
523 int i;
524
525 for (i = 0; i < 4; ++i)
526 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
527 }
528
529 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
530 u64 address, int flags)
531 {
532 struct iommu_dev_data *dev_data = NULL;
533 struct pci_dev *pdev;
534
535 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
536 devid & 0xff);
537 if (pdev)
538 dev_data = get_dev_data(&pdev->dev);
539
540 if (dev_data && __ratelimit(&dev_data->rs)) {
541 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
542 domain_id, address, flags);
543 } else if (printk_ratelimit()) {
544 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
545 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
546 domain_id, address, flags);
547 }
548
549 if (pdev)
550 pci_dev_put(pdev);
551 }
552
553 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
554 {
555 struct device *dev = iommu->iommu.dev;
556 int type, devid, pasid, flags, tag;
557 volatile u32 *event = __evt;
558 int count = 0;
559 u64 address;
560
561 retry:
562 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
563 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
564 pasid = PPR_PASID(*(u64 *)&event[0]);
565 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
566 address = (u64)(((u64)event[3]) << 32) | event[2];
567
568 if (type == 0) {
569 /* Did we hit the erratum? */
570 if (++count == LOOP_TIMEOUT) {
571 pr_err("AMD-Vi: No event written to event log\n");
572 return;
573 }
574 udelay(1);
575 goto retry;
576 }
577
578 if (type == EVENT_TYPE_IO_FAULT) {
579 amd_iommu_report_page_fault(devid, pasid, address, flags);
580 return;
581 } else {
582 dev_err(dev, "AMD-Vi: Event logged [");
583 }
584
585 switch (type) {
586 case EVENT_TYPE_ILL_DEV:
587 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
588 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
589 pasid, address, flags);
590 dump_dte_entry(devid);
591 break;
592 case EVENT_TYPE_DEV_TAB_ERR:
593 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
594 "address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
596 address, flags);
597 break;
598 case EVENT_TYPE_PAGE_TAB_ERR:
599 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
600 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
601 pasid, address, flags);
602 break;
603 case EVENT_TYPE_ILL_CMD:
604 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
605 dump_command(address);
606 break;
607 case EVENT_TYPE_CMD_HARD_ERR:
608 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
609 address, flags);
610 break;
611 case EVENT_TYPE_IOTLB_INV_TO:
612 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 address);
615 break;
616 case EVENT_TYPE_INV_DEV_REQ:
617 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
618 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
619 pasid, address, flags);
620 break;
621 case EVENT_TYPE_INV_PPR_REQ:
622 pasid = ((event[0] >> 16) & 0xFFFF)
623 | ((event[1] << 6) & 0xF0000);
624 tag = event[1] & 0x03FF;
625 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
626 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
627 pasid, address, flags);
628 break;
629 default:
630 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
631 event[0], event[1], event[2], event[3]);
632 }
633
634 memset(__evt, 0, 4 * sizeof(u32));
635 }
636
637 static void iommu_poll_events(struct amd_iommu *iommu)
638 {
639 u32 head, tail;
640
641 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
642 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
643
644 while (head != tail) {
645 iommu_print_event(iommu, iommu->evt_buf + head);
646 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
647 }
648
649 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
650 }
651
652 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
653 {
654 struct amd_iommu_fault fault;
655
656 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
657 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
658 return;
659 }
660
661 fault.address = raw[1];
662 fault.pasid = PPR_PASID(raw[0]);
663 fault.device_id = PPR_DEVID(raw[0]);
664 fault.tag = PPR_TAG(raw[0]);
665 fault.flags = PPR_FLAGS(raw[0]);
666
667 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
668 }
669
670 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
671 {
672 u32 head, tail;
673
674 if (iommu->ppr_log == NULL)
675 return;
676
677 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
679
680 while (head != tail) {
681 volatile u64 *raw;
682 u64 entry[2];
683 int i;
684
685 raw = (u64 *)(iommu->ppr_log + head);
686
687 /*
688 * Hardware bug: Interrupt may arrive before the entry is
689 * written to memory. If this happens we need to wait for the
690 * entry to arrive.
691 */
692 for (i = 0; i < LOOP_TIMEOUT; ++i) {
693 if (PPR_REQ_TYPE(raw[0]) != 0)
694 break;
695 udelay(1);
696 }
697
698 /* Avoid memcpy function-call overhead */
699 entry[0] = raw[0];
700 entry[1] = raw[1];
701
702 /*
703 * To detect the hardware bug we need to clear the entry
704 * back to zero.
705 */
706 raw[0] = raw[1] = 0UL;
707
708 /* Update head pointer of hardware ring-buffer */
709 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
710 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
711
712 /* Handle PPR entry */
713 iommu_handle_ppr_entry(iommu, entry);
714
715 /* Refresh ring-buffer information */
716 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
717 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
718 }
719 }
720
721 #ifdef CONFIG_IRQ_REMAP
722 static int (*iommu_ga_log_notifier)(u32);
723
724 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
725 {
726 iommu_ga_log_notifier = notifier;
727
728 return 0;
729 }
730 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
731
732 static void iommu_poll_ga_log(struct amd_iommu *iommu)
733 {
734 u32 head, tail, cnt = 0;
735
736 if (iommu->ga_log == NULL)
737 return;
738
739 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
740 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
741
742 while (head != tail) {
743 volatile u64 *raw;
744 u64 log_entry;
745
746 raw = (u64 *)(iommu->ga_log + head);
747 cnt++;
748
749 /* Avoid memcpy function-call overhead */
750 log_entry = *raw;
751
752 /* Update head pointer of hardware ring-buffer */
753 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
754 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
755
756 /* Handle GA entry */
757 switch (GA_REQ_TYPE(log_entry)) {
758 case GA_GUEST_NR:
759 if (!iommu_ga_log_notifier)
760 break;
761
762 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
763 __func__, GA_DEVID(log_entry),
764 GA_TAG(log_entry));
765
766 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
767 pr_err("AMD-Vi: GA log notifier failed.\n");
768 break;
769 default:
770 break;
771 }
772 }
773 }
774 #endif /* CONFIG_IRQ_REMAP */
775
776 #define AMD_IOMMU_INT_MASK \
777 (MMIO_STATUS_EVT_INT_MASK | \
778 MMIO_STATUS_PPR_INT_MASK | \
779 MMIO_STATUS_GALOG_INT_MASK)
780
781 irqreturn_t amd_iommu_int_thread(int irq, void *data)
782 {
783 struct amd_iommu *iommu = (struct amd_iommu *) data;
784 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
785
786 while (status & AMD_IOMMU_INT_MASK) {
787 /* Enable EVT and PPR and GA interrupts again */
788 writel(AMD_IOMMU_INT_MASK,
789 iommu->mmio_base + MMIO_STATUS_OFFSET);
790
791 if (status & MMIO_STATUS_EVT_INT_MASK) {
792 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
793 iommu_poll_events(iommu);
794 }
795
796 if (status & MMIO_STATUS_PPR_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
798 iommu_poll_ppr_log(iommu);
799 }
800
801 #ifdef CONFIG_IRQ_REMAP
802 if (status & MMIO_STATUS_GALOG_INT_MASK) {
803 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
804 iommu_poll_ga_log(iommu);
805 }
806 #endif
807
808 /*
809 * Hardware bug: ERBT1312
810 * When re-enabling interrupt (by writing 1
811 * to clear the bit), the hardware might also try to set
812 * the interrupt bit in the event status register.
813 * In this scenario, the bit will be set, and disable
814 * subsequent interrupts.
815 *
816 * Workaround: The IOMMU driver should read back the
817 * status register and check if the interrupt bits are cleared.
818 * If not, driver will need to go through the interrupt handler
819 * again and re-clear the bits
820 */
821 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
822 }
823 return IRQ_HANDLED;
824 }
825
826 irqreturn_t amd_iommu_int_handler(int irq, void *data)
827 {
828 return IRQ_WAKE_THREAD;
829 }
830
831 /****************************************************************************
832 *
833 * IOMMU command queuing functions
834 *
835 ****************************************************************************/
836
837 static int wait_on_sem(volatile u64 *sem)
838 {
839 int i = 0;
840
841 while (*sem == 0 && i < LOOP_TIMEOUT) {
842 udelay(1);
843 i += 1;
844 }
845
846 if (i == LOOP_TIMEOUT) {
847 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
848 return -EIO;
849 }
850
851 return 0;
852 }
853
854 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
855 struct iommu_cmd *cmd)
856 {
857 u8 *target;
858
859 target = iommu->cmd_buf + iommu->cmd_buf_tail;
860
861 iommu->cmd_buf_tail += sizeof(*cmd);
862 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
863
864 /* Copy command to buffer */
865 memcpy(target, cmd, sizeof(*cmd));
866
867 /* Tell the IOMMU about it */
868 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
869 }
870
871 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
872 {
873 u64 paddr = iommu_virt_to_phys((void *)address);
874
875 WARN_ON(address & 0x7ULL);
876
877 memset(cmd, 0, sizeof(*cmd));
878 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
879 cmd->data[1] = upper_32_bits(paddr);
880 cmd->data[2] = 1;
881 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
882 }
883
884 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
885 {
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = devid;
888 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
889 }
890
891 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
892 size_t size, u16 domid, int pde)
893 {
894 u64 pages;
895 bool s;
896
897 pages = iommu_num_pages(address, size, PAGE_SIZE);
898 s = false;
899
900 if (pages > 1) {
901 /*
902 * If we have to flush more than one page, flush all
903 * TLB entries for this domain
904 */
905 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
906 s = true;
907 }
908
909 address &= PAGE_MASK;
910
911 memset(cmd, 0, sizeof(*cmd));
912 cmd->data[1] |= domid;
913 cmd->data[2] = lower_32_bits(address);
914 cmd->data[3] = upper_32_bits(address);
915 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
916 if (s) /* size bit - we flush more than one 4kb page */
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
918 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
920 }
921
922 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
923 u64 address, size_t size)
924 {
925 u64 pages;
926 bool s;
927
928 pages = iommu_num_pages(address, size, PAGE_SIZE);
929 s = false;
930
931 if (pages > 1) {
932 /*
933 * If we have to flush more than one page, flush all
934 * TLB entries for this domain
935 */
936 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
937 s = true;
938 }
939
940 address &= PAGE_MASK;
941
942 memset(cmd, 0, sizeof(*cmd));
943 cmd->data[0] = devid;
944 cmd->data[0] |= (qdep & 0xff) << 24;
945 cmd->data[1] = devid;
946 cmd->data[2] = lower_32_bits(address);
947 cmd->data[3] = upper_32_bits(address);
948 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
949 if (s)
950 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
951 }
952
953 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
954 u64 address, bool size)
955 {
956 memset(cmd, 0, sizeof(*cmd));
957
958 address &= ~(0xfffULL);
959
960 cmd->data[0] = pasid;
961 cmd->data[1] = domid;
962 cmd->data[2] = lower_32_bits(address);
963 cmd->data[3] = upper_32_bits(address);
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
965 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
966 if (size)
967 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
968 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
969 }
970
971 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
972 int qdep, u64 address, bool size)
973 {
974 memset(cmd, 0, sizeof(*cmd));
975
976 address &= ~(0xfffULL);
977
978 cmd->data[0] = devid;
979 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
980 cmd->data[0] |= (qdep & 0xff) << 24;
981 cmd->data[1] = devid;
982 cmd->data[1] |= (pasid & 0xff) << 16;
983 cmd->data[2] = lower_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
985 cmd->data[3] = upper_32_bits(address);
986 if (size)
987 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
988 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
989 }
990
991 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
992 int status, int tag, bool gn)
993 {
994 memset(cmd, 0, sizeof(*cmd));
995
996 cmd->data[0] = devid;
997 if (gn) {
998 cmd->data[1] = pasid;
999 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1000 }
1001 cmd->data[3] = tag & 0x1ff;
1002 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1003
1004 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1005 }
1006
1007 static void build_inv_all(struct iommu_cmd *cmd)
1008 {
1009 memset(cmd, 0, sizeof(*cmd));
1010 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1011 }
1012
1013 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1014 {
1015 memset(cmd, 0, sizeof(*cmd));
1016 cmd->data[0] = devid;
1017 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1018 }
1019
1020 /*
1021 * Writes the command to the IOMMUs command buffer and informs the
1022 * hardware about the new command.
1023 */
1024 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1025 struct iommu_cmd *cmd,
1026 bool sync)
1027 {
1028 unsigned int count = 0;
1029 u32 left, next_tail;
1030
1031 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1032 again:
1033 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1034
1035 if (left <= 0x20) {
1036 /* Skip udelay() the first time around */
1037 if (count++) {
1038 if (count == LOOP_TIMEOUT) {
1039 pr_err("AMD-Vi: Command buffer timeout\n");
1040 return -EIO;
1041 }
1042
1043 udelay(1);
1044 }
1045
1046 /* Update head and recheck remaining space */
1047 iommu->cmd_buf_head = readl(iommu->mmio_base +
1048 MMIO_CMD_HEAD_OFFSET);
1049
1050 goto again;
1051 }
1052
1053 copy_cmd_to_buffer(iommu, cmd);
1054
1055 /* Do we need to make sure all commands are processed? */
1056 iommu->need_sync = sync;
1057
1058 return 0;
1059 }
1060
1061 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1062 struct iommu_cmd *cmd,
1063 bool sync)
1064 {
1065 unsigned long flags;
1066 int ret;
1067
1068 raw_spin_lock_irqsave(&iommu->lock, flags);
1069 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1070 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1071
1072 return ret;
1073 }
1074
1075 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1076 {
1077 return iommu_queue_command_sync(iommu, cmd, true);
1078 }
1079
1080 /*
1081 * This function queues a completion wait command into the command
1082 * buffer of an IOMMU
1083 */
1084 static int iommu_completion_wait(struct amd_iommu *iommu)
1085 {
1086 struct iommu_cmd cmd;
1087 unsigned long flags;
1088 int ret;
1089
1090 if (!iommu->need_sync)
1091 return 0;
1092
1093
1094 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1095
1096 raw_spin_lock_irqsave(&iommu->lock, flags);
1097
1098 iommu->cmd_sem = 0;
1099
1100 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1101 if (ret)
1102 goto out_unlock;
1103
1104 ret = wait_on_sem(&iommu->cmd_sem);
1105
1106 out_unlock:
1107 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1108
1109 return ret;
1110 }
1111
1112 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1113 {
1114 struct iommu_cmd cmd;
1115
1116 build_inv_dte(&cmd, devid);
1117
1118 return iommu_queue_command(iommu, &cmd);
1119 }
1120
1121 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1122 {
1123 u32 devid;
1124
1125 for (devid = 0; devid <= 0xffff; ++devid)
1126 iommu_flush_dte(iommu, devid);
1127
1128 iommu_completion_wait(iommu);
1129 }
1130
1131 /*
1132 * This function uses heavy locking and may disable irqs for some time. But
1133 * this is no issue because it is only called during resume.
1134 */
1135 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1136 {
1137 u32 dom_id;
1138
1139 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1140 struct iommu_cmd cmd;
1141 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1142 dom_id, 1);
1143 iommu_queue_command(iommu, &cmd);
1144 }
1145
1146 iommu_completion_wait(iommu);
1147 }
1148
1149 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1150 {
1151 struct iommu_cmd cmd;
1152
1153 build_inv_all(&cmd);
1154
1155 iommu_queue_command(iommu, &cmd);
1156 iommu_completion_wait(iommu);
1157 }
1158
1159 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1160 {
1161 struct iommu_cmd cmd;
1162
1163 build_inv_irt(&cmd, devid);
1164
1165 iommu_queue_command(iommu, &cmd);
1166 }
1167
1168 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1169 {
1170 u32 devid;
1171
1172 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1173 iommu_flush_irt(iommu, devid);
1174
1175 iommu_completion_wait(iommu);
1176 }
1177
1178 void iommu_flush_all_caches(struct amd_iommu *iommu)
1179 {
1180 if (iommu_feature(iommu, FEATURE_IA)) {
1181 amd_iommu_flush_all(iommu);
1182 } else {
1183 amd_iommu_flush_dte_all(iommu);
1184 amd_iommu_flush_irt_all(iommu);
1185 amd_iommu_flush_tlb_all(iommu);
1186 }
1187 }
1188
1189 /*
1190 * Command send function for flushing on-device TLB
1191 */
1192 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1193 u64 address, size_t size)
1194 {
1195 struct amd_iommu *iommu;
1196 struct iommu_cmd cmd;
1197 int qdep;
1198
1199 qdep = dev_data->ats.qdep;
1200 iommu = amd_iommu_rlookup_table[dev_data->devid];
1201
1202 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1203
1204 return iommu_queue_command(iommu, &cmd);
1205 }
1206
1207 /*
1208 * Command send function for invalidating a device table entry
1209 */
1210 static int device_flush_dte(struct iommu_dev_data *dev_data)
1211 {
1212 struct amd_iommu *iommu;
1213 u16 alias;
1214 int ret;
1215
1216 iommu = amd_iommu_rlookup_table[dev_data->devid];
1217 alias = dev_data->alias;
1218
1219 ret = iommu_flush_dte(iommu, dev_data->devid);
1220 if (!ret && alias != dev_data->devid)
1221 ret = iommu_flush_dte(iommu, alias);
1222 if (ret)
1223 return ret;
1224
1225 if (dev_data->ats.enabled)
1226 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1227
1228 return ret;
1229 }
1230
1231 /*
1232 * TLB invalidation function which is called from the mapping functions.
1233 * It invalidates a single PTE if the range to flush is within a single
1234 * page. Otherwise it flushes the whole TLB of the IOMMU.
1235 */
1236 static void __domain_flush_pages(struct protection_domain *domain,
1237 u64 address, size_t size, int pde)
1238 {
1239 struct iommu_dev_data *dev_data;
1240 struct iommu_cmd cmd;
1241 int ret = 0, i;
1242
1243 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1244
1245 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1246 if (!domain->dev_iommu[i])
1247 continue;
1248
1249 /*
1250 * Devices of this domain are behind this IOMMU
1251 * We need a TLB flush
1252 */
1253 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1254 }
1255
1256 list_for_each_entry(dev_data, &domain->dev_list, list) {
1257
1258 if (!dev_data->ats.enabled)
1259 continue;
1260
1261 ret |= device_flush_iotlb(dev_data, address, size);
1262 }
1263
1264 WARN_ON(ret);
1265 }
1266
1267 static void domain_flush_pages(struct protection_domain *domain,
1268 u64 address, size_t size)
1269 {
1270 __domain_flush_pages(domain, address, size, 0);
1271 }
1272
1273 /* Flush the whole IO/TLB for a given protection domain */
1274 static void domain_flush_tlb(struct protection_domain *domain)
1275 {
1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1277 }
1278
1279 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1280 static void domain_flush_tlb_pde(struct protection_domain *domain)
1281 {
1282 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1283 }
1284
1285 static void domain_flush_complete(struct protection_domain *domain)
1286 {
1287 int i;
1288
1289 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1290 if (domain && !domain->dev_iommu[i])
1291 continue;
1292
1293 /*
1294 * Devices of this domain are behind this IOMMU
1295 * We need to wait for completion of all commands.
1296 */
1297 iommu_completion_wait(amd_iommus[i]);
1298 }
1299 }
1300
1301
1302 /*
1303 * This function flushes the DTEs for all devices in domain
1304 */
1305 static void domain_flush_devices(struct protection_domain *domain)
1306 {
1307 struct iommu_dev_data *dev_data;
1308
1309 list_for_each_entry(dev_data, &domain->dev_list, list)
1310 device_flush_dte(dev_data);
1311 }
1312
1313 /****************************************************************************
1314 *
1315 * The functions below are used the create the page table mappings for
1316 * unity mapped regions.
1317 *
1318 ****************************************************************************/
1319
1320 /*
1321 * This function is used to add another level to an IO page table. Adding
1322 * another level increases the size of the address space by 9 bits to a size up
1323 * to 64 bits.
1324 */
1325 static bool increase_address_space(struct protection_domain *domain,
1326 gfp_t gfp)
1327 {
1328 u64 *pte;
1329
1330 if (domain->mode == PAGE_MODE_6_LEVEL)
1331 /* address space already 64 bit large */
1332 return false;
1333
1334 pte = (void *)get_zeroed_page(gfp);
1335 if (!pte)
1336 return false;
1337
1338 *pte = PM_LEVEL_PDE(domain->mode,
1339 iommu_virt_to_phys(domain->pt_root));
1340 domain->pt_root = pte;
1341 domain->mode += 1;
1342 domain->updated = true;
1343
1344 return true;
1345 }
1346
1347 static u64 *alloc_pte(struct protection_domain *domain,
1348 unsigned long address,
1349 unsigned long page_size,
1350 u64 **pte_page,
1351 gfp_t gfp)
1352 {
1353 int level, end_lvl;
1354 u64 *pte, *page;
1355
1356 BUG_ON(!is_power_of_2(page_size));
1357
1358 while (address > PM_LEVEL_SIZE(domain->mode))
1359 increase_address_space(domain, gfp);
1360
1361 level = domain->mode - 1;
1362 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1363 address = PAGE_SIZE_ALIGN(address, page_size);
1364 end_lvl = PAGE_SIZE_LEVEL(page_size);
1365
1366 while (level > end_lvl) {
1367 u64 __pte, __npte;
1368
1369 __pte = *pte;
1370
1371 if (!IOMMU_PTE_PRESENT(__pte)) {
1372 page = (u64 *)get_zeroed_page(gfp);
1373 if (!page)
1374 return NULL;
1375
1376 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1377
1378 /* pte could have been changed somewhere. */
1379 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1380 free_page((unsigned long)page);
1381 continue;
1382 }
1383 }
1384
1385 /* No level skipping support yet */
1386 if (PM_PTE_LEVEL(*pte) != level)
1387 return NULL;
1388
1389 level -= 1;
1390
1391 pte = IOMMU_PTE_PAGE(*pte);
1392
1393 if (pte_page && level == end_lvl)
1394 *pte_page = pte;
1395
1396 pte = &pte[PM_LEVEL_INDEX(level, address)];
1397 }
1398
1399 return pte;
1400 }
1401
1402 /*
1403 * This function checks if there is a PTE for a given dma address. If
1404 * there is one, it returns the pointer to it.
1405 */
1406 static u64 *fetch_pte(struct protection_domain *domain,
1407 unsigned long address,
1408 unsigned long *page_size)
1409 {
1410 int level;
1411 u64 *pte;
1412
1413 *page_size = 0;
1414
1415 if (address > PM_LEVEL_SIZE(domain->mode))
1416 return NULL;
1417
1418 level = domain->mode - 1;
1419 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1420 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1421
1422 while (level > 0) {
1423
1424 /* Not Present */
1425 if (!IOMMU_PTE_PRESENT(*pte))
1426 return NULL;
1427
1428 /* Large PTE */
1429 if (PM_PTE_LEVEL(*pte) == 7 ||
1430 PM_PTE_LEVEL(*pte) == 0)
1431 break;
1432
1433 /* No level skipping support yet */
1434 if (PM_PTE_LEVEL(*pte) != level)
1435 return NULL;
1436
1437 level -= 1;
1438
1439 /* Walk to the next level */
1440 pte = IOMMU_PTE_PAGE(*pte);
1441 pte = &pte[PM_LEVEL_INDEX(level, address)];
1442 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1443 }
1444
1445 if (PM_PTE_LEVEL(*pte) == 0x07) {
1446 unsigned long pte_mask;
1447
1448 /*
1449 * If we have a series of large PTEs, make
1450 * sure to return a pointer to the first one.
1451 */
1452 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1453 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1454 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1455 }
1456
1457 return pte;
1458 }
1459
1460 /*
1461 * Generic mapping functions. It maps a physical address into a DMA
1462 * address space. It allocates the page table pages if necessary.
1463 * In the future it can be extended to a generic mapping function
1464 * supporting all features of AMD IOMMU page tables like level skipping
1465 * and full 64 bit address spaces.
1466 */
1467 static int iommu_map_page(struct protection_domain *dom,
1468 unsigned long bus_addr,
1469 unsigned long phys_addr,
1470 unsigned long page_size,
1471 int prot,
1472 gfp_t gfp)
1473 {
1474 u64 __pte, *pte;
1475 int i, count;
1476
1477 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1478 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1479
1480 if (!(prot & IOMMU_PROT_MASK))
1481 return -EINVAL;
1482
1483 count = PAGE_SIZE_PTE_COUNT(page_size);
1484 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1485
1486 if (!pte)
1487 return -ENOMEM;
1488
1489 for (i = 0; i < count; ++i)
1490 if (IOMMU_PTE_PRESENT(pte[i]))
1491 return -EBUSY;
1492
1493 if (count > 1) {
1494 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1495 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1496 } else
1497 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1498
1499 if (prot & IOMMU_PROT_IR)
1500 __pte |= IOMMU_PTE_IR;
1501 if (prot & IOMMU_PROT_IW)
1502 __pte |= IOMMU_PTE_IW;
1503
1504 for (i = 0; i < count; ++i)
1505 pte[i] = __pte;
1506
1507 update_domain(dom);
1508
1509 return 0;
1510 }
1511
1512 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1513 unsigned long bus_addr,
1514 unsigned long page_size)
1515 {
1516 unsigned long long unmapped;
1517 unsigned long unmap_size;
1518 u64 *pte;
1519
1520 BUG_ON(!is_power_of_2(page_size));
1521
1522 unmapped = 0;
1523
1524 while (unmapped < page_size) {
1525
1526 pte = fetch_pte(dom, bus_addr, &unmap_size);
1527
1528 if (pte) {
1529 int i, count;
1530
1531 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1532 for (i = 0; i < count; i++)
1533 pte[i] = 0ULL;
1534 }
1535
1536 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1537 unmapped += unmap_size;
1538 }
1539
1540 BUG_ON(unmapped && !is_power_of_2(unmapped));
1541
1542 return unmapped;
1543 }
1544
1545 /****************************************************************************
1546 *
1547 * The next functions belong to the address allocator for the dma_ops
1548 * interface functions.
1549 *
1550 ****************************************************************************/
1551
1552
1553 static unsigned long dma_ops_alloc_iova(struct device *dev,
1554 struct dma_ops_domain *dma_dom,
1555 unsigned int pages, u64 dma_mask)
1556 {
1557 unsigned long pfn = 0;
1558
1559 pages = __roundup_pow_of_two(pages);
1560
1561 if (dma_mask > DMA_BIT_MASK(32))
1562 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1563 IOVA_PFN(DMA_BIT_MASK(32)), false);
1564
1565 if (!pfn)
1566 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1567 IOVA_PFN(dma_mask), true);
1568
1569 return (pfn << PAGE_SHIFT);
1570 }
1571
1572 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1573 unsigned long address,
1574 unsigned int pages)
1575 {
1576 pages = __roundup_pow_of_two(pages);
1577 address >>= PAGE_SHIFT;
1578
1579 free_iova_fast(&dma_dom->iovad, address, pages);
1580 }
1581
1582 /****************************************************************************
1583 *
1584 * The next functions belong to the domain allocation. A domain is
1585 * allocated for every IOMMU as the default domain. If device isolation
1586 * is enabled, every device get its own domain. The most important thing
1587 * about domains is the page table mapping the DMA address space they
1588 * contain.
1589 *
1590 ****************************************************************************/
1591
1592 /*
1593 * This function adds a protection domain to the global protection domain list
1594 */
1595 static void add_domain_to_list(struct protection_domain *domain)
1596 {
1597 unsigned long flags;
1598
1599 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1600 list_add(&domain->list, &amd_iommu_pd_list);
1601 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1602 }
1603
1604 /*
1605 * This function removes a protection domain to the global
1606 * protection domain list
1607 */
1608 static void del_domain_from_list(struct protection_domain *domain)
1609 {
1610 unsigned long flags;
1611
1612 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1613 list_del(&domain->list);
1614 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1615 }
1616
1617 static u16 domain_id_alloc(void)
1618 {
1619 int id;
1620
1621 spin_lock(&pd_bitmap_lock);
1622 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1623 BUG_ON(id == 0);
1624 if (id > 0 && id < MAX_DOMAIN_ID)
1625 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1626 else
1627 id = 0;
1628 spin_unlock(&pd_bitmap_lock);
1629
1630 return id;
1631 }
1632
1633 static void domain_id_free(int id)
1634 {
1635 spin_lock(&pd_bitmap_lock);
1636 if (id > 0 && id < MAX_DOMAIN_ID)
1637 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1638 spin_unlock(&pd_bitmap_lock);
1639 }
1640
1641 #define DEFINE_FREE_PT_FN(LVL, FN) \
1642 static void free_pt_##LVL (unsigned long __pt) \
1643 { \
1644 unsigned long p; \
1645 u64 *pt; \
1646 int i; \
1647 \
1648 pt = (u64 *)__pt; \
1649 \
1650 for (i = 0; i < 512; ++i) { \
1651 /* PTE present? */ \
1652 if (!IOMMU_PTE_PRESENT(pt[i])) \
1653 continue; \
1654 \
1655 /* Large PTE? */ \
1656 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1657 PM_PTE_LEVEL(pt[i]) == 7) \
1658 continue; \
1659 \
1660 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1661 FN(p); \
1662 } \
1663 free_page((unsigned long)pt); \
1664 }
1665
1666 DEFINE_FREE_PT_FN(l2, free_page)
1667 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1668 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1669 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1670 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1671
1672 static void free_pagetable(struct protection_domain *domain)
1673 {
1674 unsigned long root = (unsigned long)domain->pt_root;
1675
1676 switch (domain->mode) {
1677 case PAGE_MODE_NONE:
1678 break;
1679 case PAGE_MODE_1_LEVEL:
1680 free_page(root);
1681 break;
1682 case PAGE_MODE_2_LEVEL:
1683 free_pt_l2(root);
1684 break;
1685 case PAGE_MODE_3_LEVEL:
1686 free_pt_l3(root);
1687 break;
1688 case PAGE_MODE_4_LEVEL:
1689 free_pt_l4(root);
1690 break;
1691 case PAGE_MODE_5_LEVEL:
1692 free_pt_l5(root);
1693 break;
1694 case PAGE_MODE_6_LEVEL:
1695 free_pt_l6(root);
1696 break;
1697 default:
1698 BUG();
1699 }
1700 }
1701
1702 static void free_gcr3_tbl_level1(u64 *tbl)
1703 {
1704 u64 *ptr;
1705 int i;
1706
1707 for (i = 0; i < 512; ++i) {
1708 if (!(tbl[i] & GCR3_VALID))
1709 continue;
1710
1711 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1712
1713 free_page((unsigned long)ptr);
1714 }
1715 }
1716
1717 static void free_gcr3_tbl_level2(u64 *tbl)
1718 {
1719 u64 *ptr;
1720 int i;
1721
1722 for (i = 0; i < 512; ++i) {
1723 if (!(tbl[i] & GCR3_VALID))
1724 continue;
1725
1726 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1727
1728 free_gcr3_tbl_level1(ptr);
1729 }
1730 }
1731
1732 static void free_gcr3_table(struct protection_domain *domain)
1733 {
1734 if (domain->glx == 2)
1735 free_gcr3_tbl_level2(domain->gcr3_tbl);
1736 else if (domain->glx == 1)
1737 free_gcr3_tbl_level1(domain->gcr3_tbl);
1738 else
1739 BUG_ON(domain->glx != 0);
1740
1741 free_page((unsigned long)domain->gcr3_tbl);
1742 }
1743
1744 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1745 {
1746 domain_flush_tlb(&dom->domain);
1747 domain_flush_complete(&dom->domain);
1748 }
1749
1750 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1751 {
1752 struct dma_ops_domain *dom;
1753
1754 dom = container_of(iovad, struct dma_ops_domain, iovad);
1755
1756 dma_ops_domain_flush_tlb(dom);
1757 }
1758
1759 /*
1760 * Free a domain, only used if something went wrong in the
1761 * allocation path and we need to free an already allocated page table
1762 */
1763 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1764 {
1765 if (!dom)
1766 return;
1767
1768 del_domain_from_list(&dom->domain);
1769
1770 put_iova_domain(&dom->iovad);
1771
1772 free_pagetable(&dom->domain);
1773
1774 if (dom->domain.id)
1775 domain_id_free(dom->domain.id);
1776
1777 kfree(dom);
1778 }
1779
1780 /*
1781 * Allocates a new protection domain usable for the dma_ops functions.
1782 * It also initializes the page table and the address allocator data
1783 * structures required for the dma_ops interface
1784 */
1785 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1786 {
1787 struct dma_ops_domain *dma_dom;
1788
1789 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1790 if (!dma_dom)
1791 return NULL;
1792
1793 if (protection_domain_init(&dma_dom->domain))
1794 goto free_dma_dom;
1795
1796 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1797 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1798 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1799 if (!dma_dom->domain.pt_root)
1800 goto free_dma_dom;
1801
1802 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1803
1804 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1805 goto free_dma_dom;
1806
1807 /* Initialize reserved ranges */
1808 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1809
1810 add_domain_to_list(&dma_dom->domain);
1811
1812 return dma_dom;
1813
1814 free_dma_dom:
1815 dma_ops_domain_free(dma_dom);
1816
1817 return NULL;
1818 }
1819
1820 /*
1821 * little helper function to check whether a given protection domain is a
1822 * dma_ops domain
1823 */
1824 static bool dma_ops_domain(struct protection_domain *domain)
1825 {
1826 return domain->flags & PD_DMA_OPS_MASK;
1827 }
1828
1829 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1830 bool ats, bool ppr)
1831 {
1832 u64 pte_root = 0;
1833 u64 flags = 0;
1834
1835 if (domain->mode != PAGE_MODE_NONE)
1836 pte_root = iommu_virt_to_phys(domain->pt_root);
1837
1838 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1839 << DEV_ENTRY_MODE_SHIFT;
1840 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1841
1842 flags = amd_iommu_dev_table[devid].data[1];
1843
1844 if (ats)
1845 flags |= DTE_FLAG_IOTLB;
1846
1847 if (ppr) {
1848 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1849
1850 if (iommu_feature(iommu, FEATURE_EPHSUP))
1851 pte_root |= 1ULL << DEV_ENTRY_PPR;
1852 }
1853
1854 if (domain->flags & PD_IOMMUV2_MASK) {
1855 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1856 u64 glx = domain->glx;
1857 u64 tmp;
1858
1859 pte_root |= DTE_FLAG_GV;
1860 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1861
1862 /* First mask out possible old values for GCR3 table */
1863 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1864 flags &= ~tmp;
1865
1866 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1867 flags &= ~tmp;
1868
1869 /* Encode GCR3 table into DTE */
1870 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1871 pte_root |= tmp;
1872
1873 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1874 flags |= tmp;
1875
1876 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1877 flags |= tmp;
1878 }
1879
1880 flags &= ~DEV_DOMID_MASK;
1881 flags |= domain->id;
1882
1883 amd_iommu_dev_table[devid].data[1] = flags;
1884 amd_iommu_dev_table[devid].data[0] = pte_root;
1885 }
1886
1887 static void clear_dte_entry(u16 devid)
1888 {
1889 /* remove entry from the device table seen by the hardware */
1890 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1891 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1892
1893 amd_iommu_apply_erratum_63(devid);
1894 }
1895
1896 static void do_attach(struct iommu_dev_data *dev_data,
1897 struct protection_domain *domain)
1898 {
1899 struct amd_iommu *iommu;
1900 u16 alias;
1901 bool ats;
1902
1903 iommu = amd_iommu_rlookup_table[dev_data->devid];
1904 alias = dev_data->alias;
1905 ats = dev_data->ats.enabled;
1906
1907 /* Update data structures */
1908 dev_data->domain = domain;
1909 list_add(&dev_data->list, &domain->dev_list);
1910
1911 /* Do reference counting */
1912 domain->dev_iommu[iommu->index] += 1;
1913 domain->dev_cnt += 1;
1914
1915 /* Update device table */
1916 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1917 if (alias != dev_data->devid)
1918 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1919
1920 device_flush_dte(dev_data);
1921 }
1922
1923 static void do_detach(struct iommu_dev_data *dev_data)
1924 {
1925 struct amd_iommu *iommu;
1926 u16 alias;
1927
1928 iommu = amd_iommu_rlookup_table[dev_data->devid];
1929 alias = dev_data->alias;
1930
1931 /* decrease reference counters */
1932 dev_data->domain->dev_iommu[iommu->index] -= 1;
1933 dev_data->domain->dev_cnt -= 1;
1934
1935 /* Update data structures */
1936 dev_data->domain = NULL;
1937 list_del(&dev_data->list);
1938 clear_dte_entry(dev_data->devid);
1939 if (alias != dev_data->devid)
1940 clear_dte_entry(alias);
1941
1942 /* Flush the DTE entry */
1943 device_flush_dte(dev_data);
1944 }
1945
1946 /*
1947 * If a device is not yet associated with a domain, this function makes the
1948 * device visible in the domain
1949 */
1950 static int __attach_device(struct iommu_dev_data *dev_data,
1951 struct protection_domain *domain)
1952 {
1953 int ret;
1954
1955 /* lock domain */
1956 spin_lock(&domain->lock);
1957
1958 ret = -EBUSY;
1959 if (dev_data->domain != NULL)
1960 goto out_unlock;
1961
1962 /* Attach alias group root */
1963 do_attach(dev_data, domain);
1964
1965 ret = 0;
1966
1967 out_unlock:
1968
1969 /* ready */
1970 spin_unlock(&domain->lock);
1971
1972 return ret;
1973 }
1974
1975
1976 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1977 {
1978 pci_disable_ats(pdev);
1979 pci_disable_pri(pdev);
1980 pci_disable_pasid(pdev);
1981 }
1982
1983 /* FIXME: Change generic reset-function to do the same */
1984 static int pri_reset_while_enabled(struct pci_dev *pdev)
1985 {
1986 u16 control;
1987 int pos;
1988
1989 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1990 if (!pos)
1991 return -EINVAL;
1992
1993 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1994 control |= PCI_PRI_CTRL_RESET;
1995 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1996
1997 return 0;
1998 }
1999
2000 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2001 {
2002 bool reset_enable;
2003 int reqs, ret;
2004
2005 /* FIXME: Hardcode number of outstanding requests for now */
2006 reqs = 32;
2007 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2008 reqs = 1;
2009 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2010
2011 /* Only allow access to user-accessible pages */
2012 ret = pci_enable_pasid(pdev, 0);
2013 if (ret)
2014 goto out_err;
2015
2016 /* First reset the PRI state of the device */
2017 ret = pci_reset_pri(pdev);
2018 if (ret)
2019 goto out_err;
2020
2021 /* Enable PRI */
2022 ret = pci_enable_pri(pdev, reqs);
2023 if (ret)
2024 goto out_err;
2025
2026 if (reset_enable) {
2027 ret = pri_reset_while_enabled(pdev);
2028 if (ret)
2029 goto out_err;
2030 }
2031
2032 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2033 if (ret)
2034 goto out_err;
2035
2036 return 0;
2037
2038 out_err:
2039 pci_disable_pri(pdev);
2040 pci_disable_pasid(pdev);
2041
2042 return ret;
2043 }
2044
2045 /* FIXME: Move this to PCI code */
2046 #define PCI_PRI_TLP_OFF (1 << 15)
2047
2048 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2049 {
2050 u16 status;
2051 int pos;
2052
2053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2054 if (!pos)
2055 return false;
2056
2057 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2058
2059 return (status & PCI_PRI_TLP_OFF) ? true : false;
2060 }
2061
2062 /*
2063 * If a device is not yet associated with a domain, this function makes the
2064 * device visible in the domain
2065 */
2066 static int attach_device(struct device *dev,
2067 struct protection_domain *domain)
2068 {
2069 struct pci_dev *pdev;
2070 struct iommu_dev_data *dev_data;
2071 unsigned long flags;
2072 int ret;
2073
2074 dev_data = get_dev_data(dev);
2075
2076 if (!dev_is_pci(dev))
2077 goto skip_ats_check;
2078
2079 pdev = to_pci_dev(dev);
2080 if (domain->flags & PD_IOMMUV2_MASK) {
2081 if (!dev_data->passthrough)
2082 return -EINVAL;
2083
2084 if (dev_data->iommu_v2) {
2085 if (pdev_iommuv2_enable(pdev) != 0)
2086 return -EINVAL;
2087
2088 dev_data->ats.enabled = true;
2089 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2090 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2091 }
2092 } else if (amd_iommu_iotlb_sup &&
2093 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2094 dev_data->ats.enabled = true;
2095 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2096 }
2097
2098 skip_ats_check:
2099 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2100 ret = __attach_device(dev_data, domain);
2101 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2102
2103 /*
2104 * We might boot into a crash-kernel here. The crashed kernel
2105 * left the caches in the IOMMU dirty. So we have to flush
2106 * here to evict all dirty stuff.
2107 */
2108 domain_flush_tlb_pde(domain);
2109
2110 return ret;
2111 }
2112
2113 /*
2114 * Removes a device from a protection domain (unlocked)
2115 */
2116 static void __detach_device(struct iommu_dev_data *dev_data)
2117 {
2118 struct protection_domain *domain;
2119
2120 domain = dev_data->domain;
2121
2122 spin_lock(&domain->lock);
2123
2124 do_detach(dev_data);
2125
2126 spin_unlock(&domain->lock);
2127 }
2128
2129 /*
2130 * Removes a device from a protection domain (with devtable_lock held)
2131 */
2132 static void detach_device(struct device *dev)
2133 {
2134 struct protection_domain *domain;
2135 struct iommu_dev_data *dev_data;
2136 unsigned long flags;
2137
2138 dev_data = get_dev_data(dev);
2139 domain = dev_data->domain;
2140
2141 /*
2142 * First check if the device is still attached. It might already
2143 * be detached from its domain because the generic
2144 * iommu_detach_group code detached it and we try again here in
2145 * our alias handling.
2146 */
2147 if (WARN_ON(!dev_data->domain))
2148 return;
2149
2150 /* lock device table */
2151 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2152 __detach_device(dev_data);
2153 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2154
2155 if (!dev_is_pci(dev))
2156 return;
2157
2158 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2159 pdev_iommuv2_disable(to_pci_dev(dev));
2160 else if (dev_data->ats.enabled)
2161 pci_disable_ats(to_pci_dev(dev));
2162
2163 dev_data->ats.enabled = false;
2164 }
2165
2166 static int amd_iommu_add_device(struct device *dev)
2167 {
2168 struct iommu_dev_data *dev_data;
2169 struct iommu_domain *domain;
2170 struct amd_iommu *iommu;
2171 int ret, devid;
2172
2173 if (!check_device(dev) || get_dev_data(dev))
2174 return 0;
2175
2176 devid = get_device_id(dev);
2177 if (devid < 0)
2178 return devid;
2179
2180 iommu = amd_iommu_rlookup_table[devid];
2181
2182 ret = iommu_init_device(dev);
2183 if (ret) {
2184 if (ret != -ENOTSUPP)
2185 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2186 dev_name(dev));
2187
2188 iommu_ignore_device(dev);
2189 dev->dma_ops = &dma_direct_ops;
2190 goto out;
2191 }
2192 init_iommu_group(dev);
2193
2194 dev_data = get_dev_data(dev);
2195
2196 BUG_ON(!dev_data);
2197
2198 if (iommu_pass_through || dev_data->iommu_v2)
2199 iommu_request_dm_for_dev(dev);
2200
2201 /* Domains are initialized for this device - have a look what we ended up with */
2202 domain = iommu_get_domain_for_dev(dev);
2203 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2204 dev_data->passthrough = true;
2205 else
2206 dev->dma_ops = &amd_iommu_dma_ops;
2207
2208 out:
2209 iommu_completion_wait(iommu);
2210
2211 return 0;
2212 }
2213
2214 static void amd_iommu_remove_device(struct device *dev)
2215 {
2216 struct amd_iommu *iommu;
2217 int devid;
2218
2219 if (!check_device(dev))
2220 return;
2221
2222 devid = get_device_id(dev);
2223 if (devid < 0)
2224 return;
2225
2226 iommu = amd_iommu_rlookup_table[devid];
2227
2228 iommu_uninit_device(dev);
2229 iommu_completion_wait(iommu);
2230 }
2231
2232 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2233 {
2234 if (dev_is_pci(dev))
2235 return pci_device_group(dev);
2236
2237 return acpihid_device_group(dev);
2238 }
2239
2240 /*****************************************************************************
2241 *
2242 * The next functions belong to the dma_ops mapping/unmapping code.
2243 *
2244 *****************************************************************************/
2245
2246 /*
2247 * In the dma_ops path we only have the struct device. This function
2248 * finds the corresponding IOMMU, the protection domain and the
2249 * requestor id for a given device.
2250 * If the device is not yet associated with a domain this is also done
2251 * in this function.
2252 */
2253 static struct protection_domain *get_domain(struct device *dev)
2254 {
2255 struct protection_domain *domain;
2256 struct iommu_domain *io_domain;
2257
2258 if (!check_device(dev))
2259 return ERR_PTR(-EINVAL);
2260
2261 domain = get_dev_data(dev)->domain;
2262 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2263 get_dev_data(dev)->defer_attach = false;
2264 io_domain = iommu_get_domain_for_dev(dev);
2265 domain = to_pdomain(io_domain);
2266 attach_device(dev, domain);
2267 }
2268 if (domain == NULL)
2269 return ERR_PTR(-EBUSY);
2270
2271 if (!dma_ops_domain(domain))
2272 return ERR_PTR(-EBUSY);
2273
2274 return domain;
2275 }
2276
2277 static void update_device_table(struct protection_domain *domain)
2278 {
2279 struct iommu_dev_data *dev_data;
2280
2281 list_for_each_entry(dev_data, &domain->dev_list, list) {
2282 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2283 dev_data->iommu_v2);
2284
2285 if (dev_data->devid == dev_data->alias)
2286 continue;
2287
2288 /* There is an alias, update device table entry for it */
2289 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2290 dev_data->iommu_v2);
2291 }
2292 }
2293
2294 static void update_domain(struct protection_domain *domain)
2295 {
2296 if (!domain->updated)
2297 return;
2298
2299 update_device_table(domain);
2300
2301 domain_flush_devices(domain);
2302 domain_flush_tlb_pde(domain);
2303
2304 domain->updated = false;
2305 }
2306
2307 static int dir2prot(enum dma_data_direction direction)
2308 {
2309 if (direction == DMA_TO_DEVICE)
2310 return IOMMU_PROT_IR;
2311 else if (direction == DMA_FROM_DEVICE)
2312 return IOMMU_PROT_IW;
2313 else if (direction == DMA_BIDIRECTIONAL)
2314 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2315 else
2316 return 0;
2317 }
2318
2319 /*
2320 * This function contains common code for mapping of a physically
2321 * contiguous memory region into DMA address space. It is used by all
2322 * mapping functions provided with this IOMMU driver.
2323 * Must be called with the domain lock held.
2324 */
2325 static dma_addr_t __map_single(struct device *dev,
2326 struct dma_ops_domain *dma_dom,
2327 phys_addr_t paddr,
2328 size_t size,
2329 enum dma_data_direction direction,
2330 u64 dma_mask)
2331 {
2332 dma_addr_t offset = paddr & ~PAGE_MASK;
2333 dma_addr_t address, start, ret;
2334 unsigned int pages;
2335 int prot = 0;
2336 int i;
2337
2338 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2339 paddr &= PAGE_MASK;
2340
2341 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2342 if (address == AMD_IOMMU_MAPPING_ERROR)
2343 goto out;
2344
2345 prot = dir2prot(direction);
2346
2347 start = address;
2348 for (i = 0; i < pages; ++i) {
2349 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2350 PAGE_SIZE, prot, GFP_ATOMIC);
2351 if (ret)
2352 goto out_unmap;
2353
2354 paddr += PAGE_SIZE;
2355 start += PAGE_SIZE;
2356 }
2357 address += offset;
2358
2359 if (unlikely(amd_iommu_np_cache)) {
2360 domain_flush_pages(&dma_dom->domain, address, size);
2361 domain_flush_complete(&dma_dom->domain);
2362 }
2363
2364 out:
2365 return address;
2366
2367 out_unmap:
2368
2369 for (--i; i >= 0; --i) {
2370 start -= PAGE_SIZE;
2371 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2372 }
2373
2374 domain_flush_tlb(&dma_dom->domain);
2375 domain_flush_complete(&dma_dom->domain);
2376
2377 dma_ops_free_iova(dma_dom, address, pages);
2378
2379 return AMD_IOMMU_MAPPING_ERROR;
2380 }
2381
2382 /*
2383 * Does the reverse of the __map_single function. Must be called with
2384 * the domain lock held too
2385 */
2386 static void __unmap_single(struct dma_ops_domain *dma_dom,
2387 dma_addr_t dma_addr,
2388 size_t size,
2389 int dir)
2390 {
2391 dma_addr_t i, start;
2392 unsigned int pages;
2393
2394 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2395 dma_addr &= PAGE_MASK;
2396 start = dma_addr;
2397
2398 for (i = 0; i < pages; ++i) {
2399 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2400 start += PAGE_SIZE;
2401 }
2402
2403 if (amd_iommu_unmap_flush) {
2404 domain_flush_tlb(&dma_dom->domain);
2405 domain_flush_complete(&dma_dom->domain);
2406 dma_ops_free_iova(dma_dom, dma_addr, pages);
2407 } else {
2408 pages = __roundup_pow_of_two(pages);
2409 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2410 }
2411 }
2412
2413 /*
2414 * The exported map_single function for dma_ops.
2415 */
2416 static dma_addr_t map_page(struct device *dev, struct page *page,
2417 unsigned long offset, size_t size,
2418 enum dma_data_direction dir,
2419 unsigned long attrs)
2420 {
2421 phys_addr_t paddr = page_to_phys(page) + offset;
2422 struct protection_domain *domain;
2423 struct dma_ops_domain *dma_dom;
2424 u64 dma_mask;
2425
2426 domain = get_domain(dev);
2427 if (PTR_ERR(domain) == -EINVAL)
2428 return (dma_addr_t)paddr;
2429 else if (IS_ERR(domain))
2430 return AMD_IOMMU_MAPPING_ERROR;
2431
2432 dma_mask = *dev->dma_mask;
2433 dma_dom = to_dma_ops_domain(domain);
2434
2435 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2436 }
2437
2438 /*
2439 * The exported unmap_single function for dma_ops.
2440 */
2441 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2442 enum dma_data_direction dir, unsigned long attrs)
2443 {
2444 struct protection_domain *domain;
2445 struct dma_ops_domain *dma_dom;
2446
2447 domain = get_domain(dev);
2448 if (IS_ERR(domain))
2449 return;
2450
2451 dma_dom = to_dma_ops_domain(domain);
2452
2453 __unmap_single(dma_dom, dma_addr, size, dir);
2454 }
2455
2456 static int sg_num_pages(struct device *dev,
2457 struct scatterlist *sglist,
2458 int nelems)
2459 {
2460 unsigned long mask, boundary_size;
2461 struct scatterlist *s;
2462 int i, npages = 0;
2463
2464 mask = dma_get_seg_boundary(dev);
2465 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2466 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2467
2468 for_each_sg(sglist, s, nelems, i) {
2469 int p, n;
2470
2471 s->dma_address = npages << PAGE_SHIFT;
2472 p = npages % boundary_size;
2473 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2474 if (p + n > boundary_size)
2475 npages += boundary_size - p;
2476 npages += n;
2477 }
2478
2479 return npages;
2480 }
2481
2482 /*
2483 * The exported map_sg function for dma_ops (handles scatter-gather
2484 * lists).
2485 */
2486 static int map_sg(struct device *dev, struct scatterlist *sglist,
2487 int nelems, enum dma_data_direction direction,
2488 unsigned long attrs)
2489 {
2490 int mapped_pages = 0, npages = 0, prot = 0, i;
2491 struct protection_domain *domain;
2492 struct dma_ops_domain *dma_dom;
2493 struct scatterlist *s;
2494 unsigned long address;
2495 u64 dma_mask;
2496
2497 domain = get_domain(dev);
2498 if (IS_ERR(domain))
2499 return 0;
2500
2501 dma_dom = to_dma_ops_domain(domain);
2502 dma_mask = *dev->dma_mask;
2503
2504 npages = sg_num_pages(dev, sglist, nelems);
2505
2506 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2507 if (address == AMD_IOMMU_MAPPING_ERROR)
2508 goto out_err;
2509
2510 prot = dir2prot(direction);
2511
2512 /* Map all sg entries */
2513 for_each_sg(sglist, s, nelems, i) {
2514 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2515
2516 for (j = 0; j < pages; ++j) {
2517 unsigned long bus_addr, phys_addr;
2518 int ret;
2519
2520 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2521 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2522 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2523 if (ret)
2524 goto out_unmap;
2525
2526 mapped_pages += 1;
2527 }
2528 }
2529
2530 /* Everything is mapped - write the right values into s->dma_address */
2531 for_each_sg(sglist, s, nelems, i) {
2532 s->dma_address += address + s->offset;
2533 s->dma_length = s->length;
2534 }
2535
2536 return nelems;
2537
2538 out_unmap:
2539 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2540 dev_name(dev), npages);
2541
2542 for_each_sg(sglist, s, nelems, i) {
2543 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2544
2545 for (j = 0; j < pages; ++j) {
2546 unsigned long bus_addr;
2547
2548 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2549 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2550
2551 if (--mapped_pages)
2552 goto out_free_iova;
2553 }
2554 }
2555
2556 out_free_iova:
2557 free_iova_fast(&dma_dom->iovad, address, npages);
2558
2559 out_err:
2560 return 0;
2561 }
2562
2563 /*
2564 * The exported map_sg function for dma_ops (handles scatter-gather
2565 * lists).
2566 */
2567 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2568 int nelems, enum dma_data_direction dir,
2569 unsigned long attrs)
2570 {
2571 struct protection_domain *domain;
2572 struct dma_ops_domain *dma_dom;
2573 unsigned long startaddr;
2574 int npages = 2;
2575
2576 domain = get_domain(dev);
2577 if (IS_ERR(domain))
2578 return;
2579
2580 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2581 dma_dom = to_dma_ops_domain(domain);
2582 npages = sg_num_pages(dev, sglist, nelems);
2583
2584 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2585 }
2586
2587 /*
2588 * The exported alloc_coherent function for dma_ops.
2589 */
2590 static void *alloc_coherent(struct device *dev, size_t size,
2591 dma_addr_t *dma_addr, gfp_t flag,
2592 unsigned long attrs)
2593 {
2594 u64 dma_mask = dev->coherent_dma_mask;
2595 struct protection_domain *domain;
2596 struct dma_ops_domain *dma_dom;
2597 struct page *page;
2598
2599 domain = get_domain(dev);
2600 if (PTR_ERR(domain) == -EINVAL) {
2601 page = alloc_pages(flag, get_order(size));
2602 *dma_addr = page_to_phys(page);
2603 return page_address(page);
2604 } else if (IS_ERR(domain))
2605 return NULL;
2606
2607 dma_dom = to_dma_ops_domain(domain);
2608 size = PAGE_ALIGN(size);
2609 dma_mask = dev->coherent_dma_mask;
2610 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2611 flag |= __GFP_ZERO;
2612
2613 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2614 if (!page) {
2615 if (!gfpflags_allow_blocking(flag))
2616 return NULL;
2617
2618 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2619 get_order(size), flag & __GFP_NOWARN);
2620 if (!page)
2621 return NULL;
2622 }
2623
2624 if (!dma_mask)
2625 dma_mask = *dev->dma_mask;
2626
2627 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2628 size, DMA_BIDIRECTIONAL, dma_mask);
2629
2630 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2631 goto out_free;
2632
2633 return page_address(page);
2634
2635 out_free:
2636
2637 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2638 __free_pages(page, get_order(size));
2639
2640 return NULL;
2641 }
2642
2643 /*
2644 * The exported free_coherent function for dma_ops.
2645 */
2646 static void free_coherent(struct device *dev, size_t size,
2647 void *virt_addr, dma_addr_t dma_addr,
2648 unsigned long attrs)
2649 {
2650 struct protection_domain *domain;
2651 struct dma_ops_domain *dma_dom;
2652 struct page *page;
2653
2654 page = virt_to_page(virt_addr);
2655 size = PAGE_ALIGN(size);
2656
2657 domain = get_domain(dev);
2658 if (IS_ERR(domain))
2659 goto free_mem;
2660
2661 dma_dom = to_dma_ops_domain(domain);
2662
2663 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2664
2665 free_mem:
2666 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2667 __free_pages(page, get_order(size));
2668 }
2669
2670 /*
2671 * This function is called by the DMA layer to find out if we can handle a
2672 * particular device. It is part of the dma_ops.
2673 */
2674 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2675 {
2676 if (!dma_direct_supported(dev, mask))
2677 return 0;
2678 return check_device(dev);
2679 }
2680
2681 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2682 {
2683 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2684 }
2685
2686 static const struct dma_map_ops amd_iommu_dma_ops = {
2687 .alloc = alloc_coherent,
2688 .free = free_coherent,
2689 .map_page = map_page,
2690 .unmap_page = unmap_page,
2691 .map_sg = map_sg,
2692 .unmap_sg = unmap_sg,
2693 .dma_supported = amd_iommu_dma_supported,
2694 .mapping_error = amd_iommu_mapping_error,
2695 };
2696
2697 static int init_reserved_iova_ranges(void)
2698 {
2699 struct pci_dev *pdev = NULL;
2700 struct iova *val;
2701
2702 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2703
2704 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2705 &reserved_rbtree_key);
2706
2707 /* MSI memory range */
2708 val = reserve_iova(&reserved_iova_ranges,
2709 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2710 if (!val) {
2711 pr_err("Reserving MSI range failed\n");
2712 return -ENOMEM;
2713 }
2714
2715 /* HT memory range */
2716 val = reserve_iova(&reserved_iova_ranges,
2717 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2718 if (!val) {
2719 pr_err("Reserving HT range failed\n");
2720 return -ENOMEM;
2721 }
2722
2723 /*
2724 * Memory used for PCI resources
2725 * FIXME: Check whether we can reserve the PCI-hole completly
2726 */
2727 for_each_pci_dev(pdev) {
2728 int i;
2729
2730 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2731 struct resource *r = &pdev->resource[i];
2732
2733 if (!(r->flags & IORESOURCE_MEM))
2734 continue;
2735
2736 val = reserve_iova(&reserved_iova_ranges,
2737 IOVA_PFN(r->start),
2738 IOVA_PFN(r->end));
2739 if (!val) {
2740 pr_err("Reserve pci-resource range failed\n");
2741 return -ENOMEM;
2742 }
2743 }
2744 }
2745
2746 return 0;
2747 }
2748
2749 int __init amd_iommu_init_api(void)
2750 {
2751 int ret, err = 0;
2752
2753 ret = iova_cache_get();
2754 if (ret)
2755 return ret;
2756
2757 ret = init_reserved_iova_ranges();
2758 if (ret)
2759 return ret;
2760
2761 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2762 if (err)
2763 return err;
2764 #ifdef CONFIG_ARM_AMBA
2765 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2766 if (err)
2767 return err;
2768 #endif
2769 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2770 if (err)
2771 return err;
2772
2773 return 0;
2774 }
2775
2776 int __init amd_iommu_init_dma_ops(void)
2777 {
2778 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2779 iommu_detected = 1;
2780
2781 /*
2782 * In case we don't initialize SWIOTLB (actually the common case
2783 * when AMD IOMMU is enabled and SME is not active), make sure there
2784 * are global dma_ops set as a fall-back for devices not handled by
2785 * this driver (for example non-PCI devices). When SME is active,
2786 * make sure that swiotlb variable remains set so the global dma_ops
2787 * continue to be SWIOTLB.
2788 */
2789 if (!swiotlb)
2790 dma_ops = &dma_direct_ops;
2791
2792 if (amd_iommu_unmap_flush)
2793 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2794 else
2795 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2796
2797 return 0;
2798
2799 }
2800
2801 /*****************************************************************************
2802 *
2803 * The following functions belong to the exported interface of AMD IOMMU
2804 *
2805 * This interface allows access to lower level functions of the IOMMU
2806 * like protection domain handling and assignement of devices to domains
2807 * which is not possible with the dma_ops interface.
2808 *
2809 *****************************************************************************/
2810
2811 static void cleanup_domain(struct protection_domain *domain)
2812 {
2813 struct iommu_dev_data *entry;
2814 unsigned long flags;
2815
2816 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2817
2818 while (!list_empty(&domain->dev_list)) {
2819 entry = list_first_entry(&domain->dev_list,
2820 struct iommu_dev_data, list);
2821 BUG_ON(!entry->domain);
2822 __detach_device(entry);
2823 }
2824
2825 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2826 }
2827
2828 static void protection_domain_free(struct protection_domain *domain)
2829 {
2830 if (!domain)
2831 return;
2832
2833 del_domain_from_list(domain);
2834
2835 if (domain->id)
2836 domain_id_free(domain->id);
2837
2838 kfree(domain);
2839 }
2840
2841 static int protection_domain_init(struct protection_domain *domain)
2842 {
2843 spin_lock_init(&domain->lock);
2844 mutex_init(&domain->api_lock);
2845 domain->id = domain_id_alloc();
2846 if (!domain->id)
2847 return -ENOMEM;
2848 INIT_LIST_HEAD(&domain->dev_list);
2849
2850 return 0;
2851 }
2852
2853 static struct protection_domain *protection_domain_alloc(void)
2854 {
2855 struct protection_domain *domain;
2856
2857 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2858 if (!domain)
2859 return NULL;
2860
2861 if (protection_domain_init(domain))
2862 goto out_err;
2863
2864 add_domain_to_list(domain);
2865
2866 return domain;
2867
2868 out_err:
2869 kfree(domain);
2870
2871 return NULL;
2872 }
2873
2874 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2875 {
2876 struct protection_domain *pdomain;
2877 struct dma_ops_domain *dma_domain;
2878
2879 switch (type) {
2880 case IOMMU_DOMAIN_UNMANAGED:
2881 pdomain = protection_domain_alloc();
2882 if (!pdomain)
2883 return NULL;
2884
2885 pdomain->mode = PAGE_MODE_3_LEVEL;
2886 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2887 if (!pdomain->pt_root) {
2888 protection_domain_free(pdomain);
2889 return NULL;
2890 }
2891
2892 pdomain->domain.geometry.aperture_start = 0;
2893 pdomain->domain.geometry.aperture_end = ~0ULL;
2894 pdomain->domain.geometry.force_aperture = true;
2895
2896 break;
2897 case IOMMU_DOMAIN_DMA:
2898 dma_domain = dma_ops_domain_alloc();
2899 if (!dma_domain) {
2900 pr_err("AMD-Vi: Failed to allocate\n");
2901 return NULL;
2902 }
2903 pdomain = &dma_domain->domain;
2904 break;
2905 case IOMMU_DOMAIN_IDENTITY:
2906 pdomain = protection_domain_alloc();
2907 if (!pdomain)
2908 return NULL;
2909
2910 pdomain->mode = PAGE_MODE_NONE;
2911 break;
2912 default:
2913 return NULL;
2914 }
2915
2916 return &pdomain->domain;
2917 }
2918
2919 static void amd_iommu_domain_free(struct iommu_domain *dom)
2920 {
2921 struct protection_domain *domain;
2922 struct dma_ops_domain *dma_dom;
2923
2924 domain = to_pdomain(dom);
2925
2926 if (domain->dev_cnt > 0)
2927 cleanup_domain(domain);
2928
2929 BUG_ON(domain->dev_cnt != 0);
2930
2931 if (!dom)
2932 return;
2933
2934 switch (dom->type) {
2935 case IOMMU_DOMAIN_DMA:
2936 /* Now release the domain */
2937 dma_dom = to_dma_ops_domain(domain);
2938 dma_ops_domain_free(dma_dom);
2939 break;
2940 default:
2941 if (domain->mode != PAGE_MODE_NONE)
2942 free_pagetable(domain);
2943
2944 if (domain->flags & PD_IOMMUV2_MASK)
2945 free_gcr3_table(domain);
2946
2947 protection_domain_free(domain);
2948 break;
2949 }
2950 }
2951
2952 static void amd_iommu_detach_device(struct iommu_domain *dom,
2953 struct device *dev)
2954 {
2955 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2956 struct amd_iommu *iommu;
2957 int devid;
2958
2959 if (!check_device(dev))
2960 return;
2961
2962 devid = get_device_id(dev);
2963 if (devid < 0)
2964 return;
2965
2966 if (dev_data->domain != NULL)
2967 detach_device(dev);
2968
2969 iommu = amd_iommu_rlookup_table[devid];
2970 if (!iommu)
2971 return;
2972
2973 #ifdef CONFIG_IRQ_REMAP
2974 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2975 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2976 dev_data->use_vapic = 0;
2977 #endif
2978
2979 iommu_completion_wait(iommu);
2980 }
2981
2982 static int amd_iommu_attach_device(struct iommu_domain *dom,
2983 struct device *dev)
2984 {
2985 struct protection_domain *domain = to_pdomain(dom);
2986 struct iommu_dev_data *dev_data;
2987 struct amd_iommu *iommu;
2988 int ret;
2989
2990 if (!check_device(dev))
2991 return -EINVAL;
2992
2993 dev_data = dev->archdata.iommu;
2994
2995 iommu = amd_iommu_rlookup_table[dev_data->devid];
2996 if (!iommu)
2997 return -EINVAL;
2998
2999 if (dev_data->domain)
3000 detach_device(dev);
3001
3002 ret = attach_device(dev, domain);
3003
3004 #ifdef CONFIG_IRQ_REMAP
3005 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3006 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3007 dev_data->use_vapic = 1;
3008 else
3009 dev_data->use_vapic = 0;
3010 }
3011 #endif
3012
3013 iommu_completion_wait(iommu);
3014
3015 return ret;
3016 }
3017
3018 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3019 phys_addr_t paddr, size_t page_size, int iommu_prot)
3020 {
3021 struct protection_domain *domain = to_pdomain(dom);
3022 int prot = 0;
3023 int ret;
3024
3025 if (domain->mode == PAGE_MODE_NONE)
3026 return -EINVAL;
3027
3028 if (iommu_prot & IOMMU_READ)
3029 prot |= IOMMU_PROT_IR;
3030 if (iommu_prot & IOMMU_WRITE)
3031 prot |= IOMMU_PROT_IW;
3032
3033 mutex_lock(&domain->api_lock);
3034 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3035 mutex_unlock(&domain->api_lock);
3036
3037 return ret;
3038 }
3039
3040 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3041 size_t page_size)
3042 {
3043 struct protection_domain *domain = to_pdomain(dom);
3044 size_t unmap_size;
3045
3046 if (domain->mode == PAGE_MODE_NONE)
3047 return 0;
3048
3049 mutex_lock(&domain->api_lock);
3050 unmap_size = iommu_unmap_page(domain, iova, page_size);
3051 mutex_unlock(&domain->api_lock);
3052
3053 return unmap_size;
3054 }
3055
3056 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3057 dma_addr_t iova)
3058 {
3059 struct protection_domain *domain = to_pdomain(dom);
3060 unsigned long offset_mask, pte_pgsize;
3061 u64 *pte, __pte;
3062
3063 if (domain->mode == PAGE_MODE_NONE)
3064 return iova;
3065
3066 pte = fetch_pte(domain, iova, &pte_pgsize);
3067
3068 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3069 return 0;
3070
3071 offset_mask = pte_pgsize - 1;
3072 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3073
3074 return (__pte & ~offset_mask) | (iova & offset_mask);
3075 }
3076
3077 static bool amd_iommu_capable(enum iommu_cap cap)
3078 {
3079 switch (cap) {
3080 case IOMMU_CAP_CACHE_COHERENCY:
3081 return true;
3082 case IOMMU_CAP_INTR_REMAP:
3083 return (irq_remapping_enabled == 1);
3084 case IOMMU_CAP_NOEXEC:
3085 return false;
3086 default:
3087 break;
3088 }
3089
3090 return false;
3091 }
3092
3093 static void amd_iommu_get_resv_regions(struct device *dev,
3094 struct list_head *head)
3095 {
3096 struct iommu_resv_region *region;
3097 struct unity_map_entry *entry;
3098 int devid;
3099
3100 devid = get_device_id(dev);
3101 if (devid < 0)
3102 return;
3103
3104 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3105 size_t length;
3106 int prot = 0;
3107
3108 if (devid < entry->devid_start || devid > entry->devid_end)
3109 continue;
3110
3111 length = entry->address_end - entry->address_start;
3112 if (entry->prot & IOMMU_PROT_IR)
3113 prot |= IOMMU_READ;
3114 if (entry->prot & IOMMU_PROT_IW)
3115 prot |= IOMMU_WRITE;
3116
3117 region = iommu_alloc_resv_region(entry->address_start,
3118 length, prot,
3119 IOMMU_RESV_DIRECT);
3120 if (!region) {
3121 pr_err("Out of memory allocating dm-regions for %s\n",
3122 dev_name(dev));
3123 return;
3124 }
3125 list_add_tail(&region->list, head);
3126 }
3127
3128 region = iommu_alloc_resv_region(MSI_RANGE_START,
3129 MSI_RANGE_END - MSI_RANGE_START + 1,
3130 0, IOMMU_RESV_MSI);
3131 if (!region)
3132 return;
3133 list_add_tail(&region->list, head);
3134
3135 region = iommu_alloc_resv_region(HT_RANGE_START,
3136 HT_RANGE_END - HT_RANGE_START + 1,
3137 0, IOMMU_RESV_RESERVED);
3138 if (!region)
3139 return;
3140 list_add_tail(&region->list, head);
3141 }
3142
3143 static void amd_iommu_put_resv_regions(struct device *dev,
3144 struct list_head *head)
3145 {
3146 struct iommu_resv_region *entry, *next;
3147
3148 list_for_each_entry_safe(entry, next, head, list)
3149 kfree(entry);
3150 }
3151
3152 static void amd_iommu_apply_resv_region(struct device *dev,
3153 struct iommu_domain *domain,
3154 struct iommu_resv_region *region)
3155 {
3156 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3157 unsigned long start, end;
3158
3159 start = IOVA_PFN(region->start);
3160 end = IOVA_PFN(region->start + region->length - 1);
3161
3162 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3163 }
3164
3165 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3166 struct device *dev)
3167 {
3168 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3169 return dev_data->defer_attach;
3170 }
3171
3172 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3173 {
3174 struct protection_domain *dom = to_pdomain(domain);
3175
3176 domain_flush_tlb_pde(dom);
3177 domain_flush_complete(dom);
3178 }
3179
3180 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3181 unsigned long iova, size_t size)
3182 {
3183 }
3184
3185 const struct iommu_ops amd_iommu_ops = {
3186 .capable = amd_iommu_capable,
3187 .domain_alloc = amd_iommu_domain_alloc,
3188 .domain_free = amd_iommu_domain_free,
3189 .attach_dev = amd_iommu_attach_device,
3190 .detach_dev = amd_iommu_detach_device,
3191 .map = amd_iommu_map,
3192 .unmap = amd_iommu_unmap,
3193 .iova_to_phys = amd_iommu_iova_to_phys,
3194 .add_device = amd_iommu_add_device,
3195 .remove_device = amd_iommu_remove_device,
3196 .device_group = amd_iommu_device_group,
3197 .get_resv_regions = amd_iommu_get_resv_regions,
3198 .put_resv_regions = amd_iommu_put_resv_regions,
3199 .apply_resv_region = amd_iommu_apply_resv_region,
3200 .is_attach_deferred = amd_iommu_is_attach_deferred,
3201 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3202 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3203 .iotlb_range_add = amd_iommu_iotlb_range_add,
3204 .iotlb_sync = amd_iommu_flush_iotlb_all,
3205 };
3206
3207 /*****************************************************************************
3208 *
3209 * The next functions do a basic initialization of IOMMU for pass through
3210 * mode
3211 *
3212 * In passthrough mode the IOMMU is initialized and enabled but not used for
3213 * DMA-API translation.
3214 *
3215 *****************************************************************************/
3216
3217 /* IOMMUv2 specific functions */
3218 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3219 {
3220 return atomic_notifier_chain_register(&ppr_notifier, nb);
3221 }
3222 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3223
3224 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3225 {
3226 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3227 }
3228 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3229
3230 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3231 {
3232 struct protection_domain *domain = to_pdomain(dom);
3233 unsigned long flags;
3234
3235 spin_lock_irqsave(&domain->lock, flags);
3236
3237 /* Update data structure */
3238 domain->mode = PAGE_MODE_NONE;
3239 domain->updated = true;
3240
3241 /* Make changes visible to IOMMUs */
3242 update_domain(domain);
3243
3244 /* Page-table is not visible to IOMMU anymore, so free it */
3245 free_pagetable(domain);
3246
3247 spin_unlock_irqrestore(&domain->lock, flags);
3248 }
3249 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3250
3251 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3252 {
3253 struct protection_domain *domain = to_pdomain(dom);
3254 unsigned long flags;
3255 int levels, ret;
3256
3257 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3258 return -EINVAL;
3259
3260 /* Number of GCR3 table levels required */
3261 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3262 levels += 1;
3263
3264 if (levels > amd_iommu_max_glx_val)
3265 return -EINVAL;
3266
3267 spin_lock_irqsave(&domain->lock, flags);
3268
3269 /*
3270 * Save us all sanity checks whether devices already in the
3271 * domain support IOMMUv2. Just force that the domain has no
3272 * devices attached when it is switched into IOMMUv2 mode.
3273 */
3274 ret = -EBUSY;
3275 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3276 goto out;
3277
3278 ret = -ENOMEM;
3279 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3280 if (domain->gcr3_tbl == NULL)
3281 goto out;
3282
3283 domain->glx = levels;
3284 domain->flags |= PD_IOMMUV2_MASK;
3285 domain->updated = true;
3286
3287 update_domain(domain);
3288
3289 ret = 0;
3290
3291 out:
3292 spin_unlock_irqrestore(&domain->lock, flags);
3293
3294 return ret;
3295 }
3296 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3297
3298 static int __flush_pasid(struct protection_domain *domain, int pasid,
3299 u64 address, bool size)
3300 {
3301 struct iommu_dev_data *dev_data;
3302 struct iommu_cmd cmd;
3303 int i, ret;
3304
3305 if (!(domain->flags & PD_IOMMUV2_MASK))
3306 return -EINVAL;
3307
3308 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3309
3310 /*
3311 * IOMMU TLB needs to be flushed before Device TLB to
3312 * prevent device TLB refill from IOMMU TLB
3313 */
3314 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3315 if (domain->dev_iommu[i] == 0)
3316 continue;
3317
3318 ret = iommu_queue_command(amd_iommus[i], &cmd);
3319 if (ret != 0)
3320 goto out;
3321 }
3322
3323 /* Wait until IOMMU TLB flushes are complete */
3324 domain_flush_complete(domain);
3325
3326 /* Now flush device TLBs */
3327 list_for_each_entry(dev_data, &domain->dev_list, list) {
3328 struct amd_iommu *iommu;
3329 int qdep;
3330
3331 /*
3332 There might be non-IOMMUv2 capable devices in an IOMMUv2
3333 * domain.
3334 */
3335 if (!dev_data->ats.enabled)
3336 continue;
3337
3338 qdep = dev_data->ats.qdep;
3339 iommu = amd_iommu_rlookup_table[dev_data->devid];
3340
3341 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3342 qdep, address, size);
3343
3344 ret = iommu_queue_command(iommu, &cmd);
3345 if (ret != 0)
3346 goto out;
3347 }
3348
3349 /* Wait until all device TLBs are flushed */
3350 domain_flush_complete(domain);
3351
3352 ret = 0;
3353
3354 out:
3355
3356 return ret;
3357 }
3358
3359 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3360 u64 address)
3361 {
3362 return __flush_pasid(domain, pasid, address, false);
3363 }
3364
3365 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3366 u64 address)
3367 {
3368 struct protection_domain *domain = to_pdomain(dom);
3369 unsigned long flags;
3370 int ret;
3371
3372 spin_lock_irqsave(&domain->lock, flags);
3373 ret = __amd_iommu_flush_page(domain, pasid, address);
3374 spin_unlock_irqrestore(&domain->lock, flags);
3375
3376 return ret;
3377 }
3378 EXPORT_SYMBOL(amd_iommu_flush_page);
3379
3380 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3381 {
3382 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3383 true);
3384 }
3385
3386 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3387 {
3388 struct protection_domain *domain = to_pdomain(dom);
3389 unsigned long flags;
3390 int ret;
3391
3392 spin_lock_irqsave(&domain->lock, flags);
3393 ret = __amd_iommu_flush_tlb(domain, pasid);
3394 spin_unlock_irqrestore(&domain->lock, flags);
3395
3396 return ret;
3397 }
3398 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3399
3400 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3401 {
3402 int index;
3403 u64 *pte;
3404
3405 while (true) {
3406
3407 index = (pasid >> (9 * level)) & 0x1ff;
3408 pte = &root[index];
3409
3410 if (level == 0)
3411 break;
3412
3413 if (!(*pte & GCR3_VALID)) {
3414 if (!alloc)
3415 return NULL;
3416
3417 root = (void *)get_zeroed_page(GFP_ATOMIC);
3418 if (root == NULL)
3419 return NULL;
3420
3421 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3422 }
3423
3424 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3425
3426 level -= 1;
3427 }
3428
3429 return pte;
3430 }
3431
3432 static int __set_gcr3(struct protection_domain *domain, int pasid,
3433 unsigned long cr3)
3434 {
3435 u64 *pte;
3436
3437 if (domain->mode != PAGE_MODE_NONE)
3438 return -EINVAL;
3439
3440 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3441 if (pte == NULL)
3442 return -ENOMEM;
3443
3444 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3445
3446 return __amd_iommu_flush_tlb(domain, pasid);
3447 }
3448
3449 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3450 {
3451 u64 *pte;
3452
3453 if (domain->mode != PAGE_MODE_NONE)
3454 return -EINVAL;
3455
3456 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3457 if (pte == NULL)
3458 return 0;
3459
3460 *pte = 0;
3461
3462 return __amd_iommu_flush_tlb(domain, pasid);
3463 }
3464
3465 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3466 unsigned long cr3)
3467 {
3468 struct protection_domain *domain = to_pdomain(dom);
3469 unsigned long flags;
3470 int ret;
3471
3472 spin_lock_irqsave(&domain->lock, flags);
3473 ret = __set_gcr3(domain, pasid, cr3);
3474 spin_unlock_irqrestore(&domain->lock, flags);
3475
3476 return ret;
3477 }
3478 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3479
3480 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3481 {
3482 struct protection_domain *domain = to_pdomain(dom);
3483 unsigned long flags;
3484 int ret;
3485
3486 spin_lock_irqsave(&domain->lock, flags);
3487 ret = __clear_gcr3(domain, pasid);
3488 spin_unlock_irqrestore(&domain->lock, flags);
3489
3490 return ret;
3491 }
3492 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3493
3494 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3495 int status, int tag)
3496 {
3497 struct iommu_dev_data *dev_data;
3498 struct amd_iommu *iommu;
3499 struct iommu_cmd cmd;
3500
3501 dev_data = get_dev_data(&pdev->dev);
3502 iommu = amd_iommu_rlookup_table[dev_data->devid];
3503
3504 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3505 tag, dev_data->pri_tlp);
3506
3507 return iommu_queue_command(iommu, &cmd);
3508 }
3509 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3510
3511 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3512 {
3513 struct protection_domain *pdomain;
3514
3515 pdomain = get_domain(&pdev->dev);
3516 if (IS_ERR(pdomain))
3517 return NULL;
3518
3519 /* Only return IOMMUv2 domains */
3520 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3521 return NULL;
3522
3523 return &pdomain->domain;
3524 }
3525 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3526
3527 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3528 {
3529 struct iommu_dev_data *dev_data;
3530
3531 if (!amd_iommu_v2_supported())
3532 return;
3533
3534 dev_data = get_dev_data(&pdev->dev);
3535 dev_data->errata |= (1 << erratum);
3536 }
3537 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3538
3539 int amd_iommu_device_info(struct pci_dev *pdev,
3540 struct amd_iommu_device_info *info)
3541 {
3542 int max_pasids;
3543 int pos;
3544
3545 if (pdev == NULL || info == NULL)
3546 return -EINVAL;
3547
3548 if (!amd_iommu_v2_supported())
3549 return -EINVAL;
3550
3551 memset(info, 0, sizeof(*info));
3552
3553 if (!pci_ats_disabled()) {
3554 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3555 if (pos)
3556 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3557 }
3558
3559 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3560 if (pos)
3561 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3562
3563 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3564 if (pos) {
3565 int features;
3566
3567 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3568 max_pasids = min(max_pasids, (1 << 20));
3569
3570 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3571 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3572
3573 features = pci_pasid_features(pdev);
3574 if (features & PCI_PASID_CAP_EXEC)
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3576 if (features & PCI_PASID_CAP_PRIV)
3577 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3578 }
3579
3580 return 0;
3581 }
3582 EXPORT_SYMBOL(amd_iommu_device_info);
3583
3584 #ifdef CONFIG_IRQ_REMAP
3585
3586 /*****************************************************************************
3587 *
3588 * Interrupt Remapping Implementation
3589 *
3590 *****************************************************************************/
3591
3592 static struct irq_chip amd_ir_chip;
3593 static DEFINE_SPINLOCK(iommu_table_lock);
3594
3595 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3596 {
3597 u64 dte;
3598
3599 dte = amd_iommu_dev_table[devid].data[2];
3600 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3601 dte |= iommu_virt_to_phys(table->table);
3602 dte |= DTE_IRQ_REMAP_INTCTL;
3603 dte |= DTE_IRQ_TABLE_LEN;
3604 dte |= DTE_IRQ_REMAP_ENABLE;
3605
3606 amd_iommu_dev_table[devid].data[2] = dte;
3607 }
3608
3609 static struct irq_remap_table *get_irq_table(u16 devid)
3610 {
3611 struct irq_remap_table *table;
3612
3613 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3614 "%s: no iommu for devid %x\n", __func__, devid))
3615 return NULL;
3616
3617 table = irq_lookup_table[devid];
3618 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3619 return NULL;
3620
3621 return table;
3622 }
3623
3624 static struct irq_remap_table *__alloc_irq_table(void)
3625 {
3626 struct irq_remap_table *table;
3627
3628 table = kzalloc(sizeof(*table), GFP_KERNEL);
3629 if (!table)
3630 return NULL;
3631
3632 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3633 if (!table->table) {
3634 kfree(table);
3635 return NULL;
3636 }
3637 raw_spin_lock_init(&table->lock);
3638
3639 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3640 memset(table->table, 0,
3641 MAX_IRQS_PER_TABLE * sizeof(u32));
3642 else
3643 memset(table->table, 0,
3644 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3645 return table;
3646 }
3647
3648 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3649 struct irq_remap_table *table)
3650 {
3651 irq_lookup_table[devid] = table;
3652 set_dte_irq_entry(devid, table);
3653 iommu_flush_dte(iommu, devid);
3654 }
3655
3656 static struct irq_remap_table *alloc_irq_table(u16 devid)
3657 {
3658 struct irq_remap_table *table = NULL;
3659 struct irq_remap_table *new_table = NULL;
3660 struct amd_iommu *iommu;
3661 unsigned long flags;
3662 u16 alias;
3663
3664 spin_lock_irqsave(&iommu_table_lock, flags);
3665
3666 iommu = amd_iommu_rlookup_table[devid];
3667 if (!iommu)
3668 goto out_unlock;
3669
3670 table = irq_lookup_table[devid];
3671 if (table)
3672 goto out_unlock;
3673
3674 alias = amd_iommu_alias_table[devid];
3675 table = irq_lookup_table[alias];
3676 if (table) {
3677 set_remap_table_entry(iommu, devid, table);
3678 goto out_wait;
3679 }
3680 spin_unlock_irqrestore(&iommu_table_lock, flags);
3681
3682 /* Nothing there yet, allocate new irq remapping table */
3683 new_table = __alloc_irq_table();
3684 if (!new_table)
3685 return NULL;
3686
3687 spin_lock_irqsave(&iommu_table_lock, flags);
3688
3689 table = irq_lookup_table[devid];
3690 if (table)
3691 goto out_unlock;
3692
3693 table = irq_lookup_table[alias];
3694 if (table) {
3695 set_remap_table_entry(iommu, devid, table);
3696 goto out_wait;
3697 }
3698
3699 table = new_table;
3700 new_table = NULL;
3701
3702 set_remap_table_entry(iommu, devid, table);
3703 if (devid != alias)
3704 set_remap_table_entry(iommu, alias, table);
3705
3706 out_wait:
3707 iommu_completion_wait(iommu);
3708
3709 out_unlock:
3710 spin_unlock_irqrestore(&iommu_table_lock, flags);
3711
3712 if (new_table) {
3713 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3714 kfree(new_table);
3715 }
3716 return table;
3717 }
3718
3719 static int alloc_irq_index(u16 devid, int count, bool align)
3720 {
3721 struct irq_remap_table *table;
3722 int index, c, alignment = 1;
3723 unsigned long flags;
3724 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3725
3726 if (!iommu)
3727 return -ENODEV;
3728
3729 table = alloc_irq_table(devid);
3730 if (!table)
3731 return -ENODEV;
3732
3733 if (align)
3734 alignment = roundup_pow_of_two(count);
3735
3736 raw_spin_lock_irqsave(&table->lock, flags);
3737
3738 /* Scan table for free entries */
3739 for (index = ALIGN(table->min_index, alignment), c = 0;
3740 index < MAX_IRQS_PER_TABLE;) {
3741 if (!iommu->irte_ops->is_allocated(table, index)) {
3742 c += 1;
3743 } else {
3744 c = 0;
3745 index = ALIGN(index + 1, alignment);
3746 continue;
3747 }
3748
3749 if (c == count) {
3750 for (; c != 0; --c)
3751 iommu->irte_ops->set_allocated(table, index - c + 1);
3752
3753 index -= count - 1;
3754 goto out;
3755 }
3756
3757 index++;
3758 }
3759
3760 index = -ENOSPC;
3761
3762 out:
3763 raw_spin_unlock_irqrestore(&table->lock, flags);
3764
3765 return index;
3766 }
3767
3768 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3769 struct amd_ir_data *data)
3770 {
3771 struct irq_remap_table *table;
3772 struct amd_iommu *iommu;
3773 unsigned long flags;
3774 struct irte_ga *entry;
3775
3776 iommu = amd_iommu_rlookup_table[devid];
3777 if (iommu == NULL)
3778 return -EINVAL;
3779
3780 table = get_irq_table(devid);
3781 if (!table)
3782 return -ENOMEM;
3783
3784 raw_spin_lock_irqsave(&table->lock, flags);
3785
3786 entry = (struct irte_ga *)table->table;
3787 entry = &entry[index];
3788 entry->lo.fields_remap.valid = 0;
3789 entry->hi.val = irte->hi.val;
3790 entry->lo.val = irte->lo.val;
3791 entry->lo.fields_remap.valid = 1;
3792 if (data)
3793 data->ref = entry;
3794
3795 raw_spin_unlock_irqrestore(&table->lock, flags);
3796
3797 iommu_flush_irt(iommu, devid);
3798 iommu_completion_wait(iommu);
3799
3800 return 0;
3801 }
3802
3803 static int modify_irte(u16 devid, int index, union irte *irte)
3804 {
3805 struct irq_remap_table *table;
3806 struct amd_iommu *iommu;
3807 unsigned long flags;
3808
3809 iommu = amd_iommu_rlookup_table[devid];
3810 if (iommu == NULL)
3811 return -EINVAL;
3812
3813 table = get_irq_table(devid);
3814 if (!table)
3815 return -ENOMEM;
3816
3817 raw_spin_lock_irqsave(&table->lock, flags);
3818 table->table[index] = irte->val;
3819 raw_spin_unlock_irqrestore(&table->lock, flags);
3820
3821 iommu_flush_irt(iommu, devid);
3822 iommu_completion_wait(iommu);
3823
3824 return 0;
3825 }
3826
3827 static void free_irte(u16 devid, int index)
3828 {
3829 struct irq_remap_table *table;
3830 struct amd_iommu *iommu;
3831 unsigned long flags;
3832
3833 iommu = amd_iommu_rlookup_table[devid];
3834 if (iommu == NULL)
3835 return;
3836
3837 table = get_irq_table(devid);
3838 if (!table)
3839 return;
3840
3841 raw_spin_lock_irqsave(&table->lock, flags);
3842 iommu->irte_ops->clear_allocated(table, index);
3843 raw_spin_unlock_irqrestore(&table->lock, flags);
3844
3845 iommu_flush_irt(iommu, devid);
3846 iommu_completion_wait(iommu);
3847 }
3848
3849 static void irte_prepare(void *entry,
3850 u32 delivery_mode, u32 dest_mode,
3851 u8 vector, u32 dest_apicid, int devid)
3852 {
3853 union irte *irte = (union irte *) entry;
3854
3855 irte->val = 0;
3856 irte->fields.vector = vector;
3857 irte->fields.int_type = delivery_mode;
3858 irte->fields.destination = dest_apicid;
3859 irte->fields.dm = dest_mode;
3860 irte->fields.valid = 1;
3861 }
3862
3863 static void irte_ga_prepare(void *entry,
3864 u32 delivery_mode, u32 dest_mode,
3865 u8 vector, u32 dest_apicid, int devid)
3866 {
3867 struct irte_ga *irte = (struct irte_ga *) entry;
3868
3869 irte->lo.val = 0;
3870 irte->hi.val = 0;
3871 irte->lo.fields_remap.int_type = delivery_mode;
3872 irte->lo.fields_remap.dm = dest_mode;
3873 irte->hi.fields.vector = vector;
3874 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3875 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3876 irte->lo.fields_remap.valid = 1;
3877 }
3878
3879 static void irte_activate(void *entry, u16 devid, u16 index)
3880 {
3881 union irte *irte = (union irte *) entry;
3882
3883 irte->fields.valid = 1;
3884 modify_irte(devid, index, irte);
3885 }
3886
3887 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3888 {
3889 struct irte_ga *irte = (struct irte_ga *) entry;
3890
3891 irte->lo.fields_remap.valid = 1;
3892 modify_irte_ga(devid, index, irte, NULL);
3893 }
3894
3895 static void irte_deactivate(void *entry, u16 devid, u16 index)
3896 {
3897 union irte *irte = (union irte *) entry;
3898
3899 irte->fields.valid = 0;
3900 modify_irte(devid, index, irte);
3901 }
3902
3903 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3904 {
3905 struct irte_ga *irte = (struct irte_ga *) entry;
3906
3907 irte->lo.fields_remap.valid = 0;
3908 modify_irte_ga(devid, index, irte, NULL);
3909 }
3910
3911 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3912 u8 vector, u32 dest_apicid)
3913 {
3914 union irte *irte = (union irte *) entry;
3915
3916 irte->fields.vector = vector;
3917 irte->fields.destination = dest_apicid;
3918 modify_irte(devid, index, irte);
3919 }
3920
3921 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3922 u8 vector, u32 dest_apicid)
3923 {
3924 struct irte_ga *irte = (struct irte_ga *) entry;
3925
3926 if (!irte->lo.fields_remap.guest_mode) {
3927 irte->hi.fields.vector = vector;
3928 irte->lo.fields_remap.destination =
3929 APICID_TO_IRTE_DEST_LO(dest_apicid);
3930 irte->hi.fields.destination =
3931 APICID_TO_IRTE_DEST_HI(dest_apicid);
3932 modify_irte_ga(devid, index, irte, NULL);
3933 }
3934 }
3935
3936 #define IRTE_ALLOCATED (~1U)
3937 static void irte_set_allocated(struct irq_remap_table *table, int index)
3938 {
3939 table->table[index] = IRTE_ALLOCATED;
3940 }
3941
3942 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3943 {
3944 struct irte_ga *ptr = (struct irte_ga *)table->table;
3945 struct irte_ga *irte = &ptr[index];
3946
3947 memset(&irte->lo.val, 0, sizeof(u64));
3948 memset(&irte->hi.val, 0, sizeof(u64));
3949 irte->hi.fields.vector = 0xff;
3950 }
3951
3952 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3953 {
3954 union irte *ptr = (union irte *)table->table;
3955 union irte *irte = &ptr[index];
3956
3957 return irte->val != 0;
3958 }
3959
3960 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3961 {
3962 struct irte_ga *ptr = (struct irte_ga *)table->table;
3963 struct irte_ga *irte = &ptr[index];
3964
3965 return irte->hi.fields.vector != 0;
3966 }
3967
3968 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3969 {
3970 table->table[index] = 0;
3971 }
3972
3973 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3974 {
3975 struct irte_ga *ptr = (struct irte_ga *)table->table;
3976 struct irte_ga *irte = &ptr[index];
3977
3978 memset(&irte->lo.val, 0, sizeof(u64));
3979 memset(&irte->hi.val, 0, sizeof(u64));
3980 }
3981
3982 static int get_devid(struct irq_alloc_info *info)
3983 {
3984 int devid = -1;
3985
3986 switch (info->type) {
3987 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3988 devid = get_ioapic_devid(info->ioapic_id);
3989 break;
3990 case X86_IRQ_ALLOC_TYPE_HPET:
3991 devid = get_hpet_devid(info->hpet_id);
3992 break;
3993 case X86_IRQ_ALLOC_TYPE_MSI:
3994 case X86_IRQ_ALLOC_TYPE_MSIX:
3995 devid = get_device_id(&info->msi_dev->dev);
3996 break;
3997 default:
3998 BUG_ON(1);
3999 break;
4000 }
4001
4002 return devid;
4003 }
4004
4005 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4006 {
4007 struct amd_iommu *iommu;
4008 int devid;
4009
4010 if (!info)
4011 return NULL;
4012
4013 devid = get_devid(info);
4014 if (devid >= 0) {
4015 iommu = amd_iommu_rlookup_table[devid];
4016 if (iommu)
4017 return iommu->ir_domain;
4018 }
4019
4020 return NULL;
4021 }
4022
4023 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4024 {
4025 struct amd_iommu *iommu;
4026 int devid;
4027
4028 if (!info)
4029 return NULL;
4030
4031 switch (info->type) {
4032 case X86_IRQ_ALLOC_TYPE_MSI:
4033 case X86_IRQ_ALLOC_TYPE_MSIX:
4034 devid = get_device_id(&info->msi_dev->dev);
4035 if (devid < 0)
4036 return NULL;
4037
4038 iommu = amd_iommu_rlookup_table[devid];
4039 if (iommu)
4040 return iommu->msi_domain;
4041 break;
4042 default:
4043 break;
4044 }
4045
4046 return NULL;
4047 }
4048
4049 struct irq_remap_ops amd_iommu_irq_ops = {
4050 .prepare = amd_iommu_prepare,
4051 .enable = amd_iommu_enable,
4052 .disable = amd_iommu_disable,
4053 .reenable = amd_iommu_reenable,
4054 .enable_faulting = amd_iommu_enable_faulting,
4055 .get_ir_irq_domain = get_ir_irq_domain,
4056 .get_irq_domain = get_irq_domain,
4057 };
4058
4059 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4060 struct irq_cfg *irq_cfg,
4061 struct irq_alloc_info *info,
4062 int devid, int index, int sub_handle)
4063 {
4064 struct irq_2_irte *irte_info = &data->irq_2_irte;
4065 struct msi_msg *msg = &data->msi_entry;
4066 struct IO_APIC_route_entry *entry;
4067 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4068
4069 if (!iommu)
4070 return;
4071
4072 data->irq_2_irte.devid = devid;
4073 data->irq_2_irte.index = index + sub_handle;
4074 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4075 apic->irq_dest_mode, irq_cfg->vector,
4076 irq_cfg->dest_apicid, devid);
4077
4078 switch (info->type) {
4079 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4080 /* Setup IOAPIC entry */
4081 entry = info->ioapic_entry;
4082 info->ioapic_entry = NULL;
4083 memset(entry, 0, sizeof(*entry));
4084 entry->vector = index;
4085 entry->mask = 0;
4086 entry->trigger = info->ioapic_trigger;
4087 entry->polarity = info->ioapic_polarity;
4088 /* Mask level triggered irqs. */
4089 if (info->ioapic_trigger)
4090 entry->mask = 1;
4091 break;
4092
4093 case X86_IRQ_ALLOC_TYPE_HPET:
4094 case X86_IRQ_ALLOC_TYPE_MSI:
4095 case X86_IRQ_ALLOC_TYPE_MSIX:
4096 msg->address_hi = MSI_ADDR_BASE_HI;
4097 msg->address_lo = MSI_ADDR_BASE_LO;
4098 msg->data = irte_info->index;
4099 break;
4100
4101 default:
4102 BUG_ON(1);
4103 break;
4104 }
4105 }
4106
4107 struct amd_irte_ops irte_32_ops = {
4108 .prepare = irte_prepare,
4109 .activate = irte_activate,
4110 .deactivate = irte_deactivate,
4111 .set_affinity = irte_set_affinity,
4112 .set_allocated = irte_set_allocated,
4113 .is_allocated = irte_is_allocated,
4114 .clear_allocated = irte_clear_allocated,
4115 };
4116
4117 struct amd_irte_ops irte_128_ops = {
4118 .prepare = irte_ga_prepare,
4119 .activate = irte_ga_activate,
4120 .deactivate = irte_ga_deactivate,
4121 .set_affinity = irte_ga_set_affinity,
4122 .set_allocated = irte_ga_set_allocated,
4123 .is_allocated = irte_ga_is_allocated,
4124 .clear_allocated = irte_ga_clear_allocated,
4125 };
4126
4127 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4128 unsigned int nr_irqs, void *arg)
4129 {
4130 struct irq_alloc_info *info = arg;
4131 struct irq_data *irq_data;
4132 struct amd_ir_data *data = NULL;
4133 struct irq_cfg *cfg;
4134 int i, ret, devid;
4135 int index;
4136
4137 if (!info)
4138 return -EINVAL;
4139 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4140 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4141 return -EINVAL;
4142
4143 /*
4144 * With IRQ remapping enabled, don't need contiguous CPU vectors
4145 * to support multiple MSI interrupts.
4146 */
4147 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4148 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4149
4150 devid = get_devid(info);
4151 if (devid < 0)
4152 return -EINVAL;
4153
4154 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4155 if (ret < 0)
4156 return ret;
4157
4158 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4159 struct irq_remap_table *table;
4160 struct amd_iommu *iommu;
4161
4162 table = alloc_irq_table(devid);
4163 if (table) {
4164 if (!table->min_index) {
4165 /*
4166 * Keep the first 32 indexes free for IOAPIC
4167 * interrupts.
4168 */
4169 table->min_index = 32;
4170 iommu = amd_iommu_rlookup_table[devid];
4171 for (i = 0; i < 32; ++i)
4172 iommu->irte_ops->set_allocated(table, i);
4173 }
4174 WARN_ON(table->min_index != 32);
4175 index = info->ioapic_pin;
4176 } else {
4177 index = -ENOMEM;
4178 }
4179 } else {
4180 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4181
4182 index = alloc_irq_index(devid, nr_irqs, align);
4183 }
4184 if (index < 0) {
4185 pr_warn("Failed to allocate IRTE\n");
4186 ret = index;
4187 goto out_free_parent;
4188 }
4189
4190 for (i = 0; i < nr_irqs; i++) {
4191 irq_data = irq_domain_get_irq_data(domain, virq + i);
4192 cfg = irqd_cfg(irq_data);
4193 if (!irq_data || !cfg) {
4194 ret = -EINVAL;
4195 goto out_free_data;
4196 }
4197
4198 ret = -ENOMEM;
4199 data = kzalloc(sizeof(*data), GFP_KERNEL);
4200 if (!data)
4201 goto out_free_data;
4202
4203 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4204 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4205 else
4206 data->entry = kzalloc(sizeof(struct irte_ga),
4207 GFP_KERNEL);
4208 if (!data->entry) {
4209 kfree(data);
4210 goto out_free_data;
4211 }
4212
4213 irq_data->hwirq = (devid << 16) + i;
4214 irq_data->chip_data = data;
4215 irq_data->chip = &amd_ir_chip;
4216 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4217 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4218 }
4219
4220 return 0;
4221
4222 out_free_data:
4223 for (i--; i >= 0; i--) {
4224 irq_data = irq_domain_get_irq_data(domain, virq + i);
4225 if (irq_data)
4226 kfree(irq_data->chip_data);
4227 }
4228 for (i = 0; i < nr_irqs; i++)
4229 free_irte(devid, index + i);
4230 out_free_parent:
4231 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4232 return ret;
4233 }
4234
4235 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4236 unsigned int nr_irqs)
4237 {
4238 struct irq_2_irte *irte_info;
4239 struct irq_data *irq_data;
4240 struct amd_ir_data *data;
4241 int i;
4242
4243 for (i = 0; i < nr_irqs; i++) {
4244 irq_data = irq_domain_get_irq_data(domain, virq + i);
4245 if (irq_data && irq_data->chip_data) {
4246 data = irq_data->chip_data;
4247 irte_info = &data->irq_2_irte;
4248 free_irte(irte_info->devid, irte_info->index);
4249 kfree(data->entry);
4250 kfree(data);
4251 }
4252 }
4253 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4254 }
4255
4256 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4257 struct amd_ir_data *ir_data,
4258 struct irq_2_irte *irte_info,
4259 struct irq_cfg *cfg);
4260
4261 static int irq_remapping_activate(struct irq_domain *domain,
4262 struct irq_data *irq_data, bool reserve)
4263 {
4264 struct amd_ir_data *data = irq_data->chip_data;
4265 struct irq_2_irte *irte_info = &data->irq_2_irte;
4266 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4267 struct irq_cfg *cfg = irqd_cfg(irq_data);
4268
4269 if (!iommu)
4270 return 0;
4271
4272 iommu->irte_ops->activate(data->entry, irte_info->devid,
4273 irte_info->index);
4274 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4275 return 0;
4276 }
4277
4278 static void irq_remapping_deactivate(struct irq_domain *domain,
4279 struct irq_data *irq_data)
4280 {
4281 struct amd_ir_data *data = irq_data->chip_data;
4282 struct irq_2_irte *irte_info = &data->irq_2_irte;
4283 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4284
4285 if (iommu)
4286 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4287 irte_info->index);
4288 }
4289
4290 static const struct irq_domain_ops amd_ir_domain_ops = {
4291 .alloc = irq_remapping_alloc,
4292 .free = irq_remapping_free,
4293 .activate = irq_remapping_activate,
4294 .deactivate = irq_remapping_deactivate,
4295 };
4296
4297 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4298 {
4299 struct amd_iommu *iommu;
4300 struct amd_iommu_pi_data *pi_data = vcpu_info;
4301 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4302 struct amd_ir_data *ir_data = data->chip_data;
4303 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4304 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4305 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4306
4307 /* Note:
4308 * This device has never been set up for guest mode.
4309 * we should not modify the IRTE
4310 */
4311 if (!dev_data || !dev_data->use_vapic)
4312 return 0;
4313
4314 pi_data->ir_data = ir_data;
4315
4316 /* Note:
4317 * SVM tries to set up for VAPIC mode, but we are in
4318 * legacy mode. So, we force legacy mode instead.
4319 */
4320 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4321 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4322 __func__);
4323 pi_data->is_guest_mode = false;
4324 }
4325
4326 iommu = amd_iommu_rlookup_table[irte_info->devid];
4327 if (iommu == NULL)
4328 return -EINVAL;
4329
4330 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4331 if (pi_data->is_guest_mode) {
4332 /* Setting */
4333 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4334 irte->hi.fields.vector = vcpu_pi_info->vector;
4335 irte->lo.fields_vapic.ga_log_intr = 1;
4336 irte->lo.fields_vapic.guest_mode = 1;
4337 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4338
4339 ir_data->cached_ga_tag = pi_data->ga_tag;
4340 } else {
4341 /* Un-Setting */
4342 struct irq_cfg *cfg = irqd_cfg(data);
4343
4344 irte->hi.val = 0;
4345 irte->lo.val = 0;
4346 irte->hi.fields.vector = cfg->vector;
4347 irte->lo.fields_remap.guest_mode = 0;
4348 irte->lo.fields_remap.destination =
4349 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4350 irte->hi.fields.destination =
4351 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4352 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4353 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4354
4355 /*
4356 * This communicates the ga_tag back to the caller
4357 * so that it can do all the necessary clean up.
4358 */
4359 ir_data->cached_ga_tag = 0;
4360 }
4361
4362 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4363 }
4364
4365
4366 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4367 struct amd_ir_data *ir_data,
4368 struct irq_2_irte *irte_info,
4369 struct irq_cfg *cfg)
4370 {
4371
4372 /*
4373 * Atomically updates the IRTE with the new destination, vector
4374 * and flushes the interrupt entry cache.
4375 */
4376 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4377 irte_info->index, cfg->vector,
4378 cfg->dest_apicid);
4379 }
4380
4381 static int amd_ir_set_affinity(struct irq_data *data,
4382 const struct cpumask *mask, bool force)
4383 {
4384 struct amd_ir_data *ir_data = data->chip_data;
4385 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4386 struct irq_cfg *cfg = irqd_cfg(data);
4387 struct irq_data *parent = data->parent_data;
4388 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4389 int ret;
4390
4391 if (!iommu)
4392 return -ENODEV;
4393
4394 ret = parent->chip->irq_set_affinity(parent, mask, force);
4395 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4396 return ret;
4397
4398 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4399 /*
4400 * After this point, all the interrupts will start arriving
4401 * at the new destination. So, time to cleanup the previous
4402 * vector allocation.
4403 */
4404 send_cleanup_vector(cfg);
4405
4406 return IRQ_SET_MASK_OK_DONE;
4407 }
4408
4409 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4410 {
4411 struct amd_ir_data *ir_data = irq_data->chip_data;
4412
4413 *msg = ir_data->msi_entry;
4414 }
4415
4416 static struct irq_chip amd_ir_chip = {
4417 .name = "AMD-IR",
4418 .irq_ack = apic_ack_irq,
4419 .irq_set_affinity = amd_ir_set_affinity,
4420 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4421 .irq_compose_msi_msg = ir_compose_msi_msg,
4422 };
4423
4424 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4425 {
4426 struct fwnode_handle *fn;
4427
4428 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4429 if (!fn)
4430 return -ENOMEM;
4431 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4432 irq_domain_free_fwnode(fn);
4433 if (!iommu->ir_domain)
4434 return -ENOMEM;
4435
4436 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4437 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4438 "AMD-IR-MSI",
4439 iommu->index);
4440 return 0;
4441 }
4442
4443 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4444 {
4445 unsigned long flags;
4446 struct amd_iommu *iommu;
4447 struct irq_remap_table *table;
4448 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4449 int devid = ir_data->irq_2_irte.devid;
4450 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4451 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4452
4453 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4454 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4455 return 0;
4456
4457 iommu = amd_iommu_rlookup_table[devid];
4458 if (!iommu)
4459 return -ENODEV;
4460
4461 table = get_irq_table(devid);
4462 if (!table)
4463 return -ENODEV;
4464
4465 raw_spin_lock_irqsave(&table->lock, flags);
4466
4467 if (ref->lo.fields_vapic.guest_mode) {
4468 if (cpu >= 0) {
4469 ref->lo.fields_vapic.destination =
4470 APICID_TO_IRTE_DEST_LO(cpu);
4471 ref->hi.fields.destination =
4472 APICID_TO_IRTE_DEST_HI(cpu);
4473 }
4474 ref->lo.fields_vapic.is_run = is_run;
4475 barrier();
4476 }
4477
4478 raw_spin_unlock_irqrestore(&table->lock, flags);
4479
4480 iommu_flush_irt(iommu, devid);
4481 iommu_completion_wait(iommu);
4482 return 0;
4483 }
4484 EXPORT_SYMBOL(amd_iommu_update_ga);
4485 #endif
Linux with added FPC-III support