arch/c6x/platforms/timer64.c

   1 /*
   2  *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
   3  *  Contributed by: Mark Salter (msalter@redhat.com)
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License version 2 as
   7  *  published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clockchips.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/of.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_address.h>
  16 #include <asm/soc.h>
  17 #include <asm/dscr.h>
  18 #include <asm/special_insns.h>
  19 #include <asm/timer64.h>
  20
  21 struct timer_regs {
  22         u32     reserved0;
  23         u32     emumgt;
  24         u32     reserved1;
  25         u32     reserved2;
  26         u32     cntlo;
  27         u32     cnthi;
  28         u32     prdlo;
  29         u32     prdhi;
  30         u32     tcr;
  31         u32     tgcr;
  32         u32     wdtcr;
  33 };
  34
  35 static struct timer_regs __iomem *timer;
  36
  37 #define TCR_TSTATLO          0x001
  38 #define TCR_INVOUTPLO        0x002
  39 #define TCR_INVINPLO         0x004
  40 #define TCR_CPLO             0x008
  41 #define TCR_ENAMODELO_ONCE   0x040
  42 #define TCR_ENAMODELO_CONT   0x080
  43 #define TCR_ENAMODELO_MASK   0x0c0
  44 #define TCR_PWIDLO_MASK      0x030
  45 #define TCR_CLKSRCLO         0x100
  46 #define TCR_TIENLO           0x200
  47 #define TCR_TSTATHI          (0x001 << 16)
  48 #define TCR_INVOUTPHI        (0x002 << 16)
  49 #define TCR_CPHI             (0x008 << 16)
  50 #define TCR_PWIDHI_MASK      (0x030 << 16)
  51 #define TCR_ENAMODEHI_ONCE   (0x040 << 16)
  52 #define TCR_ENAMODEHI_CONT   (0x080 << 16)
  53 #define TCR_ENAMODEHI_MASK   (0x0c0 << 16)
  54
  55 #define TGCR_TIMLORS         0x001
  56 #define TGCR_TIMHIRS         0x002
  57 #define TGCR_TIMMODE_UD32    0x004
  58 #define TGCR_TIMMODE_WDT64   0x008
  59 #define TGCR_TIMMODE_CD32    0x00c
  60 #define TGCR_TIMMODE_MASK    0x00c
  61 #define TGCR_PSCHI_MASK      (0x00f << 8)
  62 #define TGCR_TDDRHI_MASK     (0x00f << 12)
  63
  64 /*
  65  * Timer clocks are divided down from the CPU clock
  66  * The divisor is in the EMUMGTCLKSPD register
  67  */
  68 #define TIMER_DIVISOR \
  69         ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
  70
  71 #define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
  72
  73 #define TIMER64_MODE_DISABLED 0
  74 #define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
  75 #define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
  76
  77 static int timer64_mode;
  78 static int timer64_devstate_id = -1;
  79
  80 static void timer64_config(unsigned long period)
  81 {
  82         u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
  83
  84         soc_writel(tcr, &timer->tcr);
  85         soc_writel(period - 1, &timer->prdlo);
  86         soc_writel(0, &timer->cntlo);
  87         tcr |= timer64_mode;
  88         soc_writel(tcr, &timer->tcr);
  89 }
  90
  91 static void timer64_enable(void)
  92 {
  93         u32 val;
  94
  95         if (timer64_devstate_id >= 0)
  96                 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
  97
  98         /* disable timer, reset count */
  99         soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
 100         soc_writel(0, &timer->prdlo);
 101
 102         /* use internal clock and 1 cycle pulse width */
 103         val = soc_readl(&timer->tcr);
 104         soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
 105
 106         /* dual 32-bit unchained mode */
 107         val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
 108         soc_writel(val, &timer->tgcr);
 109         soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
 110 }
 111
 112 static void timer64_disable(void)
 113 {
 114         /* disable timer, reset count */
 115         soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
 116         soc_writel(0, &timer->prdlo);
 117
 118         if (timer64_devstate_id >= 0)
 119                 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
 120 }
 121
 122 static int next_event(unsigned long delta,
 123                       struct clock_event_device *evt)
 124 {
 125         timer64_config(delta);
 126         return 0;
 127 }
 128
 129 static void set_clock_mode(enum clock_event_mode mode,
 130                            struct clock_event_device *evt)
 131 {
 132         switch (mode) {
 133         case CLOCK_EVT_MODE_PERIODIC:
 134                 timer64_enable();
 135                 timer64_mode = TIMER64_MODE_PERIODIC;
 136                 timer64_config(TIMER64_RATE / HZ);
 137                 break;
 138         case CLOCK_EVT_MODE_ONESHOT:
 139                 timer64_enable();
 140                 timer64_mode = TIMER64_MODE_ONE_SHOT;
 141                 break;
 142         case CLOCK_EVT_MODE_UNUSED:
 143         case CLOCK_EVT_MODE_SHUTDOWN:
 144                 timer64_mode = TIMER64_MODE_DISABLED;
 145                 timer64_disable();
 146                 break;
 147         case CLOCK_EVT_MODE_RESUME:
 148                 break;
 149         }
 150 }
 151
 152 static struct clock_event_device t64_clockevent_device = {
 153         .name           = "TIMER64_EVT32_TIMER",
 154         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 155         .rating         = 200,
 156         .set_mode       = set_clock_mode,
 157         .set_next_event = next_event,
 158 };
 159
 160 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 161 {
 162         struct clock_event_device *cd = &t64_clockevent_device;
 163
 164         cd->event_handler(cd);
 165
 166         return IRQ_HANDLED;
 167 }
 168
 169 static struct irqaction timer_iact = {
 170         .name           = "timer",
 171         .flags          = IRQF_TIMER,
 172         .handler        = timer_interrupt,
 173         .dev_id         = &t64_clockevent_device,
 174 };
 175
 176 void __init timer64_init(void)
 177 {
 178         struct clock_event_device *cd = &t64_clockevent_device;
 179         struct device_node *np, *first = NULL;
 180         u32 val;
 181         int err, found = 0;
 182
 183         for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
 184                 err = of_property_read_u32(np, "ti,core-mask", &val);
 185                 if (!err) {
 186                         if (val & (1 << get_coreid())) {
 187                                 found = 1;
 188                                 break;
 189                         }
 190                 } else if (!first)
 191                         first = np;
 192         }
 193         if (!found) {
 194                 /* try first one with no core-mask */
 195                 if (first)
 196                         np = of_node_get(first);
 197                 else {
 198                         pr_debug("Cannot find ti,c64x+timer64 timer.\n");
 199                         return;
 200                 }
 201         }
 202
 203         timer = of_iomap(np, 0);
 204         if (!timer) {
 205                 pr_debug("%s: Cannot map timer registers.\n", np->full_name);
 206                 goto out;
 207         }
 208         pr_debug("%s: Timer registers=%p.\n", np->full_name, timer);
 209
 210         cd->irq = irq_of_parse_and_map(np, 0);
 211         if (cd->irq == NO_IRQ) {
 212                 pr_debug("%s: Cannot find interrupt.\n", np->full_name);
 213                 iounmap(timer);
 214                 goto out;
 215         }
 216
 217         /* If there is a device state control, save the ID. */
 218         err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
 219         if (!err) {
 220                 timer64_devstate_id = val;
 221
 222                 /*
 223                  * It is necessary to enable the timer block here because
 224                  * the TIMER_DIVISOR macro needs to read a timer register
 225                  * to get the divisor.
 226                  */
 227                 dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
 228         }
 229
 230         pr_debug("%s: Timer irq=%d.\n", np->full_name, cd->irq);
 231
 232         clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
 233
 234         cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
 235         cd->min_delta_ns        = clockevent_delta2ns(250, cd);
 236
 237         cd->cpumask             = cpumask_of(smp_processor_id());
 238
 239         clockevents_register_device(cd);
 240         setup_irq(cd->irq, &timer_iact);
 241
 242 out:
 243         of_node_put(np);
 244         return;
 245 }