2 * SoC specific setup code for the AT91SAM9N12
4 * Copyright (C) 2012 Atmel Corporation.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/dma-mapping.h>
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15 #include <mach/at91sam9n12.h>
16 #include <mach/at91_pmc.h>
25 /* --------------------------------------------------------------------
27 * -------------------------------------------------------------------- */
30 * The peripheral clocks.
32 static struct clk pioAB_clk
= {
34 .pmc_mask
= 1 << AT91SAM9N12_ID_PIOAB
,
35 .type
= CLK_TYPE_PERIPHERAL
,
37 static struct clk pioCD_clk
= {
39 .pmc_mask
= 1 << AT91SAM9N12_ID_PIOCD
,
40 .type
= CLK_TYPE_PERIPHERAL
,
42 static struct clk usart0_clk
= {
44 .pmc_mask
= 1 << AT91SAM9N12_ID_USART0
,
45 .type
= CLK_TYPE_PERIPHERAL
,
47 static struct clk usart1_clk
= {
49 .pmc_mask
= 1 << AT91SAM9N12_ID_USART1
,
50 .type
= CLK_TYPE_PERIPHERAL
,
52 static struct clk usart2_clk
= {
54 .pmc_mask
= 1 << AT91SAM9N12_ID_USART2
,
55 .type
= CLK_TYPE_PERIPHERAL
,
57 static struct clk usart3_clk
= {
59 .pmc_mask
= 1 << AT91SAM9N12_ID_USART3
,
60 .type
= CLK_TYPE_PERIPHERAL
,
62 static struct clk twi0_clk
= {
64 .pmc_mask
= 1 << AT91SAM9N12_ID_TWI0
,
65 .type
= CLK_TYPE_PERIPHERAL
,
67 static struct clk twi1_clk
= {
69 .pmc_mask
= 1 << AT91SAM9N12_ID_TWI1
,
70 .type
= CLK_TYPE_PERIPHERAL
,
72 static struct clk mmc_clk
= {
74 .pmc_mask
= 1 << AT91SAM9N12_ID_MCI
,
75 .type
= CLK_TYPE_PERIPHERAL
,
77 static struct clk spi0_clk
= {
79 .pmc_mask
= 1 << AT91SAM9N12_ID_SPI0
,
80 .type
= CLK_TYPE_PERIPHERAL
,
82 static struct clk spi1_clk
= {
84 .pmc_mask
= 1 << AT91SAM9N12_ID_SPI1
,
85 .type
= CLK_TYPE_PERIPHERAL
,
87 static struct clk uart0_clk
= {
89 .pmc_mask
= 1 << AT91SAM9N12_ID_UART0
,
90 .type
= CLK_TYPE_PERIPHERAL
,
92 static struct clk uart1_clk
= {
94 .pmc_mask
= 1 << AT91SAM9N12_ID_UART1
,
95 .type
= CLK_TYPE_PERIPHERAL
,
97 static struct clk tcb_clk
= {
99 .pmc_mask
= 1 << AT91SAM9N12_ID_TCB
,
100 .type
= CLK_TYPE_PERIPHERAL
,
102 static struct clk pwm_clk
= {
104 .pmc_mask
= 1 << AT91SAM9N12_ID_PWM
,
105 .type
= CLK_TYPE_PERIPHERAL
,
107 static struct clk adc_clk
= {
109 .pmc_mask
= 1 << AT91SAM9N12_ID_ADC
,
110 .type
= CLK_TYPE_PERIPHERAL
,
112 static struct clk dma_clk
= {
114 .pmc_mask
= 1 << AT91SAM9N12_ID_DMA
,
115 .type
= CLK_TYPE_PERIPHERAL
,
117 static struct clk uhp_clk
= {
119 .pmc_mask
= 1 << AT91SAM9N12_ID_UHP
,
120 .type
= CLK_TYPE_PERIPHERAL
,
122 static struct clk udp_clk
= {
124 .pmc_mask
= 1 << AT91SAM9N12_ID_UDP
,
125 .type
= CLK_TYPE_PERIPHERAL
,
127 static struct clk lcdc_clk
= {
129 .pmc_mask
= 1 << AT91SAM9N12_ID_LCDC
,
130 .type
= CLK_TYPE_PERIPHERAL
,
132 static struct clk ssc_clk
= {
134 .pmc_mask
= 1 << AT91SAM9N12_ID_SSC
,
135 .type
= CLK_TYPE_PERIPHERAL
,
138 static struct clk
*periph_clocks
[] __initdata
= {
162 static struct clk_lookup periph_clocks_lookups
[] = {
163 /* lookup table for DT entries */
164 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck
),
165 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk
),
166 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk
),
167 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk
),
168 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk
),
169 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk
),
170 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk
),
171 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk
),
172 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk
),
173 CLKDEV_CON_DEV_ID(NULL
, "f8010000.i2c", &twi0_clk
),
174 CLKDEV_CON_DEV_ID(NULL
, "f8014000.i2c", &twi1_clk
),
175 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk
),
176 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk
),
177 CLKDEV_CON_DEV_ID(NULL
, "fffff400.gpio", &pioAB_clk
),
178 CLKDEV_CON_DEV_ID(NULL
, "fffff600.gpio", &pioAB_clk
),
179 CLKDEV_CON_DEV_ID(NULL
, "fffff800.gpio", &pioCD_clk
),
180 CLKDEV_CON_DEV_ID(NULL
, "fffffa00.gpio", &pioCD_clk
),
181 /* additional fake clock for macb_hclk */
182 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk
),
183 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk
),
187 * The two programmable clocks.
188 * You must configure pin multiplexing to bring these signals out.
190 static struct clk pck0
= {
192 .pmc_mask
= AT91_PMC_PCK0
,
193 .type
= CLK_TYPE_PROGRAMMABLE
,
196 static struct clk pck1
= {
198 .pmc_mask
= AT91_PMC_PCK1
,
199 .type
= CLK_TYPE_PROGRAMMABLE
,
203 static void __init
at91sam9n12_register_clocks(void)
207 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
208 clk_register(periph_clocks
[i
]);
212 clkdev_add_table(periph_clocks_lookups
,
213 ARRAY_SIZE(periph_clocks_lookups
));
217 /* --------------------------------------------------------------------
218 * AT91SAM9N12 processor initialization
219 * -------------------------------------------------------------------- */
221 static void __init
at91sam9n12_map_io(void)
223 at91_init_sram(0, AT91SAM9N12_SRAM_BASE
, AT91SAM9N12_SRAM_SIZE
);
226 static void __init
at91sam9n12_initialize(void)
228 at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC
);
231 AT91_SOC_START(at91sam9n12
)
232 .map_io
= at91sam9n12_map_io
,
233 .register_clocks
= at91sam9n12_register_clocks
,
234 .init
= at91sam9n12_initialize
,