arch/arm/mach-at91/include/mach/hardware.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/hardware.h
   3  *
   4  *  Copyright (C) 2003 SAN People
   5  *  Copyright (C) 2003 ATMEL
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13
  14 #ifndef __ASM_ARCH_HARDWARE_H
  15 #define __ASM_ARCH_HARDWARE_H
  16
  17 #include <asm/sizes.h>
  18
  19 /* DBGU base */
  20 /* rm9200, 9260/9g20, 9261/9g10, 9rl */
  21 #define AT91_BASE_DBGU0 0xfffff200
  22 /* 9263, 9g45 */
  23 #define AT91_BASE_DBGU1 0xffffee00
  24
  25 #if defined(CONFIG_ARCH_AT91X40)
  26 #include <mach/at91x40.h>
  27 #else
  28 #include <mach/at91rm9200.h>
  29 #include <mach/at91sam9260.h>
  30 #include <mach/at91sam9261.h>
  31 #include <mach/at91sam9263.h>
  32 #include <mach/at91sam9rl.h>
  33 #include <mach/at91sam9g45.h>
  34 #include <mach/at91sam9x5.h>
  35 #include <mach/at91sam9n12.h>
  36 #include <mach/sama5d3.h>
  37
  38 /*
  39  * On all at91 except rm9200 and x40 have the System Controller starts
  40  * at address 0xffffc000 and has a size of 16KiB.
  41  *
  42  * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
  43  * at 0xfffff000
  44  *
  45  * Removes the individual definitions of AT91_BASE_SYS and
  46  * replaces them with a common version at base 0xfffffc000 and size 16KiB
  47  * and map the same memory space
  48  */
  49 #define AT91_BASE_SYS   0xffffc000
  50 #endif
  51
  52 /*
  53  * On all at91 have the Advanced Interrupt Controller starts at address
  54  * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
  55  */
  56 #define AT91_AIC        0xfffff000
  57 #define AT91_PMC        0xfffffc00
  58
  59 /*
  60  * Peripheral identifiers/interrupts.
  61  */
  62 #define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
  63 #define AT91_ID_SYS             1       /* System Peripherals */
  64
  65 #ifdef CONFIG_MMU
  66 /*
  67  * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
  68  * to 0xFEF78000 .. 0xFF000000.  (544Kb)
  69  */
  70 #define AT91_IO_PHYS_BASE       0xFFF78000
  71 #define AT91_IO_VIRT_BASE       IOMEM(0xFF000000 - AT91_IO_SIZE)
  72 #else
  73 /*
  74  * Identity mapping for the non MMU case.
  75  */
  76 #define AT91_IO_PHYS_BASE       AT91_BASE_SYS
  77 #define AT91_IO_VIRT_BASE       IOMEM(AT91_IO_PHYS_BASE)
  78 #endif
  79
  80 #define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
  81
  82  /* Convert a physical IO address to virtual IO address */
  83 #define AT91_IO_P2V(x)          ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
  84
  85 /*
  86  * Virtual to Physical Address mapping for IO devices.
  87  */
  88 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
  89
  90  /* Internal SRAM is mapped below the IO devices */
  91 #define AT91_SRAM_MAX           SZ_1M
  92 #define AT91_VIRT_BASE          (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
  93
  94 /* External Memory Map */
  95 #define AT91_CHIPSELECT_0       0x10000000
  96 #define AT91_CHIPSELECT_1       0x20000000
  97 #define AT91_CHIPSELECT_2       0x30000000
  98 #define AT91_CHIPSELECT_3       0x40000000
  99 #define AT91_CHIPSELECT_4       0x50000000
 100 #define AT91_CHIPSELECT_5       0x60000000
 101 #define AT91_CHIPSELECT_6       0x70000000
 102 #define AT91_CHIPSELECT_7       0x80000000
 103
 104 /* Clocks */
 105 #define AT91_SLOW_CLOCK         32768           /* slow clock */
 106
 107
 108 #endif