arch/arm/mach-at91/include/mach/uncompress.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/uncompress.h
   3  *
   4  * Copyright (C) 2003 SAN People
   5  * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #ifndef __ASM_ARCH_UNCOMPRESS_H
  23 #define __ASM_ARCH_UNCOMPRESS_H
  24
  25 #include <linux/io.h>
  26 #include <linux/atmel_serial.h>
  27 #include <mach/hardware.h>
  28
  29 #include <mach/at91_dbgu.h>
  30 #include <mach/cpu.h>
  31
  32 void __iomem *at91_uart;
  33
  34 #if !defined(CONFIG_ARCH_AT91X40)
  35 static const u32 uarts_rm9200[] = {
  36         AT91_BASE_DBGU0,
  37         AT91RM9200_BASE_US0,
  38         AT91RM9200_BASE_US1,
  39         AT91RM9200_BASE_US2,
  40         AT91RM9200_BASE_US3,
  41         0,
  42 };
  43
  44 static const u32 uarts_sam9260[] = {
  45         AT91_BASE_DBGU0,
  46         AT91SAM9260_BASE_US0,
  47         AT91SAM9260_BASE_US1,
  48         AT91SAM9260_BASE_US2,
  49         AT91SAM9260_BASE_US3,
  50         AT91SAM9260_BASE_US4,
  51         AT91SAM9260_BASE_US5,
  52         0,
  53 };
  54
  55 static const u32 uarts_sam9261[] = {
  56         AT91_BASE_DBGU0,
  57         AT91SAM9261_BASE_US0,
  58         AT91SAM9261_BASE_US1,
  59         AT91SAM9261_BASE_US2,
  60         0,
  61 };
  62
  63 static const u32 uarts_sam9263[] = {
  64         AT91_BASE_DBGU1,
  65         AT91SAM9263_BASE_US0,
  66         AT91SAM9263_BASE_US1,
  67         AT91SAM9263_BASE_US2,
  68         0,
  69 };
  70
  71 static const u32 uarts_sam9g45[] = {
  72         AT91_BASE_DBGU1,
  73         AT91SAM9G45_BASE_US0,
  74         AT91SAM9G45_BASE_US1,
  75         AT91SAM9G45_BASE_US2,
  76         AT91SAM9G45_BASE_US3,
  77         0,
  78 };
  79
  80 static const u32 uarts_sam9rl[] = {
  81         AT91_BASE_DBGU0,
  82         AT91SAM9RL_BASE_US0,
  83         AT91SAM9RL_BASE_US1,
  84         AT91SAM9RL_BASE_US2,
  85         AT91SAM9RL_BASE_US3,
  86         0,
  87 };
  88
  89 static const u32 uarts_sam9x5[] = {
  90         AT91_BASE_DBGU0,
  91         AT91SAM9X5_BASE_USART0,
  92         AT91SAM9X5_BASE_USART1,
  93         AT91SAM9X5_BASE_USART2,
  94         0,
  95 };
  96
  97 static const u32 uarts_sama5[] = {
  98         AT91_BASE_DBGU1,
  99         SAMA5D3_BASE_USART0,
 100         SAMA5D3_BASE_USART1,
 101         SAMA5D3_BASE_USART2,
 102         SAMA5D3_BASE_USART3,
 103         0,
 104 };
 105
 106 static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 107 {
 108         u32 cidr, socid;
 109
 110         cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
 111         socid = cidr & ~AT91_CIDR_VERSION;
 112
 113         switch (socid) {
 114         case ARCH_ID_AT91RM9200:
 115                 return uarts_rm9200;
 116
 117         case ARCH_ID_AT91SAM9G20:
 118         case ARCH_ID_AT91SAM9260:
 119                 return uarts_sam9260;
 120
 121         case ARCH_ID_AT91SAM9261:
 122                 return uarts_sam9261;
 123
 124         case ARCH_ID_AT91SAM9263:
 125                 return uarts_sam9263;
 126
 127         case ARCH_ID_AT91SAM9G45:
 128                 return uarts_sam9g45;
 129
 130         case ARCH_ID_AT91SAM9RL64:
 131                 return uarts_sam9rl;
 132
 133         case ARCH_ID_AT91SAM9N12:
 134         case ARCH_ID_AT91SAM9X5:
 135                 return uarts_sam9x5;
 136
 137         case ARCH_ID_SAMA5D3:
 138                 return uarts_sama5;
 139         }
 140
 141         /* at91sam9g10 */
 142         if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 143                 return uarts_sam9261;
 144         }
 145         /* at91sam9xe */
 146         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 147                 return uarts_sam9260;
 148         }
 149
 150         return NULL;
 151 }
 152
 153 static inline void arch_decomp_setup(void)
 154 {
 155         int i = 0;
 156         const u32* usarts;
 157
 158         usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
 159
 160         if (!usarts)
 161                 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
 162         if (!usarts) {
 163                 at91_uart = NULL;
 164                 return;
 165         }
 166
 167         do {
 168                 /* physical address */
 169                 at91_uart = (void __iomem *)usarts[i];
 170
 171                 if (__raw_readl(at91_uart + ATMEL_US_BRGR))
 172                         return;
 173                 i++;
 174         } while (usarts[i]);
 175
 176         at91_uart = NULL;
 177 }
 178 #else
 179 static inline void arch_decomp_setup(void)
 180 {
 181         at91_uart = NULL;
 182 }
 183 #endif
 184
 185 /*
 186  * The following code assumes the serial port has already been
 187  * initialized by the bootloader.  If you didn't setup a port in
 188  * your bootloader then nothing will appear (which might be desired).
 189  *
 190  * This does not append a newline
 191  */
 192 static void putc(int c)
 193 {
 194         if (!at91_uart)
 195                 return;
 196
 197         while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
 198                 barrier();
 199         __raw_writel(c, at91_uart + ATMEL_US_THR);
 200 }
 201
 202 static inline void flush(void)
 203 {
 204         if (!at91_uart)
 205                 return;
 206
 207         /* wait for transmission to complete */
 208         while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
 209                 barrier();
 210 }
 211
 212 #endif