x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / arm / mach-davinci / board-neuros-osd2.c
blob46f336fca80384541257e667383d85080b718b1b
1 /*
2 * Neuros Technologies OSD2 board support
4 * Modified from original 644X-EVM board support.
5 * 2008 (c) Neuros Technology, LLC.
6 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
7 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
9 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
10 * Internet Television Platform. Hardware is very close to TI
11 * DM644X-EVM board. It has:
12 * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
13 * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
14 * Additionally realtime clock, IR remote control receiver,
15 * IR Blaster based on MSP430 (firmware although is different
16 * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
17 * with PATA interface, two muxed red-green leds.
19 * For more information please refer to
20 * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
26 #include <linux/platform_device.h>
27 #include <linux/gpio.h>
28 #include <linux/mtd/partitions.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
33 #include <mach/common.h>
34 #include <linux/platform_data/i2c-davinci.h>
35 #include <mach/serial.h>
36 #include <mach/mux.h>
37 #include <linux/platform_data/mtd-davinci.h>
38 #include <linux/platform_data/mmc-davinci.h>
39 #include <linux/platform_data/usb-davinci.h>
41 #include "davinci.h"
43 #define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
44 #define LXT971_PHY_ID 0x001378e2
45 #define LXT971_PHY_MASK 0xfffffff0
47 #define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
48 #define NTOSD2_MSP430_I2C_ADDR 0x59
49 #define NTOSD2_MSP430_IRQ 2
51 /* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
52 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
53 * page.
56 #define NAND_BLOCK_SIZE SZ_128K
58 static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
60 /* UBL (a few copies) plus U-Boot */
61 .name = "bootloader",
62 .offset = 0,
63 .size = 15 * NAND_BLOCK_SIZE,
64 .mask_flags = MTD_WRITEABLE, /* force read-only */
65 }, {
66 /* U-Boot environment */
67 .name = "params",
68 .offset = MTDPART_OFS_APPEND,
69 .size = 1 * NAND_BLOCK_SIZE,
70 .mask_flags = 0,
71 }, {
72 /* Kernel */
73 .name = "kernel",
74 .offset = MTDPART_OFS_APPEND,
75 .size = SZ_4M,
76 .mask_flags = 0,
77 }, {
78 /* File System */
79 .name = "filesystem",
80 .offset = MTDPART_OFS_APPEND,
81 .size = MTDPART_SIZ_FULL,
82 .mask_flags = 0,
84 /* A few blocks at end hold a flash Bad Block Table. */
87 static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
88 .parts = davinci_ntosd2_nandflash_partition,
89 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
90 .ecc_mode = NAND_ECC_HW,
91 .ecc_bits = 1,
92 .bbt_options = NAND_BBT_USE_FLASH,
95 static struct resource davinci_ntosd2_nandflash_resource[] = {
97 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
98 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
99 .flags = IORESOURCE_MEM,
100 }, {
101 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
102 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
103 .flags = IORESOURCE_MEM,
107 static struct platform_device davinci_ntosd2_nandflash_device = {
108 .name = "davinci_nand",
109 .id = 0,
110 .dev = {
111 .platform_data = &davinci_ntosd2_nandflash_data,
113 .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
114 .resource = davinci_ntosd2_nandflash_resource,
117 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
119 static struct platform_device davinci_fb_device = {
120 .name = "davincifb",
121 .id = -1,
122 .dev = {
123 .dma_mask = &davinci_fb_dma_mask,
124 .coherent_dma_mask = DMA_BIT_MASK(32),
126 .num_resources = 0,
129 static struct snd_platform_data dm644x_ntosd2_snd_data;
131 static struct gpio_led ntosd2_leds[] = {
132 { .name = "led1_green", .gpio = GPIO(10), },
133 { .name = "led1_red", .gpio = GPIO(11), },
134 { .name = "led2_green", .gpio = GPIO(12), },
135 { .name = "led2_red", .gpio = GPIO(13), },
138 static struct gpio_led_platform_data ntosd2_leds_data = {
139 .num_leds = ARRAY_SIZE(ntosd2_leds),
140 .leds = ntosd2_leds,
143 static struct platform_device ntosd2_leds_dev = {
144 .name = "leds-gpio",
145 .id = -1,
146 .dev = {
147 .platform_data = &ntosd2_leds_data,
152 static struct platform_device *davinci_ntosd2_devices[] __initdata = {
153 &davinci_fb_device,
154 &ntosd2_leds_dev,
157 static void __init davinci_ntosd2_map_io(void)
159 dm644x_init();
162 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
163 .wires = 4,
166 #define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
168 #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
170 static __init void davinci_ntosd2_init(void)
172 struct clk *aemif_clk;
173 struct davinci_soc_info *soc_info = &davinci_soc_info;
175 aemif_clk = clk_get(NULL, "aemif");
176 clk_prepare_enable(aemif_clk);
178 if (HAS_ATA) {
179 if (HAS_NAND)
180 pr_warning("WARNING: both IDE and Flash are "
181 "enabled, but they share AEMIF pins.\n"
182 "\tDisable IDE for NAND/NOR support.\n");
183 davinci_init_ide();
184 } else if (HAS_NAND) {
185 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
186 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
188 /* only one device will be jumpered and detected */
189 if (HAS_NAND)
190 platform_device_register(
191 &davinci_ntosd2_nandflash_device);
194 platform_add_devices(davinci_ntosd2_devices,
195 ARRAY_SIZE(davinci_ntosd2_devices));
197 davinci_serial_init(dm644x_serial_device);
198 dm644x_init_asp(&dm644x_ntosd2_snd_data);
200 soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
202 davinci_setup_usb(1000, 8);
204 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
205 * The AEAWx are five new AEAW pins that can be muxed by separately.
206 * They are a bitmask for GPIO management. According TI
207 * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
208 * gpio(10,11,12,13) for leds any combination of bits works except
209 * four last. So we are to reset all five.
211 davinci_cfg_reg(DM644X_AEAW0);
212 davinci_cfg_reg(DM644X_AEAW1);
213 davinci_cfg_reg(DM644X_AEAW2);
214 davinci_cfg_reg(DM644X_AEAW3);
215 davinci_cfg_reg(DM644X_AEAW4);
217 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
220 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
221 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
222 .atag_offset = 0x100,
223 .map_io = davinci_ntosd2_map_io,
224 .init_irq = davinci_irq_init,
225 .init_time = davinci_timer_init,
226 .init_machine = davinci_ntosd2_init,
227 .init_late = davinci_init_late,
228 .dma_zone_size = SZ_128M,
229 .restart = davinci_restart,
230 MACHINE_END