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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / arm / mach-davinci / devices-da8xx.c
blob2e473fefd71ebc2049d490f554da0f8a70d2578b
1 /*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-contiguous.h>
16 #include <linux/serial_8250.h>
17 #include <linux/ahci_platform.h>
18 #include <linux/clk.h>
19 #include <linux/reboot.h>
20
21 #include <mach/cputype.h>
22 #include <mach/common.h>
23 #include <mach/time.h>
24 #include <mach/da8xx.h>
25 #include <mach/cpuidle.h>
26 #include <mach/sram.h>
27
28 #include "clock.h"
29 #include "asp.h"
30
31 #define DA8XX_TPCC_BASE 0x01c00000
32 #define DA8XX_TPTC0_BASE 0x01c08000
33 #define DA8XX_TPTC1_BASE 0x01c08400
34 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
35 #define DA8XX_I2C0_BASE 0x01c22000
36 #define DA8XX_RTC_BASE 0x01c23000
37 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
38 #define DA8XX_MMCSD0_BASE 0x01c40000
39 #define DA8XX_SPI0_BASE 0x01c41000
40 #define DA830_SPI1_BASE 0x01e12000
41 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
42 #define DA850_SATA_BASE 0x01e18000
43 #define DA850_MMCSD1_BASE 0x01e1b000
44 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
45 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
46 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
47 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
48 #define DA8XX_I2C1_BASE 0x01e28000
49 #define DA850_TPCC1_BASE 0x01e30000
50 #define DA850_TPTC2_BASE 0x01e38000
51 #define DA850_SPI1_BASE 0x01f0e000
52 #define DA8XX_DDR2_CTL_BASE 0xb0000000
53
54 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
55 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
56 #define DA8XX_EMAC_RAM_OFFSET 0x0000
57 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
58
59 #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
60 #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
61 #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
62 #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
63 #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
64 #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
65 #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
66 #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
67
68 void __iomem *da8xx_syscfg0_base;
69 void __iomem *da8xx_syscfg1_base;
70
71 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
72 {
73 .mapbase = DA8XX_UART0_BASE,
74 .irq = IRQ_DA8XX_UARTINT0,
75 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
76 UPF_IOREMAP,
77 .iotype = UPIO_MEM,
78 .regshift = 2,
79 },
80 {
81 .flags = 0,
82 }
83 };
84 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
85 {
86 .mapbase = DA8XX_UART1_BASE,
87 .irq = IRQ_DA8XX_UARTINT1,
88 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
89 UPF_IOREMAP,
90 .iotype = UPIO_MEM,
91 .regshift = 2,
92 },
93 {
94 .flags = 0,
95 }
96 };
97 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
98 {
99 .mapbase = DA8XX_UART2_BASE,
100 .irq = IRQ_DA8XX_UARTINT2,
101 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
102 UPF_IOREMAP,
103 .iotype = UPIO_MEM,
104 .regshift = 2,
105 },
106 {
107 .flags = 0,
108 }
109 };
110
111 struct platform_device da8xx_serial_device[] = {
112 {
113 .name = "serial8250",
114 .id = PLAT8250_DEV_PLATFORM,
115 .dev = {
116 .platform_data = da8xx_serial0_pdata,
117 }
118 },
119 {
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM1,
122 .dev = {
123 .platform_data = da8xx_serial1_pdata,
124 }
125 },
126 {
127 .name = "serial8250",
128 .id = PLAT8250_DEV_PLATFORM2,
129 .dev = {
130 .platform_data = da8xx_serial2_pdata,
131 }
132 },
133 {
134 }
135 };
136
137 static s8 da8xx_queue_tc_mapping[][2] = {
138 /* {event queue no, TC no} */
139 {0, 0},
140 {1, 1},
141 {-1, -1}
142 };
143
144 static s8 da8xx_queue_priority_mapping[][2] = {
145 /* {event queue no, Priority} */
146 {0, 3},
147 {1, 7},
148 {-1, -1}
149 };
150
151 static s8 da850_queue_tc_mapping[][2] = {
152 /* {event queue no, TC no} */
153 {0, 0},
154 {-1, -1}
155 };
156
157 static s8 da850_queue_priority_mapping[][2] = {
158 /* {event queue no, Priority} */
159 {0, 3},
160 {-1, -1}
161 };
162
163 static struct edma_soc_info da830_edma_cc0_info = {
164 .n_channel = 32,
165 .n_region = 4,
166 .n_slot = 128,
167 .n_tc = 2,
168 .n_cc = 1,
169 .queue_tc_mapping = da8xx_queue_tc_mapping,
170 .queue_priority_mapping = da8xx_queue_priority_mapping,
171 .default_queue = EVENTQ_1,
172 };
173
174 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
175 &da830_edma_cc0_info,
176 };
177
178 static struct edma_soc_info da850_edma_cc_info[] = {
179 {
180 .n_channel = 32,
181 .n_region = 4,
182 .n_slot = 128,
183 .n_tc = 2,
184 .n_cc = 1,
185 .queue_tc_mapping = da8xx_queue_tc_mapping,
186 .queue_priority_mapping = da8xx_queue_priority_mapping,
187 .default_queue = EVENTQ_1,
188 },
189 {
190 .n_channel = 32,
191 .n_region = 4,
192 .n_slot = 128,
193 .n_tc = 1,
194 .n_cc = 1,
195 .queue_tc_mapping = da850_queue_tc_mapping,
196 .queue_priority_mapping = da850_queue_priority_mapping,
197 .default_queue = EVENTQ_0,
198 },
199 };
200
201 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
202 &da850_edma_cc_info[0],
203 &da850_edma_cc_info[1],
204 };
205
206 static struct resource da830_edma_resources[] = {
207 {
208 .name = "edma_cc0",
209 .start = DA8XX_TPCC_BASE,
210 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
211 .flags = IORESOURCE_MEM,
212 },
213 {
214 .name = "edma_tc0",
215 .start = DA8XX_TPTC0_BASE,
216 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
217 .flags = IORESOURCE_MEM,
218 },
219 {
220 .name = "edma_tc1",
221 .start = DA8XX_TPTC1_BASE,
222 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
223 .flags = IORESOURCE_MEM,
224 },
225 {
226 .name = "edma0",
227 .start = IRQ_DA8XX_CCINT0,
228 .flags = IORESOURCE_IRQ,
229 },
230 {
231 .name = "edma0_err",
232 .start = IRQ_DA8XX_CCERRINT,
233 .flags = IORESOURCE_IRQ,
234 },
235 };
236
237 static struct resource da850_edma_resources[] = {
238 {
239 .name = "edma_cc0",
240 .start = DA8XX_TPCC_BASE,
241 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
242 .flags = IORESOURCE_MEM,
243 },
244 {
245 .name = "edma_tc0",
246 .start = DA8XX_TPTC0_BASE,
247 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
248 .flags = IORESOURCE_MEM,
249 },
250 {
251 .name = "edma_tc1",
252 .start = DA8XX_TPTC1_BASE,
253 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 {
257 .name = "edma_cc1",
258 .start = DA850_TPCC1_BASE,
259 .end = DA850_TPCC1_BASE + SZ_32K - 1,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .name = "edma_tc2",
264 .start = DA850_TPTC2_BASE,
265 .end = DA850_TPTC2_BASE + SZ_1K - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 {
269 .name = "edma0",
270 .start = IRQ_DA8XX_CCINT0,
271 .flags = IORESOURCE_IRQ,
272 },
273 {
274 .name = "edma0_err",
275 .start = IRQ_DA8XX_CCERRINT,
276 .flags = IORESOURCE_IRQ,
277 },
278 {
279 .name = "edma1",
280 .start = IRQ_DA850_CCINT1,
281 .flags = IORESOURCE_IRQ,
282 },
283 {
284 .name = "edma1_err",
285 .start = IRQ_DA850_CCERRINT1,
286 .flags = IORESOURCE_IRQ,
287 },
288 };
289
290 static struct platform_device da830_edma_device = {
291 .name = "edma",
292 .id = -1,
293 .dev = {
294 .platform_data = da830_edma_info,
295 },
296 .num_resources = ARRAY_SIZE(da830_edma_resources),
297 .resource = da830_edma_resources,
298 };
299
300 static struct platform_device da850_edma_device = {
301 .name = "edma",
302 .id = -1,
303 .dev = {
304 .platform_data = da850_edma_info,
305 },
306 .num_resources = ARRAY_SIZE(da850_edma_resources),
307 .resource = da850_edma_resources,
308 };
309
310 int __init da830_register_edma(struct edma_rsv_info *rsv)
311 {
312 da830_edma_cc0_info.rsv = rsv;
313
314 return platform_device_register(&da830_edma_device);
315 }
316
317 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
318 {
319 if (rsv) {
320 da850_edma_cc_info[0].rsv = rsv[0];
321 da850_edma_cc_info[1].rsv = rsv[1];
322 }
323
324 return platform_device_register(&da850_edma_device);
325 }
326
327 static struct resource da8xx_i2c_resources0[] = {
328 {
329 .start = DA8XX_I2C0_BASE,
330 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
331 .flags = IORESOURCE_MEM,
332 },
333 {
334 .start = IRQ_DA8XX_I2CINT0,
335 .end = IRQ_DA8XX_I2CINT0,
336 .flags = IORESOURCE_IRQ,
337 },
338 };
339
340 static struct platform_device da8xx_i2c_device0 = {
341 .name = "i2c_davinci",
342 .id = 1,
343 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
344 .resource = da8xx_i2c_resources0,
345 };
346
347 static struct resource da8xx_i2c_resources1[] = {
348 {
349 .start = DA8XX_I2C1_BASE,
350 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
351 .flags = IORESOURCE_MEM,
352 },
353 {
354 .start = IRQ_DA8XX_I2CINT1,
355 .end = IRQ_DA8XX_I2CINT1,
356 .flags = IORESOURCE_IRQ,
357 },
358 };
359
360 static struct platform_device da8xx_i2c_device1 = {
361 .name = "i2c_davinci",
362 .id = 2,
363 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
364 .resource = da8xx_i2c_resources1,
365 };
366
367 int __init da8xx_register_i2c(int instance,
368 struct davinci_i2c_platform_data *pdata)
369 {
370 struct platform_device *pdev;
371
372 if (instance == 0)
373 pdev = &da8xx_i2c_device0;
374 else if (instance == 1)
375 pdev = &da8xx_i2c_device1;
376 else
377 return -EINVAL;
378
379 pdev->dev.platform_data = pdata;
380 return platform_device_register(pdev);
381 }
382
383 static struct resource da8xx_watchdog_resources[] = {
384 {
385 .start = DA8XX_WDOG_BASE,
386 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
387 .flags = IORESOURCE_MEM,
388 },
389 };
390
391 static struct platform_device da8xx_wdt_device = {
392 .name = "watchdog",
393 .id = -1,
394 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
395 .resource = da8xx_watchdog_resources,
396 };
397
398 void da8xx_restart(enum reboot_mode mode, const char *cmd)
399 {
400 struct device *dev;
401
402 dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
403 if (!dev) {
404 pr_err("%s: failed to find watchdog device\n", __func__);
405 return;
406 }
407
408 davinci_watchdog_reset(to_platform_device(dev));
409 }
410
411 int __init da8xx_register_watchdog(void)
412 {
413 return platform_device_register(&da8xx_wdt_device);
414 }
415
416 static struct resource da8xx_emac_resources[] = {
417 {
418 .start = DA8XX_EMAC_CPPI_PORT_BASE,
419 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
420 .flags = IORESOURCE_MEM,
421 },
422 {
423 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
424 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
425 .flags = IORESOURCE_IRQ,
426 },
427 {
428 .start = IRQ_DA8XX_C0_RX_PULSE,
429 .end = IRQ_DA8XX_C0_RX_PULSE,
430 .flags = IORESOURCE_IRQ,
431 },
432 {
433 .start = IRQ_DA8XX_C0_TX_PULSE,
434 .end = IRQ_DA8XX_C0_TX_PULSE,
435 .flags = IORESOURCE_IRQ,
436 },
437 {
438 .start = IRQ_DA8XX_C0_MISC_PULSE,
439 .end = IRQ_DA8XX_C0_MISC_PULSE,
440 .flags = IORESOURCE_IRQ,
441 },
442 };
443
444 struct emac_platform_data da8xx_emac_pdata = {
445 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
446 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
447 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
448 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
449 .version = EMAC_VERSION_2,
450 };
451
452 static struct platform_device da8xx_emac_device = {
453 .name = "davinci_emac",
454 .id = 1,
455 .dev = {
456 .platform_data = &da8xx_emac_pdata,
457 },
458 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
459 .resource = da8xx_emac_resources,
460 };
461
462 static struct resource da8xx_mdio_resources[] = {
463 {
464 .start = DA8XX_EMAC_MDIO_BASE,
465 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
466 .flags = IORESOURCE_MEM,
467 },
468 };
469
470 static struct platform_device da8xx_mdio_device = {
471 .name = "davinci_mdio",
472 .id = 0,
473 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
474 .resource = da8xx_mdio_resources,
475 };
476
477 int __init da8xx_register_emac(void)
478 {
479 int ret;
480
481 ret = platform_device_register(&da8xx_mdio_device);
482 if (ret < 0)
483 return ret;
484
485 return platform_device_register(&da8xx_emac_device);
486 }
487
488 static struct resource da830_mcasp1_resources[] = {
489 {
490 .name = "mcasp1",
491 .start = DAVINCI_DA830_MCASP1_REG_BASE,
492 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
493 .flags = IORESOURCE_MEM,
494 },
495 /* TX event */
496 {
497 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
498 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
499 .flags = IORESOURCE_DMA,
500 },
501 /* RX event */
502 {
503 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
504 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
505 .flags = IORESOURCE_DMA,
506 },
507 };
508
509 static struct platform_device da830_mcasp1_device = {
510 .name = "davinci-mcasp",
511 .id = 1,
512 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
513 .resource = da830_mcasp1_resources,
514 };
515
516 static struct resource da850_mcasp_resources[] = {
517 {
518 .name = "mcasp",
519 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
520 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
521 .flags = IORESOURCE_MEM,
522 },
523 /* TX event */
524 {
525 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
526 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
527 .flags = IORESOURCE_DMA,
528 },
529 /* RX event */
530 {
531 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
532 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
533 .flags = IORESOURCE_DMA,
534 },
535 };
536
537 static struct platform_device da850_mcasp_device = {
538 .name = "davinci-mcasp",
539 .id = 0,
540 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
541 .resource = da850_mcasp_resources,
542 };
543
544 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
545 {
546 /* DA830/OMAP-L137 has 3 instances of McASP */
547 if (cpu_is_davinci_da830() && id == 1) {
548 da830_mcasp1_device.dev.platform_data = pdata;
549 platform_device_register(&da830_mcasp1_device);
550 } else if (cpu_is_davinci_da850()) {
551 da850_mcasp_device.dev.platform_data = pdata;
552 platform_device_register(&da850_mcasp_device);
553 }
554 }
555
556 static struct resource da8xx_pruss_resources[] = {
557 {
558 .start = DA8XX_PRUSS_MEM_BASE,
559 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
560 .flags = IORESOURCE_MEM,
561 },
562 {
563 .start = IRQ_DA8XX_EVTOUT0,
564 .end = IRQ_DA8XX_EVTOUT0,
565 .flags = IORESOURCE_IRQ,
566 },
567 {
568 .start = IRQ_DA8XX_EVTOUT1,
569 .end = IRQ_DA8XX_EVTOUT1,
570 .flags = IORESOURCE_IRQ,
571 },
572 {
573 .start = IRQ_DA8XX_EVTOUT2,
574 .end = IRQ_DA8XX_EVTOUT2,
575 .flags = IORESOURCE_IRQ,
576 },
577 {
578 .start = IRQ_DA8XX_EVTOUT3,
579 .end = IRQ_DA8XX_EVTOUT3,
580 .flags = IORESOURCE_IRQ,
581 },
582 {
583 .start = IRQ_DA8XX_EVTOUT4,
584 .end = IRQ_DA8XX_EVTOUT4,
585 .flags = IORESOURCE_IRQ,
586 },
587 {
588 .start = IRQ_DA8XX_EVTOUT5,
589 .end = IRQ_DA8XX_EVTOUT5,
590 .flags = IORESOURCE_IRQ,
591 },
592 {
593 .start = IRQ_DA8XX_EVTOUT6,
594 .end = IRQ_DA8XX_EVTOUT6,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 .start = IRQ_DA8XX_EVTOUT7,
599 .end = IRQ_DA8XX_EVTOUT7,
600 .flags = IORESOURCE_IRQ,
601 },
602 };
603
604 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
605 .pintc_base = 0x4000,
606 };
607
608 static struct platform_device da8xx_uio_pruss_dev = {
609 .name = "pruss_uio",
610 .id = -1,
611 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
612 .resource = da8xx_pruss_resources,
613 .dev = {
614 .coherent_dma_mask = DMA_BIT_MASK(32),
615 .platform_data = &da8xx_uio_pruss_pdata,
616 }
617 };
618
619 int __init da8xx_register_uio_pruss(void)
620 {
621 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
622 return platform_device_register(&da8xx_uio_pruss_dev);
623 }
624
625 static struct lcd_ctrl_config lcd_cfg = {
626 .panel_shade = COLOR_ACTIVE,
627 .bpp = 16,
628 };
629
630 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
631 .manu_name = "sharp",
632 .controller_data = &lcd_cfg,
633 .type = "Sharp_LCD035Q3DG01",
634 };
635
636 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
637 .manu_name = "sharp",
638 .controller_data = &lcd_cfg,
639 .type = "Sharp_LK043T1DG01",
640 };
641
642 static struct resource da8xx_lcdc_resources[] = {
643 [0] = { /* registers */
644 .start = DA8XX_LCD_CNTRL_BASE,
645 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
646 .flags = IORESOURCE_MEM,
647 },
648 [1] = { /* interrupt */
649 .start = IRQ_DA8XX_LCDINT,
650 .end = IRQ_DA8XX_LCDINT,
651 .flags = IORESOURCE_IRQ,
652 },
653 };
654
655 static struct platform_device da8xx_lcdc_device = {
656 .name = "da8xx_lcdc",
657 .id = 0,
658 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
659 .resource = da8xx_lcdc_resources,
660 };
661
662 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
663 {
664 da8xx_lcdc_device.dev.platform_data = pdata;
665 return platform_device_register(&da8xx_lcdc_device);
666 }
667
668 static struct resource da8xx_mmcsd0_resources[] = {
669 { /* registers */
670 .start = DA8XX_MMCSD0_BASE,
671 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
672 .flags = IORESOURCE_MEM,
673 },
674 { /* interrupt */
675 .start = IRQ_DA8XX_MMCSDINT0,
676 .end = IRQ_DA8XX_MMCSDINT0,
677 .flags = IORESOURCE_IRQ,
678 },
679 { /* DMA RX */
680 .start = DA8XX_DMA_MMCSD0_RX,
681 .end = DA8XX_DMA_MMCSD0_RX,
682 .flags = IORESOURCE_DMA,
683 },
684 { /* DMA TX */
685 .start = DA8XX_DMA_MMCSD0_TX,
686 .end = DA8XX_DMA_MMCSD0_TX,
687 .flags = IORESOURCE_DMA,
688 },
689 };
690
691 static struct platform_device da8xx_mmcsd0_device = {
692 .name = "da830-mmc",
693 .id = 0,
694 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
695 .resource = da8xx_mmcsd0_resources,
696 };
697
698 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
699 {
700 da8xx_mmcsd0_device.dev.platform_data = config;
701 return platform_device_register(&da8xx_mmcsd0_device);
702 }
703
704 #ifdef CONFIG_ARCH_DAVINCI_DA850
705 static struct resource da850_mmcsd1_resources[] = {
706 { /* registers */
707 .start = DA850_MMCSD1_BASE,
708 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
709 .flags = IORESOURCE_MEM,
710 },
711 { /* interrupt */
712 .start = IRQ_DA850_MMCSDINT0_1,
713 .end = IRQ_DA850_MMCSDINT0_1,
714 .flags = IORESOURCE_IRQ,
715 },
716 { /* DMA RX */
717 .start = DA850_DMA_MMCSD1_RX,
718 .end = DA850_DMA_MMCSD1_RX,
719 .flags = IORESOURCE_DMA,
720 },
721 { /* DMA TX */
722 .start = DA850_DMA_MMCSD1_TX,
723 .end = DA850_DMA_MMCSD1_TX,
724 .flags = IORESOURCE_DMA,
725 },
726 };
727
728 static struct platform_device da850_mmcsd1_device = {
729 .name = "da830-mmc",
730 .id = 1,
731 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
732 .resource = da850_mmcsd1_resources,
733 };
734
735 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
736 {
737 da850_mmcsd1_device.dev.platform_data = config;
738 return platform_device_register(&da850_mmcsd1_device);
739 }
740 #endif
741
742 static struct resource da8xx_rproc_resources[] = {
743 { /* DSP boot address */
744 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
745 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
746 .flags = IORESOURCE_MEM,
747 },
748 { /* DSP interrupt registers */
749 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
750 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
751 .flags = IORESOURCE_MEM,
752 },
753 { /* dsp irq */
754 .start = IRQ_DA8XX_CHIPINT0,
755 .end = IRQ_DA8XX_CHIPINT0,
756 .flags = IORESOURCE_IRQ,
757 },
758 };
759
760 static struct platform_device da8xx_dsp = {
761 .name = "davinci-rproc",
762 .dev = {
763 .coherent_dma_mask = DMA_BIT_MASK(32),
764 },
765 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
766 .resource = da8xx_rproc_resources,
767 };
768
769 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
770
771 static phys_addr_t rproc_base __initdata;
772 static unsigned long rproc_size __initdata;
773
774 static int __init early_rproc_mem(char *p)
775 {
776 char *endp;
777
778 if (p == NULL)
779 return 0;
780
781 rproc_size = memparse(p, &endp);
782 if (*endp == '@')
783 rproc_base = memparse(endp + 1, NULL);
784
785 return 0;
786 }
787 early_param("rproc_mem", early_rproc_mem);
788
789 void __init da8xx_rproc_reserve_cma(void)
790 {
791 int ret;
792
793 if (!rproc_base || !rproc_size) {
794 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
795 " 'nn' and 'address' must both be non-zero\n",
796 __func__);
797
798 return;
799 }
800
801 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
802 __func__, rproc_size, (unsigned long)rproc_base);
803
804 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
805 if (ret)
806 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
807 }
808
809 #else
810
811 void __init da8xx_rproc_reserve_cma(void)
812 {
813 }
814
815 #endif
816
817 int __init da8xx_register_rproc(void)
818 {
819 int ret;
820
821 ret = platform_device_register(&da8xx_dsp);
822 if (ret)
823 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
824
825 return ret;
826 };
827
828 static struct resource da8xx_rtc_resources[] = {
829 {
830 .start = DA8XX_RTC_BASE,
831 .end = DA8XX_RTC_BASE + SZ_4K - 1,
832 .flags = IORESOURCE_MEM,
833 },
834 { /* timer irq */
835 .start = IRQ_DA8XX_RTC,
836 .end = IRQ_DA8XX_RTC,
837 .flags = IORESOURCE_IRQ,
838 },
839 { /* alarm irq */
840 .start = IRQ_DA8XX_RTC,
841 .end = IRQ_DA8XX_RTC,
842 .flags = IORESOURCE_IRQ,
843 },
844 };
845
846 static struct platform_device da8xx_rtc_device = {
847 .name = "da830-rtc",
848 .id = -1,
849 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
850 .resource = da8xx_rtc_resources,
851 };
852
853 int da8xx_register_rtc(void)
854 {
855 return platform_device_register(&da8xx_rtc_device);
856 }
857
858 static void __iomem *da8xx_ddr2_ctlr_base;
859 void __iomem * __init da8xx_get_mem_ctlr(void)
860 {
861 if (da8xx_ddr2_ctlr_base)
862 return da8xx_ddr2_ctlr_base;
863
864 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
865 if (!da8xx_ddr2_ctlr_base)
866 pr_warn("%s: Unable to map DDR2 controller", __func__);
867
868 return da8xx_ddr2_ctlr_base;
869 }
870
871 static struct resource da8xx_cpuidle_resources[] = {
872 {
873 .start = DA8XX_DDR2_CTL_BASE,
874 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
875 .flags = IORESOURCE_MEM,
876 },
877 };
878
879 /* DA8XX devices support DDR2 power down */
880 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
881 .ddr2_pdown = 1,
882 };
883
884
885 static struct platform_device da8xx_cpuidle_device = {
886 .name = "cpuidle-davinci",
887 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
888 .resource = da8xx_cpuidle_resources,
889 .dev = {
890 .platform_data = &da8xx_cpuidle_pdata,
891 },
892 };
893
894 int __init da8xx_register_cpuidle(void)
895 {
896 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
897
898 return platform_device_register(&da8xx_cpuidle_device);
899 }
900
901 static struct resource da8xx_spi0_resources[] = {
902 [0] = {
903 .start = DA8XX_SPI0_BASE,
904 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
905 .flags = IORESOURCE_MEM,
906 },
907 [1] = {
908 .start = IRQ_DA8XX_SPINT0,
909 .end = IRQ_DA8XX_SPINT0,
910 .flags = IORESOURCE_IRQ,
911 },
912 [2] = {
913 .start = DA8XX_DMA_SPI0_RX,
914 .end = DA8XX_DMA_SPI0_RX,
915 .flags = IORESOURCE_DMA,
916 },
917 [3] = {
918 .start = DA8XX_DMA_SPI0_TX,
919 .end = DA8XX_DMA_SPI0_TX,
920 .flags = IORESOURCE_DMA,
921 },
922 };
923
924 static struct resource da8xx_spi1_resources[] = {
925 [0] = {
926 .start = DA830_SPI1_BASE,
927 .end = DA830_SPI1_BASE + SZ_4K - 1,
928 .flags = IORESOURCE_MEM,
929 },
930 [1] = {
931 .start = IRQ_DA8XX_SPINT1,
932 .end = IRQ_DA8XX_SPINT1,
933 .flags = IORESOURCE_IRQ,
934 },
935 [2] = {
936 .start = DA8XX_DMA_SPI1_RX,
937 .end = DA8XX_DMA_SPI1_RX,
938 .flags = IORESOURCE_DMA,
939 },
940 [3] = {
941 .start = DA8XX_DMA_SPI1_TX,
942 .end = DA8XX_DMA_SPI1_TX,
943 .flags = IORESOURCE_DMA,
944 },
945 };
946
947 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
948 [0] = {
949 .version = SPI_VERSION_2,
950 .intr_line = 1,
951 .dma_event_q = EVENTQ_0,
952 },
953 [1] = {
954 .version = SPI_VERSION_2,
955 .intr_line = 1,
956 .dma_event_q = EVENTQ_0,
957 },
958 };
959
960 static struct platform_device da8xx_spi_device[] = {
961 [0] = {
962 .name = "spi_davinci",
963 .id = 0,
964 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
965 .resource = da8xx_spi0_resources,
966 .dev = {
967 .platform_data = &da8xx_spi_pdata[0],
968 },
969 },
970 [1] = {
971 .name = "spi_davinci",
972 .id = 1,
973 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
974 .resource = da8xx_spi1_resources,
975 .dev = {
976 .platform_data = &da8xx_spi_pdata[1],
977 },
978 },
979 };
980
981 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
982 {
983 if (instance < 0 || instance > 1)
984 return -EINVAL;
985
986 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
987
988 if (instance == 1 && cpu_is_davinci_da850()) {
989 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
990 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
991 }
992
993 return platform_device_register(&da8xx_spi_device[instance]);
994 }
995
996 #ifdef CONFIG_ARCH_DAVINCI_DA850
997
998 static struct resource da850_sata_resources[] = {
999 {
1000 .start = DA850_SATA_BASE,
1001 .end = DA850_SATA_BASE + 0x1fff,
1002 .flags = IORESOURCE_MEM,
1003 },
1004 {
1005 .start = IRQ_DA850_SATAINT,
1006 .flags = IORESOURCE_IRQ,
1007 },
1008 };
1009
1010 /* SATA PHY Control Register offset from AHCI base */
1011 #define SATA_P0PHYCR_REG 0x178
1012
1013 #define SATA_PHY_MPY(x) ((x) << 0)
1014 #define SATA_PHY_LOS(x) ((x) << 6)
1015 #define SATA_PHY_RXCDR(x) ((x) << 10)
1016 #define SATA_PHY_RXEQ(x) ((x) << 13)
1017 #define SATA_PHY_TXSWING(x) ((x) << 19)
1018 #define SATA_PHY_ENPLL(x) ((x) << 31)
1019
1020 static struct clk *da850_sata_clk;
1021 static unsigned long da850_sata_refclkpn;
1022
1023 /* Supported DA850 SATA crystal frequencies */
1024 #define KHZ_TO_HZ(freq) ((freq) * 1000)
1025 static unsigned long da850_sata_xtal[] = {
1026 KHZ_TO_HZ(300000),
1027 KHZ_TO_HZ(250000),
1028 0, /* Reserved */
1029 KHZ_TO_HZ(187500),
1030 KHZ_TO_HZ(150000),
1031 KHZ_TO_HZ(125000),
1032 KHZ_TO_HZ(120000),
1033 KHZ_TO_HZ(100000),
1034 KHZ_TO_HZ(75000),
1035 KHZ_TO_HZ(60000),
1036 };
1037
1038 static int da850_sata_init(struct device *dev, void __iomem *addr)
1039 {
1040 int i, ret;
1041 unsigned int val;
1042
1043 da850_sata_clk = clk_get(dev, NULL);
1044 if (IS_ERR(da850_sata_clk))
1045 return PTR_ERR(da850_sata_clk);
1046
1047 ret = clk_prepare_enable(da850_sata_clk);
1048 if (ret)
1049 goto err0;
1050
1051 /* Enable SATA clock receiver */
1052 val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
1053 val &= ~BIT(0);
1054 __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
1055
1056 /* Get the multiplier needed for 1.5GHz PLL output */
1057 for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
1058 if (da850_sata_xtal[i] == da850_sata_refclkpn)
1059 break;
1060
1061 if (i == ARRAY_SIZE(da850_sata_xtal)) {
1062 ret = -EINVAL;
1063 goto err1;
1064 }
1065
1066 val = SATA_PHY_MPY(i + 1) |
1067 SATA_PHY_LOS(1) |
1068 SATA_PHY_RXCDR(4) |
1069 SATA_PHY_RXEQ(1) |
1070 SATA_PHY_TXSWING(3) |
1071 SATA_PHY_ENPLL(1);
1072
1073 __raw_writel(val, addr + SATA_P0PHYCR_REG);
1074
1075 return 0;
1076
1077 err1:
1078 clk_disable_unprepare(da850_sata_clk);
1079 err0:
1080 clk_put(da850_sata_clk);
1081 return ret;
1082 }
1083
1084 static void da850_sata_exit(struct device *dev)
1085 {
1086 clk_disable_unprepare(da850_sata_clk);
1087 clk_put(da850_sata_clk);
1088 }
1089
1090 static struct ahci_platform_data da850_sata_pdata = {
1091 .init = da850_sata_init,
1092 .exit = da850_sata_exit,
1093 };
1094
1095 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1096
1097 static struct platform_device da850_sata_device = {
1098 .name = "ahci",
1099 .id = -1,
1100 .dev = {
1101 .platform_data = &da850_sata_pdata,
1102 .dma_mask = &da850_sata_dmamask,
1103 .coherent_dma_mask = DMA_BIT_MASK(32),
1104 },
1105 .num_resources = ARRAY_SIZE(da850_sata_resources),
1106 .resource = da850_sata_resources,
1107 };
1108
1109 int __init da850_register_sata(unsigned long refclkpn)
1110 {
1111 da850_sata_refclkpn = refclkpn;
1112 if (!da850_sata_refclkpn)
1113 return -EINVAL;
1114
1115 return platform_device_register(&da850_sata_device);
1116 }
1117 #endif
Linux with added FPC-III support