2 * TI DaVinci DM355 chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
17 #include <linux/spi/spi.h>
19 #include <asm/mach/map.h>
21 #include <mach/cputype.h>
24 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
28 #include <linux/platform_data/spi-davinci.h>
29 #include <mach/gpio-davinci.h>
30 #include <linux/platform_data/edma.h>
37 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
38 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
39 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
42 * Device specific clocks
44 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
46 static struct pll_data pll1_data
= {
48 .phys_base
= DAVINCI_PLL1_BASE
,
49 .flags
= PLL_HAS_PREDIV
| PLL_HAS_POSTDIV
,
52 static struct pll_data pll2_data
= {
54 .phys_base
= DAVINCI_PLL2_BASE
,
55 .flags
= PLL_HAS_PREDIV
,
58 static struct clk ref_clk
= {
60 /* FIXME -- crystal rate is board-specific */
61 .rate
= DM355_REF_FREQ
,
64 static struct clk pll1_clk
= {
68 .pll_data
= &pll1_data
,
71 static struct clk pll1_aux_clk
= {
72 .name
= "pll1_aux_clk",
74 .flags
= CLK_PLL
| PRE_PLL
,
77 static struct clk pll1_sysclk1
= {
78 .name
= "pll1_sysclk1",
84 static struct clk pll1_sysclk2
= {
85 .name
= "pll1_sysclk2",
91 static struct clk pll1_sysclk3
= {
92 .name
= "pll1_sysclk3",
98 static struct clk pll1_sysclk4
= {
99 .name
= "pll1_sysclk4",
105 static struct clk pll1_sysclkbp
= {
106 .name
= "pll1_sysclkbp",
108 .flags
= CLK_PLL
| PRE_PLL
,
112 static struct clk vpss_dac_clk
= {
114 .parent
= &pll1_sysclk3
,
115 .lpsc
= DM355_LPSC_VPSS_DAC
,
118 static struct clk vpss_master_clk
= {
119 .name
= "vpss_master",
120 .parent
= &pll1_sysclk4
,
121 .lpsc
= DAVINCI_LPSC_VPSSMSTR
,
125 static struct clk vpss_slave_clk
= {
126 .name
= "vpss_slave",
127 .parent
= &pll1_sysclk4
,
128 .lpsc
= DAVINCI_LPSC_VPSSSLV
,
131 static struct clk clkout1_clk
= {
133 .parent
= &pll1_aux_clk
,
134 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
137 static struct clk clkout2_clk
= {
139 .parent
= &pll1_sysclkbp
,
142 static struct clk pll2_clk
= {
146 .pll_data
= &pll2_data
,
149 static struct clk pll2_sysclk1
= {
150 .name
= "pll2_sysclk1",
156 static struct clk pll2_sysclkbp
= {
157 .name
= "pll2_sysclkbp",
159 .flags
= CLK_PLL
| PRE_PLL
,
163 static struct clk clkout3_clk
= {
165 .parent
= &pll2_sysclkbp
,
166 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
169 static struct clk arm_clk
= {
171 .parent
= &pll1_sysclk1
,
172 .lpsc
= DAVINCI_LPSC_ARM
,
173 .flags
= ALWAYS_ENABLED
,
177 * NOT LISTED below, and not touched by Linux
178 * - in SyncReset state by default
179 * .lpsc = DAVINCI_LPSC_TPCC,
180 * .lpsc = DAVINCI_LPSC_TPTC0,
181 * .lpsc = DAVINCI_LPSC_TPTC1,
182 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
183 * .lpsc = DAVINCI_LPSC_MEMSTICK,
184 * - in Enabled state by default
185 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
186 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
188 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
189 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
190 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
192 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
195 static struct clk mjcp_clk
= {
197 .parent
= &pll1_sysclk1
,
198 .lpsc
= DAVINCI_LPSC_IMCOP
,
201 static struct clk uart0_clk
= {
203 .parent
= &pll1_aux_clk
,
204 .lpsc
= DAVINCI_LPSC_UART0
,
207 static struct clk uart1_clk
= {
209 .parent
= &pll1_aux_clk
,
210 .lpsc
= DAVINCI_LPSC_UART1
,
213 static struct clk uart2_clk
= {
215 .parent
= &pll1_sysclk2
,
216 .lpsc
= DAVINCI_LPSC_UART2
,
219 static struct clk i2c_clk
= {
221 .parent
= &pll1_aux_clk
,
222 .lpsc
= DAVINCI_LPSC_I2C
,
225 static struct clk asp0_clk
= {
227 .parent
= &pll1_sysclk2
,
228 .lpsc
= DAVINCI_LPSC_McBSP
,
231 static struct clk asp1_clk
= {
233 .parent
= &pll1_sysclk2
,
234 .lpsc
= DM355_LPSC_McBSP1
,
237 static struct clk mmcsd0_clk
= {
239 .parent
= &pll1_sysclk2
,
240 .lpsc
= DAVINCI_LPSC_MMC_SD
,
243 static struct clk mmcsd1_clk
= {
245 .parent
= &pll1_sysclk2
,
246 .lpsc
= DM355_LPSC_MMC_SD1
,
249 static struct clk spi0_clk
= {
251 .parent
= &pll1_sysclk2
,
252 .lpsc
= DAVINCI_LPSC_SPI
,
255 static struct clk spi1_clk
= {
257 .parent
= &pll1_sysclk2
,
258 .lpsc
= DM355_LPSC_SPI1
,
261 static struct clk spi2_clk
= {
263 .parent
= &pll1_sysclk2
,
264 .lpsc
= DM355_LPSC_SPI2
,
267 static struct clk gpio_clk
= {
269 .parent
= &pll1_sysclk2
,
270 .lpsc
= DAVINCI_LPSC_GPIO
,
273 static struct clk aemif_clk
= {
275 .parent
= &pll1_sysclk2
,
276 .lpsc
= DAVINCI_LPSC_AEMIF
,
279 static struct clk pwm0_clk
= {
281 .parent
= &pll1_aux_clk
,
282 .lpsc
= DAVINCI_LPSC_PWM0
,
285 static struct clk pwm1_clk
= {
287 .parent
= &pll1_aux_clk
,
288 .lpsc
= DAVINCI_LPSC_PWM1
,
291 static struct clk pwm2_clk
= {
293 .parent
= &pll1_aux_clk
,
294 .lpsc
= DAVINCI_LPSC_PWM2
,
297 static struct clk pwm3_clk
= {
299 .parent
= &pll1_aux_clk
,
300 .lpsc
= DM355_LPSC_PWM3
,
303 static struct clk timer0_clk
= {
305 .parent
= &pll1_aux_clk
,
306 .lpsc
= DAVINCI_LPSC_TIMER0
,
309 static struct clk timer1_clk
= {
311 .parent
= &pll1_aux_clk
,
312 .lpsc
= DAVINCI_LPSC_TIMER1
,
315 static struct clk timer2_clk
= {
317 .parent
= &pll1_aux_clk
,
318 .lpsc
= DAVINCI_LPSC_TIMER2
,
319 .usecount
= 1, /* REVISIT: why can't this be disabled? */
322 static struct clk timer3_clk
= {
324 .parent
= &pll1_aux_clk
,
325 .lpsc
= DM355_LPSC_TIMER3
,
328 static struct clk rto_clk
= {
330 .parent
= &pll1_aux_clk
,
331 .lpsc
= DM355_LPSC_RTO
,
334 static struct clk usb_clk
= {
336 .parent
= &pll1_sysclk2
,
337 .lpsc
= DAVINCI_LPSC_USB
,
340 static struct clk_lookup dm355_clks
[] = {
341 CLK(NULL
, "ref", &ref_clk
),
342 CLK(NULL
, "pll1", &pll1_clk
),
343 CLK(NULL
, "pll1_sysclk1", &pll1_sysclk1
),
344 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
345 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
346 CLK(NULL
, "pll1_sysclk4", &pll1_sysclk4
),
347 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
348 CLK(NULL
, "pll1_sysclkbp", &pll1_sysclkbp
),
349 CLK(NULL
, "vpss_dac", &vpss_dac_clk
),
350 CLK("vpss", "master", &vpss_master_clk
),
351 CLK("vpss", "slave", &vpss_slave_clk
),
352 CLK(NULL
, "clkout1", &clkout1_clk
),
353 CLK(NULL
, "clkout2", &clkout2_clk
),
354 CLK(NULL
, "pll2", &pll2_clk
),
355 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
356 CLK(NULL
, "pll2_sysclkbp", &pll2_sysclkbp
),
357 CLK(NULL
, "clkout3", &clkout3_clk
),
358 CLK(NULL
, "arm", &arm_clk
),
359 CLK(NULL
, "mjcp", &mjcp_clk
),
360 CLK("serial8250.0", NULL
, &uart0_clk
),
361 CLK("serial8250.1", NULL
, &uart1_clk
),
362 CLK("serial8250.2", NULL
, &uart2_clk
),
363 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
364 CLK("davinci-mcbsp.0", NULL
, &asp0_clk
),
365 CLK("davinci-mcbsp.1", NULL
, &asp1_clk
),
366 CLK("dm6441-mmc.0", NULL
, &mmcsd0_clk
),
367 CLK("dm6441-mmc.1", NULL
, &mmcsd1_clk
),
368 CLK("spi_davinci.0", NULL
, &spi0_clk
),
369 CLK("spi_davinci.1", NULL
, &spi1_clk
),
370 CLK("spi_davinci.2", NULL
, &spi2_clk
),
371 CLK(NULL
, "gpio", &gpio_clk
),
372 CLK(NULL
, "aemif", &aemif_clk
),
373 CLK(NULL
, "pwm0", &pwm0_clk
),
374 CLK(NULL
, "pwm1", &pwm1_clk
),
375 CLK(NULL
, "pwm2", &pwm2_clk
),
376 CLK(NULL
, "pwm3", &pwm3_clk
),
377 CLK(NULL
, "timer0", &timer0_clk
),
378 CLK(NULL
, "timer1", &timer1_clk
),
379 CLK("watchdog", NULL
, &timer2_clk
),
380 CLK(NULL
, "timer3", &timer3_clk
),
381 CLK(NULL
, "rto", &rto_clk
),
382 CLK(NULL
, "usb", &usb_clk
),
383 CLK(NULL
, NULL
, NULL
),
386 /*----------------------------------------------------------------------*/
388 static u64 dm355_spi0_dma_mask
= DMA_BIT_MASK(32);
390 static struct resource dm355_spi0_resources
[] = {
394 .flags
= IORESOURCE_MEM
,
397 .start
= IRQ_DM355_SPINT0_0
,
398 .flags
= IORESOURCE_IRQ
,
402 .flags
= IORESOURCE_DMA
,
406 .flags
= IORESOURCE_DMA
,
410 static struct davinci_spi_platform_data dm355_spi0_pdata
= {
411 .version
= SPI_VERSION_1
,
414 .dma_event_q
= EVENTQ_1
,
416 static struct platform_device dm355_spi0_device
= {
417 .name
= "spi_davinci",
420 .dma_mask
= &dm355_spi0_dma_mask
,
421 .coherent_dma_mask
= DMA_BIT_MASK(32),
422 .platform_data
= &dm355_spi0_pdata
,
424 .num_resources
= ARRAY_SIZE(dm355_spi0_resources
),
425 .resource
= dm355_spi0_resources
,
428 void __init
dm355_init_spi0(unsigned chipselect_mask
,
429 const struct spi_board_info
*info
, unsigned len
)
431 /* for now, assume we need MISO */
432 davinci_cfg_reg(DM355_SPI0_SDI
);
434 /* not all slaves will be wired up */
435 if (chipselect_mask
& BIT(0))
436 davinci_cfg_reg(DM355_SPI0_SDENA0
);
437 if (chipselect_mask
& BIT(1))
438 davinci_cfg_reg(DM355_SPI0_SDENA1
);
440 spi_register_board_info(info
, len
);
442 platform_device_register(&dm355_spi0_device
);
445 /*----------------------------------------------------------------------*/
451 * Device specific mux setup
453 * soc description mux mode mode mux dbg
454 * reg offset mask mode
456 static const struct mux_config dm355_pins
[] = {
457 #ifdef CONFIG_DAVINCI_MUX
458 MUX_CFG(DM355
, MMCSD0
, 4, 2, 1, 0, false)
460 MUX_CFG(DM355
, SD1_CLK
, 3, 6, 1, 1, false)
461 MUX_CFG(DM355
, SD1_CMD
, 3, 7, 1, 1, false)
462 MUX_CFG(DM355
, SD1_DATA3
, 3, 8, 3, 1, false)
463 MUX_CFG(DM355
, SD1_DATA2
, 3, 10, 3, 1, false)
464 MUX_CFG(DM355
, SD1_DATA1
, 3, 12, 3, 1, false)
465 MUX_CFG(DM355
, SD1_DATA0
, 3, 14, 3, 1, false)
467 MUX_CFG(DM355
, I2C_SDA
, 3, 19, 1, 1, false)
468 MUX_CFG(DM355
, I2C_SCL
, 3, 20, 1, 1, false)
470 MUX_CFG(DM355
, MCBSP0_BDX
, 3, 0, 1, 1, false)
471 MUX_CFG(DM355
, MCBSP0_X
, 3, 1, 1, 1, false)
472 MUX_CFG(DM355
, MCBSP0_BFSX
, 3, 2, 1, 1, false)
473 MUX_CFG(DM355
, MCBSP0_BDR
, 3, 3, 1, 1, false)
474 MUX_CFG(DM355
, MCBSP0_R
, 3, 4, 1, 1, false)
475 MUX_CFG(DM355
, MCBSP0_BFSR
, 3, 5, 1, 1, false)
477 MUX_CFG(DM355
, SPI0_SDI
, 4, 1, 1, 0, false)
478 MUX_CFG(DM355
, SPI0_SDENA0
, 4, 0, 1, 0, false)
479 MUX_CFG(DM355
, SPI0_SDENA1
, 3, 28, 1, 1, false)
481 INT_CFG(DM355
, INT_EDMA_CC
, 2, 1, 1, false)
482 INT_CFG(DM355
, INT_EDMA_TC0_ERR
, 3, 1, 1, false)
483 INT_CFG(DM355
, INT_EDMA_TC1_ERR
, 4, 1, 1, false)
485 EVT_CFG(DM355
, EVT8_ASP1_TX
, 0, 1, 0, false)
486 EVT_CFG(DM355
, EVT9_ASP1_RX
, 1, 1, 0, false)
487 EVT_CFG(DM355
, EVT26_MMC0_RX
, 2, 1, 0, false)
489 MUX_CFG(DM355
, VOUT_FIELD
, 1, 18, 3, 1, false)
490 MUX_CFG(DM355
, VOUT_FIELD_G70
, 1, 18, 3, 0, false)
491 MUX_CFG(DM355
, VOUT_HVSYNC
, 1, 16, 1, 0, false)
492 MUX_CFG(DM355
, VOUT_COUTL_EN
, 1, 0, 0xff, 0x55, false)
493 MUX_CFG(DM355
, VOUT_COUTH_EN
, 1, 8, 0xff, 0x55, false)
495 MUX_CFG(DM355
, VIN_PCLK
, 0, 14, 1, 1, false)
496 MUX_CFG(DM355
, VIN_CAM_WEN
, 0, 13, 1, 1, false)
497 MUX_CFG(DM355
, VIN_CAM_VD
, 0, 12, 1, 1, false)
498 MUX_CFG(DM355
, VIN_CAM_HD
, 0, 11, 1, 1, false)
499 MUX_CFG(DM355
, VIN_YIN_EN
, 0, 10, 1, 1, false)
500 MUX_CFG(DM355
, VIN_CINL_EN
, 0, 0, 0xff, 0x55, false)
501 MUX_CFG(DM355
, VIN_CINH_EN
, 0, 8, 3, 3, false)
505 static u8 dm355_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
506 [IRQ_DM355_CCDC_VDINT0
] = 2,
507 [IRQ_DM355_CCDC_VDINT1
] = 6,
508 [IRQ_DM355_CCDC_VDINT2
] = 6,
509 [IRQ_DM355_IPIPE_HST
] = 6,
510 [IRQ_DM355_H3AINT
] = 6,
511 [IRQ_DM355_IPIPE_SDR
] = 6,
512 [IRQ_DM355_IPIPEIFINT
] = 6,
513 [IRQ_DM355_OSDINT
] = 7,
514 [IRQ_DM355_VENCINT
] = 6,
518 [IRQ_DM355_RTOINT
] = 4,
519 [IRQ_DM355_UARTINT2
] = 7,
520 [IRQ_DM355_TINT6
] = 7,
521 [IRQ_CCINT0
] = 5, /* dma */
522 [IRQ_CCERRINT
] = 5, /* dma */
523 [IRQ_TCERRINT0
] = 5, /* dma */
524 [IRQ_TCERRINT
] = 5, /* dma */
525 [IRQ_DM355_SPINT2_1
] = 7,
526 [IRQ_DM355_TINT7
] = 4,
527 [IRQ_DM355_SDIOINT0
] = 7,
531 [IRQ_DM355_MMCINT1
] = 7,
532 [IRQ_DM355_PWMINT3
] = 7,
535 [IRQ_DM355_SDIOINT1
] = 4,
536 [IRQ_TINT0_TINT12
] = 2, /* clockevent */
537 [IRQ_TINT0_TINT34
] = 2, /* clocksource */
538 [IRQ_TINT1_TINT12
] = 7, /* DSP timer */
539 [IRQ_TINT1_TINT34
] = 7, /* system tick */
546 [IRQ_DM355_SPINT0_0
] = 3,
547 [IRQ_DM355_SPINT0_1
] = 3,
548 [IRQ_DM355_GPIO0
] = 3,
549 [IRQ_DM355_GPIO1
] = 7,
550 [IRQ_DM355_GPIO2
] = 4,
551 [IRQ_DM355_GPIO3
] = 4,
552 [IRQ_DM355_GPIO4
] = 7,
553 [IRQ_DM355_GPIO5
] = 7,
554 [IRQ_DM355_GPIO6
] = 7,
555 [IRQ_DM355_GPIO7
] = 7,
556 [IRQ_DM355_GPIO8
] = 7,
557 [IRQ_DM355_GPIO9
] = 7,
558 [IRQ_DM355_GPIOBNK0
] = 7,
559 [IRQ_DM355_GPIOBNK1
] = 7,
560 [IRQ_DM355_GPIOBNK2
] = 7,
561 [IRQ_DM355_GPIOBNK3
] = 7,
562 [IRQ_DM355_GPIOBNK4
] = 7,
563 [IRQ_DM355_GPIOBNK5
] = 7,
564 [IRQ_DM355_GPIOBNK6
] = 7,
570 /*----------------------------------------------------------------------*/
573 queue_tc_mapping
[][2] = {
574 /* {event queue no, TC no} */
581 queue_priority_mapping
[][2] = {
582 /* {event queue no, Priority} */
588 static struct edma_soc_info edma_cc0_info
= {
594 .queue_tc_mapping
= queue_tc_mapping
,
595 .queue_priority_mapping
= queue_priority_mapping
,
596 .default_queue
= EVENTQ_1
,
599 static struct edma_soc_info
*dm355_edma_info
[EDMA_MAX_CC
] = {
603 static struct resource edma_resources
[] = {
607 .end
= 0x01c00000 + SZ_64K
- 1,
608 .flags
= IORESOURCE_MEM
,
613 .end
= 0x01c10000 + SZ_1K
- 1,
614 .flags
= IORESOURCE_MEM
,
619 .end
= 0x01c10400 + SZ_1K
- 1,
620 .flags
= IORESOURCE_MEM
,
625 .flags
= IORESOURCE_IRQ
,
629 .start
= IRQ_CCERRINT
,
630 .flags
= IORESOURCE_IRQ
,
632 /* not using (or muxing) TC*_ERR */
635 static struct platform_device dm355_edma_device
= {
638 .dev
.platform_data
= dm355_edma_info
,
639 .num_resources
= ARRAY_SIZE(edma_resources
),
640 .resource
= edma_resources
,
643 static struct resource dm355_asp1_resources
[] = {
645 .start
= DAVINCI_ASP1_BASE
,
646 .end
= DAVINCI_ASP1_BASE
+ SZ_8K
- 1,
647 .flags
= IORESOURCE_MEM
,
650 .start
= DAVINCI_DMA_ASP1_TX
,
651 .end
= DAVINCI_DMA_ASP1_TX
,
652 .flags
= IORESOURCE_DMA
,
655 .start
= DAVINCI_DMA_ASP1_RX
,
656 .end
= DAVINCI_DMA_ASP1_RX
,
657 .flags
= IORESOURCE_DMA
,
661 static struct platform_device dm355_asp1_device
= {
662 .name
= "davinci-mcbsp",
664 .num_resources
= ARRAY_SIZE(dm355_asp1_resources
),
665 .resource
= dm355_asp1_resources
,
668 static void dm355_ccdc_setup_pinmux(void)
670 davinci_cfg_reg(DM355_VIN_PCLK
);
671 davinci_cfg_reg(DM355_VIN_CAM_WEN
);
672 davinci_cfg_reg(DM355_VIN_CAM_VD
);
673 davinci_cfg_reg(DM355_VIN_CAM_HD
);
674 davinci_cfg_reg(DM355_VIN_YIN_EN
);
675 davinci_cfg_reg(DM355_VIN_CINL_EN
);
676 davinci_cfg_reg(DM355_VIN_CINH_EN
);
679 static struct resource dm355_vpss_resources
[] = {
681 /* VPSS BL Base address */
684 .end
= 0x01c70800 + 0xff,
685 .flags
= IORESOURCE_MEM
,
688 /* VPSS CLK Base address */
691 .end
= 0x01c70000 + 0xf,
692 .flags
= IORESOURCE_MEM
,
696 static struct platform_device dm355_vpss_device
= {
699 .dev
.platform_data
= "dm355_vpss",
700 .num_resources
= ARRAY_SIZE(dm355_vpss_resources
),
701 .resource
= dm355_vpss_resources
,
704 static struct resource vpfe_resources
[] = {
708 .flags
= IORESOURCE_IRQ
,
713 .flags
= IORESOURCE_IRQ
,
717 static u64 vpfe_capture_dma_mask
= DMA_BIT_MASK(32);
718 static struct resource dm355_ccdc_resource
[] = {
719 /* CCDC Base address */
721 .flags
= IORESOURCE_MEM
,
723 .end
= 0x01c70600 + 0x1ff,
726 static struct platform_device dm355_ccdc_dev
= {
727 .name
= "dm355_ccdc",
729 .num_resources
= ARRAY_SIZE(dm355_ccdc_resource
),
730 .resource
= dm355_ccdc_resource
,
732 .dma_mask
= &vpfe_capture_dma_mask
,
733 .coherent_dma_mask
= DMA_BIT_MASK(32),
734 .platform_data
= dm355_ccdc_setup_pinmux
,
738 static struct platform_device vpfe_capture_dev
= {
739 .name
= CAPTURE_DRV_NAME
,
741 .num_resources
= ARRAY_SIZE(vpfe_resources
),
742 .resource
= vpfe_resources
,
744 .dma_mask
= &vpfe_capture_dma_mask
,
745 .coherent_dma_mask
= DMA_BIT_MASK(32),
749 static struct resource dm355_osd_resources
[] = {
751 .start
= DM355_OSD_BASE
,
752 .end
= DM355_OSD_BASE
+ 0x17f,
753 .flags
= IORESOURCE_MEM
,
757 static struct platform_device dm355_osd_dev
= {
758 .name
= DM355_VPBE_OSD_SUBDEV_NAME
,
760 .num_resources
= ARRAY_SIZE(dm355_osd_resources
),
761 .resource
= dm355_osd_resources
,
763 .dma_mask
= &vpfe_capture_dma_mask
,
764 .coherent_dma_mask
= DMA_BIT_MASK(32),
768 static struct resource dm355_venc_resources
[] = {
770 .start
= IRQ_VENCINT
,
772 .flags
= IORESOURCE_IRQ
,
774 /* venc registers io space */
776 .start
= DM355_VENC_BASE
,
777 .end
= DM355_VENC_BASE
+ 0x17f,
778 .flags
= IORESOURCE_MEM
,
780 /* VDAC config register io space */
782 .start
= DAVINCI_SYSTEM_MODULE_BASE
+ SYSMOD_VDAC_CONFIG
,
783 .end
= DAVINCI_SYSTEM_MODULE_BASE
+ SYSMOD_VDAC_CONFIG
+ 3,
784 .flags
= IORESOURCE_MEM
,
788 static struct resource dm355_v4l2_disp_resources
[] = {
790 .start
= IRQ_VENCINT
,
792 .flags
= IORESOURCE_IRQ
,
794 /* venc registers io space */
796 .start
= DM355_VENC_BASE
,
797 .end
= DM355_VENC_BASE
+ 0x17f,
798 .flags
= IORESOURCE_MEM
,
802 static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type
,
806 case V4L2_MBUS_FMT_SGRBG8_1X8
:
807 davinci_cfg_reg(DM355_VOUT_FIELD_G70
);
809 case V4L2_MBUS_FMT_YUYV10_1X20
:
811 davinci_cfg_reg(DM355_VOUT_FIELD
);
813 davinci_cfg_reg(DM355_VOUT_FIELD_G70
);
819 davinci_cfg_reg(DM355_VOUT_COUTL_EN
);
820 davinci_cfg_reg(DM355_VOUT_COUTH_EN
);
825 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type
,
828 void __iomem
*vpss_clk_ctrl_reg
;
830 vpss_clk_ctrl_reg
= DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL
);
834 writel(VPSS_DACCLKEN_ENABLE
| VPSS_VENCCLKEN_ENABLE
,
837 case VPBE_ENC_DV_TIMINGS
:
838 if (pclock
> 27000000)
840 * For HD, use external clock source since we cannot
841 * support HD mode with internal clocks.
843 writel(VPSS_MUXSEL_EXTCLK_ENABLE
, vpss_clk_ctrl_reg
);
852 static struct platform_device dm355_vpbe_display
= {
855 .num_resources
= ARRAY_SIZE(dm355_v4l2_disp_resources
),
856 .resource
= dm355_v4l2_disp_resources
,
858 .dma_mask
= &vpfe_capture_dma_mask
,
859 .coherent_dma_mask
= DMA_BIT_MASK(32),
863 static struct venc_platform_data dm355_venc_pdata
= {
864 .setup_pinmux
= dm355_vpbe_setup_pinmux
,
865 .setup_clock
= dm355_venc_setup_clock
,
868 static struct platform_device dm355_venc_dev
= {
869 .name
= DM355_VPBE_VENC_SUBDEV_NAME
,
871 .num_resources
= ARRAY_SIZE(dm355_venc_resources
),
872 .resource
= dm355_venc_resources
,
874 .dma_mask
= &vpfe_capture_dma_mask
,
875 .coherent_dma_mask
= DMA_BIT_MASK(32),
876 .platform_data
= (void *)&dm355_venc_pdata
,
880 static struct platform_device dm355_vpbe_dev
= {
881 .name
= "vpbe_controller",
884 .dma_mask
= &vpfe_capture_dma_mask
,
885 .coherent_dma_mask
= DMA_BIT_MASK(32),
889 /*----------------------------------------------------------------------*/
891 static struct map_desc dm355_io_desc
[] = {
894 .pfn
= __phys_to_pfn(IO_PHYS
),
900 /* Contents of JTAG ID register used to identify exact cpu type */
901 static struct davinci_id dm355_ids
[] = {
905 .manufacturer
= 0x00f,
906 .cpu_id
= DAVINCI_CPU_ID_DM355
,
911 static u32 dm355_psc_bases
[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE
};
914 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
915 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
916 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
917 * T1_TOP: Timer 1, top : <unused>
919 static struct davinci_timer_info dm355_timer_info
= {
920 .timers
= davinci_timer_instance
,
921 .clockevent_id
= T0_BOT
,
922 .clocksource_id
= T0_TOP
,
925 static struct plat_serial8250_port dm355_serial0_platform_data
[] = {
927 .mapbase
= DAVINCI_UART0_BASE
,
929 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
938 static struct plat_serial8250_port dm355_serial1_platform_data
[] = {
940 .mapbase
= DAVINCI_UART1_BASE
,
942 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
951 static struct plat_serial8250_port dm355_serial2_platform_data
[] = {
953 .mapbase
= DM355_UART2_BASE
,
954 .irq
= IRQ_DM355_UARTINT2
,
955 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
965 struct platform_device dm355_serial_device
[] = {
967 .name
= "serial8250",
968 .id
= PLAT8250_DEV_PLATFORM
,
970 .platform_data
= dm355_serial0_platform_data
,
974 .name
= "serial8250",
975 .id
= PLAT8250_DEV_PLATFORM1
,
977 .platform_data
= dm355_serial1_platform_data
,
981 .name
= "serial8250",
982 .id
= PLAT8250_DEV_PLATFORM2
,
984 .platform_data
= dm355_serial2_platform_data
,
991 static struct davinci_soc_info davinci_soc_info_dm355
= {
992 .io_desc
= dm355_io_desc
,
993 .io_desc_num
= ARRAY_SIZE(dm355_io_desc
),
994 .jtag_id_reg
= 0x01c40028,
996 .ids_num
= ARRAY_SIZE(dm355_ids
),
997 .cpu_clks
= dm355_clks
,
998 .psc_bases
= dm355_psc_bases
,
999 .psc_bases_num
= ARRAY_SIZE(dm355_psc_bases
),
1000 .pinmux_base
= DAVINCI_SYSTEM_MODULE_BASE
,
1001 .pinmux_pins
= dm355_pins
,
1002 .pinmux_pins_num
= ARRAY_SIZE(dm355_pins
),
1003 .intc_base
= DAVINCI_ARM_INTC_BASE
,
1004 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
1005 .intc_irq_prios
= dm355_default_priorities
,
1006 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
1007 .timer_info
= &dm355_timer_info
,
1008 .gpio_type
= GPIO_TYPE_DAVINCI
,
1009 .gpio_base
= DAVINCI_GPIO_BASE
,
1011 .gpio_irq
= IRQ_DM355_GPIOBNK0
,
1012 .sram_dma
= 0x00010000,
1016 void __init
dm355_init_asp1(u32 evt_enable
, struct snd_platform_data
*pdata
)
1018 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
1019 if (evt_enable
& ASP1_TX_EVT_EN
)
1020 davinci_cfg_reg(DM355_EVT8_ASP1_TX
);
1022 if (evt_enable
& ASP1_RX_EVT_EN
)
1023 davinci_cfg_reg(DM355_EVT9_ASP1_RX
);
1025 dm355_asp1_device
.dev
.platform_data
= pdata
;
1026 platform_device_register(&dm355_asp1_device
);
1029 void __init
dm355_init(void)
1031 davinci_common_init(&davinci_soc_info_dm355
);
1032 davinci_map_sysmod();
1035 int __init
dm355_init_video(struct vpfe_config
*vpfe_cfg
,
1036 struct vpbe_config
*vpbe_cfg
)
1038 if (vpfe_cfg
|| vpbe_cfg
)
1039 platform_device_register(&dm355_vpss_device
);
1042 vpfe_capture_dev
.dev
.platform_data
= vpfe_cfg
;
1043 platform_device_register(&dm355_ccdc_dev
);
1044 platform_device_register(&vpfe_capture_dev
);
1048 dm355_vpbe_dev
.dev
.platform_data
= vpbe_cfg
;
1049 platform_device_register(&dm355_osd_dev
);
1050 platform_device_register(&dm355_venc_dev
);
1051 platform_device_register(&dm355_vpbe_dev
);
1052 platform_device_register(&dm355_vpbe_display
);
1058 static int __init
dm355_init_devices(void)
1060 if (!cpu_is_davinci_dm355())
1063 davinci_cfg_reg(DM355_INT_EDMA_CC
);
1064 platform_device_register(&dm355_edma_device
);
1068 postcore_initcall(dm355_init_devices
);