2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/edma.h>
17 #include <asm/mach/map.h>
19 #include <mach/cputype.h>
20 #include <mach/irqs.h>
23 #include <mach/time.h>
24 #include <mach/serial.h>
25 #include <mach/common.h>
26 #include <mach/gpio-davinci.h>
34 * Device specific clocks
36 #define DM644X_REF_FREQ 27000000
38 #define DM644X_EMAC_BASE 0x01c80000
39 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
40 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
41 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
42 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
43 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
45 static struct pll_data pll1_data
= {
47 .phys_base
= DAVINCI_PLL1_BASE
,
50 static struct pll_data pll2_data
= {
52 .phys_base
= DAVINCI_PLL2_BASE
,
55 static struct clk ref_clk
= {
57 .rate
= DM644X_REF_FREQ
,
60 static struct clk pll1_clk
= {
63 .pll_data
= &pll1_data
,
67 static struct clk pll1_sysclk1
= {
68 .name
= "pll1_sysclk1",
74 static struct clk pll1_sysclk2
= {
75 .name
= "pll1_sysclk2",
81 static struct clk pll1_sysclk3
= {
82 .name
= "pll1_sysclk3",
88 static struct clk pll1_sysclk5
= {
89 .name
= "pll1_sysclk5",
95 static struct clk pll1_aux_clk
= {
96 .name
= "pll1_aux_clk",
98 .flags
= CLK_PLL
| PRE_PLL
,
101 static struct clk pll1_sysclkbp
= {
102 .name
= "pll1_sysclkbp",
104 .flags
= CLK_PLL
| PRE_PLL
,
108 static struct clk pll2_clk
= {
111 .pll_data
= &pll2_data
,
115 static struct clk pll2_sysclk1
= {
116 .name
= "pll2_sysclk1",
122 static struct clk pll2_sysclk2
= {
123 .name
= "pll2_sysclk2",
129 static struct clk pll2_sysclkbp
= {
130 .name
= "pll2_sysclkbp",
132 .flags
= CLK_PLL
| PRE_PLL
,
136 static struct clk dsp_clk
= {
138 .parent
= &pll1_sysclk1
,
139 .lpsc
= DAVINCI_LPSC_GEM
,
140 .domain
= DAVINCI_GPSC_DSPDOMAIN
,
141 .usecount
= 1, /* REVISIT how to disable? */
144 static struct clk arm_clk
= {
146 .parent
= &pll1_sysclk2
,
147 .lpsc
= DAVINCI_LPSC_ARM
,
148 .flags
= ALWAYS_ENABLED
,
151 static struct clk vicp_clk
= {
153 .parent
= &pll1_sysclk2
,
154 .lpsc
= DAVINCI_LPSC_IMCOP
,
155 .domain
= DAVINCI_GPSC_DSPDOMAIN
,
156 .usecount
= 1, /* REVISIT how to disable? */
159 static struct clk vpss_master_clk
= {
160 .name
= "vpss_master",
161 .parent
= &pll1_sysclk3
,
162 .lpsc
= DAVINCI_LPSC_VPSSMSTR
,
166 static struct clk vpss_slave_clk
= {
167 .name
= "vpss_slave",
168 .parent
= &pll1_sysclk3
,
169 .lpsc
= DAVINCI_LPSC_VPSSSLV
,
172 static struct clk uart0_clk
= {
174 .parent
= &pll1_aux_clk
,
175 .lpsc
= DAVINCI_LPSC_UART0
,
178 static struct clk uart1_clk
= {
180 .parent
= &pll1_aux_clk
,
181 .lpsc
= DAVINCI_LPSC_UART1
,
184 static struct clk uart2_clk
= {
186 .parent
= &pll1_aux_clk
,
187 .lpsc
= DAVINCI_LPSC_UART2
,
190 static struct clk emac_clk
= {
192 .parent
= &pll1_sysclk5
,
193 .lpsc
= DAVINCI_LPSC_EMAC_WRAPPER
,
196 static struct clk i2c_clk
= {
198 .parent
= &pll1_aux_clk
,
199 .lpsc
= DAVINCI_LPSC_I2C
,
202 static struct clk ide_clk
= {
204 .parent
= &pll1_sysclk5
,
205 .lpsc
= DAVINCI_LPSC_ATA
,
208 static struct clk asp_clk
= {
210 .parent
= &pll1_sysclk5
,
211 .lpsc
= DAVINCI_LPSC_McBSP
,
214 static struct clk mmcsd_clk
= {
216 .parent
= &pll1_sysclk5
,
217 .lpsc
= DAVINCI_LPSC_MMC_SD
,
220 static struct clk spi_clk
= {
222 .parent
= &pll1_sysclk5
,
223 .lpsc
= DAVINCI_LPSC_SPI
,
226 static struct clk gpio_clk
= {
228 .parent
= &pll1_sysclk5
,
229 .lpsc
= DAVINCI_LPSC_GPIO
,
232 static struct clk usb_clk
= {
234 .parent
= &pll1_sysclk5
,
235 .lpsc
= DAVINCI_LPSC_USB
,
238 static struct clk vlynq_clk
= {
240 .parent
= &pll1_sysclk5
,
241 .lpsc
= DAVINCI_LPSC_VLYNQ
,
244 static struct clk aemif_clk
= {
246 .parent
= &pll1_sysclk5
,
247 .lpsc
= DAVINCI_LPSC_AEMIF
,
250 static struct clk pwm0_clk
= {
252 .parent
= &pll1_aux_clk
,
253 .lpsc
= DAVINCI_LPSC_PWM0
,
256 static struct clk pwm1_clk
= {
258 .parent
= &pll1_aux_clk
,
259 .lpsc
= DAVINCI_LPSC_PWM1
,
262 static struct clk pwm2_clk
= {
264 .parent
= &pll1_aux_clk
,
265 .lpsc
= DAVINCI_LPSC_PWM2
,
268 static struct clk timer0_clk
= {
270 .parent
= &pll1_aux_clk
,
271 .lpsc
= DAVINCI_LPSC_TIMER0
,
274 static struct clk timer1_clk
= {
276 .parent
= &pll1_aux_clk
,
277 .lpsc
= DAVINCI_LPSC_TIMER1
,
280 static struct clk timer2_clk
= {
282 .parent
= &pll1_aux_clk
,
283 .lpsc
= DAVINCI_LPSC_TIMER2
,
284 .usecount
= 1, /* REVISIT: why can't this be disabled? */
287 static struct clk_lookup dm644x_clks
[] = {
288 CLK(NULL
, "ref", &ref_clk
),
289 CLK(NULL
, "pll1", &pll1_clk
),
290 CLK(NULL
, "pll1_sysclk1", &pll1_sysclk1
),
291 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
292 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
293 CLK(NULL
, "pll1_sysclk5", &pll1_sysclk5
),
294 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
295 CLK(NULL
, "pll1_sysclkbp", &pll1_sysclkbp
),
296 CLK(NULL
, "pll2", &pll2_clk
),
297 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
298 CLK(NULL
, "pll2_sysclk2", &pll2_sysclk2
),
299 CLK(NULL
, "pll2_sysclkbp", &pll2_sysclkbp
),
300 CLK(NULL
, "dsp", &dsp_clk
),
301 CLK(NULL
, "arm", &arm_clk
),
302 CLK(NULL
, "vicp", &vicp_clk
),
303 CLK("vpss", "master", &vpss_master_clk
),
304 CLK("vpss", "slave", &vpss_slave_clk
),
305 CLK(NULL
, "arm", &arm_clk
),
306 CLK("serial8250.0", NULL
, &uart0_clk
),
307 CLK("serial8250.1", NULL
, &uart1_clk
),
308 CLK("serial8250.2", NULL
, &uart2_clk
),
309 CLK("davinci_emac.1", NULL
, &emac_clk
),
310 CLK("davinci_mdio.0", "fck", &emac_clk
),
311 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
312 CLK("palm_bk3710", NULL
, &ide_clk
),
313 CLK("davinci-mcbsp", NULL
, &asp_clk
),
314 CLK("dm6441-mmc.0", NULL
, &mmcsd_clk
),
315 CLK(NULL
, "spi", &spi_clk
),
316 CLK(NULL
, "gpio", &gpio_clk
),
317 CLK(NULL
, "usb", &usb_clk
),
318 CLK(NULL
, "vlynq", &vlynq_clk
),
319 CLK(NULL
, "aemif", &aemif_clk
),
320 CLK(NULL
, "pwm0", &pwm0_clk
),
321 CLK(NULL
, "pwm1", &pwm1_clk
),
322 CLK(NULL
, "pwm2", &pwm2_clk
),
323 CLK(NULL
, "timer0", &timer0_clk
),
324 CLK(NULL
, "timer1", &timer1_clk
),
325 CLK("watchdog", NULL
, &timer2_clk
),
326 CLK(NULL
, NULL
, NULL
),
329 static struct emac_platform_data dm644x_emac_pdata
= {
330 .ctrl_reg_offset
= DM644X_EMAC_CNTRL_OFFSET
,
331 .ctrl_mod_reg_offset
= DM644X_EMAC_CNTRL_MOD_OFFSET
,
332 .ctrl_ram_offset
= DM644X_EMAC_CNTRL_RAM_OFFSET
,
333 .ctrl_ram_size
= DM644X_EMAC_CNTRL_RAM_SIZE
,
334 .version
= EMAC_VERSION_1
,
337 static struct resource dm644x_emac_resources
[] = {
339 .start
= DM644X_EMAC_BASE
,
340 .end
= DM644X_EMAC_BASE
+ SZ_16K
- 1,
341 .flags
= IORESOURCE_MEM
,
344 .start
= IRQ_EMACINT
,
346 .flags
= IORESOURCE_IRQ
,
350 static struct platform_device dm644x_emac_device
= {
351 .name
= "davinci_emac",
354 .platform_data
= &dm644x_emac_pdata
,
356 .num_resources
= ARRAY_SIZE(dm644x_emac_resources
),
357 .resource
= dm644x_emac_resources
,
360 static struct resource dm644x_mdio_resources
[] = {
362 .start
= DM644X_EMAC_MDIO_BASE
,
363 .end
= DM644X_EMAC_MDIO_BASE
+ SZ_4K
- 1,
364 .flags
= IORESOURCE_MEM
,
368 static struct platform_device dm644x_mdio_device
= {
369 .name
= "davinci_mdio",
371 .num_resources
= ARRAY_SIZE(dm644x_mdio_resources
),
372 .resource
= dm644x_mdio_resources
,
376 * Device specific mux setup
378 * soc description mux mode mode mux dbg
379 * reg offset mask mode
381 static const struct mux_config dm644x_pins
[] = {
382 #ifdef CONFIG_DAVINCI_MUX
383 MUX_CFG(DM644X
, HDIREN
, 0, 16, 1, 1, true)
384 MUX_CFG(DM644X
, ATAEN
, 0, 17, 1, 1, true)
385 MUX_CFG(DM644X
, ATAEN_DISABLE
, 0, 17, 1, 0, true)
387 MUX_CFG(DM644X
, HPIEN_DISABLE
, 0, 29, 1, 0, true)
389 MUX_CFG(DM644X
, AEAW
, 0, 0, 31, 31, true)
390 MUX_CFG(DM644X
, AEAW0
, 0, 0, 1, 0, true)
391 MUX_CFG(DM644X
, AEAW1
, 0, 1, 1, 0, true)
392 MUX_CFG(DM644X
, AEAW2
, 0, 2, 1, 0, true)
393 MUX_CFG(DM644X
, AEAW3
, 0, 3, 1, 0, true)
394 MUX_CFG(DM644X
, AEAW4
, 0, 4, 1, 0, true)
396 MUX_CFG(DM644X
, MSTK
, 1, 9, 1, 0, false)
398 MUX_CFG(DM644X
, I2C
, 1, 7, 1, 1, false)
400 MUX_CFG(DM644X
, MCBSP
, 1, 10, 1, 1, false)
402 MUX_CFG(DM644X
, UART1
, 1, 1, 1, 1, true)
403 MUX_CFG(DM644X
, UART2
, 1, 2, 1, 1, true)
405 MUX_CFG(DM644X
, PWM0
, 1, 4, 1, 1, false)
407 MUX_CFG(DM644X
, PWM1
, 1, 5, 1, 1, false)
409 MUX_CFG(DM644X
, PWM2
, 1, 6, 1, 1, false)
411 MUX_CFG(DM644X
, VLYNQEN
, 0, 15, 1, 1, false)
412 MUX_CFG(DM644X
, VLSCREN
, 0, 14, 1, 1, false)
413 MUX_CFG(DM644X
, VLYNQWD
, 0, 12, 3, 3, false)
415 MUX_CFG(DM644X
, EMACEN
, 0, 31, 1, 1, true)
417 MUX_CFG(DM644X
, GPIO3V
, 0, 31, 1, 0, true)
419 MUX_CFG(DM644X
, GPIO0
, 0, 24, 1, 0, true)
420 MUX_CFG(DM644X
, GPIO3
, 0, 25, 1, 0, false)
421 MUX_CFG(DM644X
, GPIO43_44
, 1, 7, 1, 0, false)
422 MUX_CFG(DM644X
, GPIO46_47
, 0, 22, 1, 0, true)
424 MUX_CFG(DM644X
, RGB666
, 0, 22, 1, 1, true)
426 MUX_CFG(DM644X
, LOEEN
, 0, 24, 1, 1, true)
427 MUX_CFG(DM644X
, LFLDEN
, 0, 25, 1, 1, false)
431 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
432 static u8 dm644x_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
449 [IRQ_CCINT0
] = 5, /* dma */
450 [IRQ_CCERRINT
] = 5, /* dma */
451 [IRQ_TCERRINT0
] = 5, /* dma */
452 [IRQ_TCERRINT
] = 5, /* dma */
465 [IRQ_TINT0_TINT12
] = 2, /* clockevent */
466 [IRQ_TINT0_TINT34
] = 2, /* clocksource */
467 [IRQ_TINT1_TINT12
] = 7, /* DSP timer */
468 [IRQ_TINT1_TINT34
] = 7, /* system tick */
499 /*----------------------------------------------------------------------*/
502 queue_tc_mapping
[][2] = {
503 /* {event queue no, TC no} */
510 queue_priority_mapping
[][2] = {
511 /* {event queue no, Priority} */
517 static struct edma_soc_info edma_cc0_info
= {
523 .queue_tc_mapping
= queue_tc_mapping
,
524 .queue_priority_mapping
= queue_priority_mapping
,
525 .default_queue
= EVENTQ_1
,
528 static struct edma_soc_info
*dm644x_edma_info
[EDMA_MAX_CC
] = {
532 static struct resource edma_resources
[] = {
536 .end
= 0x01c00000 + SZ_64K
- 1,
537 .flags
= IORESOURCE_MEM
,
542 .end
= 0x01c10000 + SZ_1K
- 1,
543 .flags
= IORESOURCE_MEM
,
548 .end
= 0x01c10400 + SZ_1K
- 1,
549 .flags
= IORESOURCE_MEM
,
554 .flags
= IORESOURCE_IRQ
,
558 .start
= IRQ_CCERRINT
,
559 .flags
= IORESOURCE_IRQ
,
561 /* not using TC*_ERR */
564 static struct platform_device dm644x_edma_device
= {
567 .dev
.platform_data
= dm644x_edma_info
,
568 .num_resources
= ARRAY_SIZE(edma_resources
),
569 .resource
= edma_resources
,
572 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
573 static struct resource dm644x_asp_resources
[] = {
575 .start
= DAVINCI_ASP0_BASE
,
576 .end
= DAVINCI_ASP0_BASE
+ SZ_8K
- 1,
577 .flags
= IORESOURCE_MEM
,
580 .start
= DAVINCI_DMA_ASP0_TX
,
581 .end
= DAVINCI_DMA_ASP0_TX
,
582 .flags
= IORESOURCE_DMA
,
585 .start
= DAVINCI_DMA_ASP0_RX
,
586 .end
= DAVINCI_DMA_ASP0_RX
,
587 .flags
= IORESOURCE_DMA
,
591 static struct platform_device dm644x_asp_device
= {
592 .name
= "davinci-mcbsp",
594 .num_resources
= ARRAY_SIZE(dm644x_asp_resources
),
595 .resource
= dm644x_asp_resources
,
598 #define DM644X_VPSS_BASE 0x01c73400
600 static struct resource dm644x_vpss_resources
[] = {
602 /* VPSS Base address */
604 .start
= DM644X_VPSS_BASE
,
605 .end
= DM644X_VPSS_BASE
+ 0xff,
606 .flags
= IORESOURCE_MEM
,
610 static struct platform_device dm644x_vpss_device
= {
613 .dev
.platform_data
= "dm644x_vpss",
614 .num_resources
= ARRAY_SIZE(dm644x_vpss_resources
),
615 .resource
= dm644x_vpss_resources
,
618 static struct resource dm644x_vpfe_resources
[] = {
622 .flags
= IORESOURCE_IRQ
,
627 .flags
= IORESOURCE_IRQ
,
631 static u64 dm644x_video_dma_mask
= DMA_BIT_MASK(32);
632 static struct resource dm644x_ccdc_resource
[] = {
633 /* CCDC Base address */
636 .end
= 0x01c70400 + 0xff,
637 .flags
= IORESOURCE_MEM
,
641 static struct platform_device dm644x_ccdc_dev
= {
642 .name
= "dm644x_ccdc",
644 .num_resources
= ARRAY_SIZE(dm644x_ccdc_resource
),
645 .resource
= dm644x_ccdc_resource
,
647 .dma_mask
= &dm644x_video_dma_mask
,
648 .coherent_dma_mask
= DMA_BIT_MASK(32),
652 static struct platform_device dm644x_vpfe_dev
= {
653 .name
= CAPTURE_DRV_NAME
,
655 .num_resources
= ARRAY_SIZE(dm644x_vpfe_resources
),
656 .resource
= dm644x_vpfe_resources
,
658 .dma_mask
= &dm644x_video_dma_mask
,
659 .coherent_dma_mask
= DMA_BIT_MASK(32),
663 #define DM644X_OSD_BASE 0x01c72600
665 static struct resource dm644x_osd_resources
[] = {
667 .start
= DM644X_OSD_BASE
,
668 .end
= DM644X_OSD_BASE
+ 0x1ff,
669 .flags
= IORESOURCE_MEM
,
673 static struct platform_device dm644x_osd_dev
= {
674 .name
= DM644X_VPBE_OSD_SUBDEV_NAME
,
676 .num_resources
= ARRAY_SIZE(dm644x_osd_resources
),
677 .resource
= dm644x_osd_resources
,
679 .dma_mask
= &dm644x_video_dma_mask
,
680 .coherent_dma_mask
= DMA_BIT_MASK(32),
684 #define DM644X_VENC_BASE 0x01c72400
686 static struct resource dm644x_venc_resources
[] = {
688 .start
= DM644X_VENC_BASE
,
689 .end
= DM644X_VENC_BASE
+ 0x17f,
690 .flags
= IORESOURCE_MEM
,
694 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
695 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
696 #define DM644X_VPSS_VENCLKEN BIT(3)
697 #define DM644X_VPSS_DACCLKEN BIT(4)
699 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type
,
703 u32 v
= DM644X_VPSS_VENCLKEN
;
707 v
|= DM644X_VPSS_DACCLKEN
;
708 writel(v
, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL
));
710 case VPBE_ENC_DV_TIMINGS
:
711 if (pclock
<= 27000000) {
712 v
|= DM644X_VPSS_DACCLKEN
;
713 writel(v
, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL
));
716 * For HD, use external clock source since
717 * HD requires higher clock rate
719 v
|= DM644X_VPSS_MUXSEL_VPBECLK_MODE
;
720 writel(v
, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL
));
730 static struct resource dm644x_v4l2_disp_resources
[] = {
732 .start
= IRQ_VENCINT
,
734 .flags
= IORESOURCE_IRQ
,
738 static struct platform_device dm644x_vpbe_display
= {
741 .num_resources
= ARRAY_SIZE(dm644x_v4l2_disp_resources
),
742 .resource
= dm644x_v4l2_disp_resources
,
744 .dma_mask
= &dm644x_video_dma_mask
,
745 .coherent_dma_mask
= DMA_BIT_MASK(32),
749 static struct venc_platform_data dm644x_venc_pdata
= {
750 .setup_clock
= dm644x_venc_setup_clock
,
753 static struct platform_device dm644x_venc_dev
= {
754 .name
= DM644X_VPBE_VENC_SUBDEV_NAME
,
756 .num_resources
= ARRAY_SIZE(dm644x_venc_resources
),
757 .resource
= dm644x_venc_resources
,
759 .dma_mask
= &dm644x_video_dma_mask
,
760 .coherent_dma_mask
= DMA_BIT_MASK(32),
761 .platform_data
= &dm644x_venc_pdata
,
765 static struct platform_device dm644x_vpbe_dev
= {
766 .name
= "vpbe_controller",
769 .dma_mask
= &dm644x_video_dma_mask
,
770 .coherent_dma_mask
= DMA_BIT_MASK(32),
774 /*----------------------------------------------------------------------*/
776 static struct map_desc dm644x_io_desc
[] = {
779 .pfn
= __phys_to_pfn(IO_PHYS
),
785 /* Contents of JTAG ID register used to identify exact cpu type */
786 static struct davinci_id dm644x_ids
[] = {
790 .manufacturer
= 0x017,
791 .cpu_id
= DAVINCI_CPU_ID_DM6446
,
797 .manufacturer
= 0x017,
798 .cpu_id
= DAVINCI_CPU_ID_DM6446
,
803 static u32 dm644x_psc_bases
[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE
};
806 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
807 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
808 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
809 * T1_TOP: Timer 1, top : <unused>
811 static struct davinci_timer_info dm644x_timer_info
= {
812 .timers
= davinci_timer_instance
,
813 .clockevent_id
= T0_BOT
,
814 .clocksource_id
= T0_TOP
,
817 static struct plat_serial8250_port dm644x_serial0_platform_data
[] = {
819 .mapbase
= DAVINCI_UART0_BASE
,
821 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
830 static struct plat_serial8250_port dm644x_serial1_platform_data
[] = {
832 .mapbase
= DAVINCI_UART1_BASE
,
834 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
843 static struct plat_serial8250_port dm644x_serial2_platform_data
[] = {
845 .mapbase
= DAVINCI_UART2_BASE
,
847 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
857 struct platform_device dm644x_serial_device
[] = {
859 .name
= "serial8250",
860 .id
= PLAT8250_DEV_PLATFORM
,
862 .platform_data
= dm644x_serial0_platform_data
,
866 .name
= "serial8250",
867 .id
= PLAT8250_DEV_PLATFORM1
,
869 .platform_data
= dm644x_serial1_platform_data
,
873 .name
= "serial8250",
874 .id
= PLAT8250_DEV_PLATFORM2
,
876 .platform_data
= dm644x_serial2_platform_data
,
883 static struct davinci_soc_info davinci_soc_info_dm644x
= {
884 .io_desc
= dm644x_io_desc
,
885 .io_desc_num
= ARRAY_SIZE(dm644x_io_desc
),
886 .jtag_id_reg
= 0x01c40028,
888 .ids_num
= ARRAY_SIZE(dm644x_ids
),
889 .cpu_clks
= dm644x_clks
,
890 .psc_bases
= dm644x_psc_bases
,
891 .psc_bases_num
= ARRAY_SIZE(dm644x_psc_bases
),
892 .pinmux_base
= DAVINCI_SYSTEM_MODULE_BASE
,
893 .pinmux_pins
= dm644x_pins
,
894 .pinmux_pins_num
= ARRAY_SIZE(dm644x_pins
),
895 .intc_base
= DAVINCI_ARM_INTC_BASE
,
896 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
897 .intc_irq_prios
= dm644x_default_priorities
,
898 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
899 .timer_info
= &dm644x_timer_info
,
900 .gpio_type
= GPIO_TYPE_DAVINCI
,
901 .gpio_base
= DAVINCI_GPIO_BASE
,
903 .gpio_irq
= IRQ_GPIOBNK0
,
904 .emac_pdata
= &dm644x_emac_pdata
,
905 .sram_dma
= 0x00008000,
909 void __init
dm644x_init_asp(struct snd_platform_data
*pdata
)
911 davinci_cfg_reg(DM644X_MCBSP
);
912 dm644x_asp_device
.dev
.platform_data
= pdata
;
913 platform_device_register(&dm644x_asp_device
);
916 void __init
dm644x_init(void)
918 davinci_common_init(&davinci_soc_info_dm644x
);
919 davinci_map_sysmod();
922 int __init
dm644x_init_video(struct vpfe_config
*vpfe_cfg
,
923 struct vpbe_config
*vpbe_cfg
)
925 if (vpfe_cfg
|| vpbe_cfg
)
926 platform_device_register(&dm644x_vpss_device
);
929 dm644x_vpfe_dev
.dev
.platform_data
= vpfe_cfg
;
930 platform_device_register(&dm644x_ccdc_dev
);
931 platform_device_register(&dm644x_vpfe_dev
);
935 dm644x_vpbe_dev
.dev
.platform_data
= vpbe_cfg
;
936 platform_device_register(&dm644x_osd_dev
);
937 platform_device_register(&dm644x_venc_dev
);
938 platform_device_register(&dm644x_vpbe_dev
);
939 platform_device_register(&dm644x_vpbe_display
);
945 static int __init
dm644x_init_devices(void)
947 if (!cpu_is_davinci_dm644x())
950 platform_device_register(&dm644x_edma_device
);
952 platform_device_register(&dm644x_mdio_device
);
953 platform_device_register(&dm644x_emac_device
);
957 postcore_initcall(dm644x_init_devices
);