arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/dma-mapping.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/platform_data/edma.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/cputype.h>
  21 #include <mach/irqs.h>
  22 #include <mach/psc.h>
  23 #include <mach/mux.h>
  24 #include <mach/time.h>
  25 #include <mach/serial.h>
  26 #include <mach/common.h>
  27 #include <mach/gpio-davinci.h>
  28
  29 #include "davinci.h"
  30 #include "clock.h"
  31 #include "mux.h"
  32 #include "asp.h"
  33
  34 #define DAVINCI_VPIF_BASE       (0x01C12000)
  35
  36 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  37                                         BIT_MASK(0))
  38 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  39                                         BIT_MASK(8))
  40
  41 /*
  42  * Device specific clocks
  43  */
  44 #define DM646X_REF_FREQ         27000000
  45 #define DM646X_AUX_FREQ         24000000
  46
  47 #define DM646X_EMAC_BASE                0x01c80000
  48 #define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
  49 #define DM646X_EMAC_CNTRL_OFFSET        0x0000
  50 #define DM646X_EMAC_CNTRL_MOD_OFFSET    0x1000
  51 #define DM646X_EMAC_CNTRL_RAM_OFFSET    0x2000
  52 #define DM646X_EMAC_CNTRL_RAM_SIZE      0x2000
  53
  54 static struct pll_data pll1_data = {
  55         .num       = 1,
  56         .phys_base = DAVINCI_PLL1_BASE,
  57 };
  58
  59 static struct pll_data pll2_data = {
  60         .num       = 2,
  61         .phys_base = DAVINCI_PLL2_BASE,
  62 };
  63
  64 static struct clk ref_clk = {
  65         .name = "ref_clk",
  66         .rate = DM646X_REF_FREQ,
  67         .set_rate = davinci_simple_set_rate,
  68 };
  69
  70 static struct clk aux_clkin = {
  71         .name = "aux_clkin",
  72         .rate = DM646X_AUX_FREQ,
  73 };
  74
  75 static struct clk pll1_clk = {
  76         .name = "pll1",
  77         .parent = &ref_clk,
  78         .pll_data = &pll1_data,
  79         .flags = CLK_PLL,
  80 };
  81
  82 static struct clk pll1_sysclk1 = {
  83         .name = "pll1_sysclk1",
  84         .parent = &pll1_clk,
  85         .flags = CLK_PLL,
  86         .div_reg = PLLDIV1,
  87 };
  88
  89 static struct clk pll1_sysclk2 = {
  90         .name = "pll1_sysclk2",
  91         .parent = &pll1_clk,
  92         .flags = CLK_PLL,
  93         .div_reg = PLLDIV2,
  94 };
  95
  96 static struct clk pll1_sysclk3 = {
  97         .name = "pll1_sysclk3",
  98         .parent = &pll1_clk,
  99         .flags = CLK_PLL,
 100         .div_reg = PLLDIV3,
 101 };
 102
 103 static struct clk pll1_sysclk4 = {
 104         .name = "pll1_sysclk4",
 105         .parent = &pll1_clk,
 106         .flags = CLK_PLL,
 107         .div_reg = PLLDIV4,
 108 };
 109
 110 static struct clk pll1_sysclk5 = {
 111         .name = "pll1_sysclk5",
 112         .parent = &pll1_clk,
 113         .flags = CLK_PLL,
 114         .div_reg = PLLDIV5,
 115 };
 116
 117 static struct clk pll1_sysclk6 = {
 118         .name = "pll1_sysclk6",
 119         .parent = &pll1_clk,
 120         .flags = CLK_PLL,
 121         .div_reg = PLLDIV6,
 122 };
 123
 124 static struct clk pll1_sysclk8 = {
 125         .name = "pll1_sysclk8",
 126         .parent = &pll1_clk,
 127         .flags = CLK_PLL,
 128         .div_reg = PLLDIV8,
 129 };
 130
 131 static struct clk pll1_sysclk9 = {
 132         .name = "pll1_sysclk9",
 133         .parent = &pll1_clk,
 134         .flags = CLK_PLL,
 135         .div_reg = PLLDIV9,
 136 };
 137
 138 static struct clk pll1_sysclkbp = {
 139         .name = "pll1_sysclkbp",
 140         .parent = &pll1_clk,
 141         .flags = CLK_PLL | PRE_PLL,
 142         .div_reg = BPDIV,
 143 };
 144
 145 static struct clk pll1_aux_clk = {
 146         .name = "pll1_aux_clk",
 147         .parent = &pll1_clk,
 148         .flags = CLK_PLL | PRE_PLL,
 149 };
 150
 151 static struct clk pll2_clk = {
 152         .name = "pll2_clk",
 153         .parent = &ref_clk,
 154         .pll_data = &pll2_data,
 155         .flags = CLK_PLL,
 156 };
 157
 158 static struct clk pll2_sysclk1 = {
 159         .name = "pll2_sysclk1",
 160         .parent = &pll2_clk,
 161         .flags = CLK_PLL,
 162         .div_reg = PLLDIV1,
 163 };
 164
 165 static struct clk dsp_clk = {
 166         .name = "dsp",
 167         .parent = &pll1_sysclk1,
 168         .lpsc = DM646X_LPSC_C64X_CPU,
 169         .usecount = 1,                  /* REVISIT how to disable? */
 170 };
 171
 172 static struct clk arm_clk = {
 173         .name = "arm",
 174         .parent = &pll1_sysclk2,
 175         .lpsc = DM646X_LPSC_ARM,
 176         .flags = ALWAYS_ENABLED,
 177 };
 178
 179 static struct clk edma_cc_clk = {
 180         .name = "edma_cc",
 181         .parent = &pll1_sysclk2,
 182         .lpsc = DM646X_LPSC_TPCC,
 183         .flags = ALWAYS_ENABLED,
 184 };
 185
 186 static struct clk edma_tc0_clk = {
 187         .name = "edma_tc0",
 188         .parent = &pll1_sysclk2,
 189         .lpsc = DM646X_LPSC_TPTC0,
 190         .flags = ALWAYS_ENABLED,
 191 };
 192
 193 static struct clk edma_tc1_clk = {
 194         .name = "edma_tc1",
 195         .parent = &pll1_sysclk2,
 196         .lpsc = DM646X_LPSC_TPTC1,
 197         .flags = ALWAYS_ENABLED,
 198 };
 199
 200 static struct clk edma_tc2_clk = {
 201         .name = "edma_tc2",
 202         .parent = &pll1_sysclk2,
 203         .lpsc = DM646X_LPSC_TPTC2,
 204         .flags = ALWAYS_ENABLED,
 205 };
 206
 207 static struct clk edma_tc3_clk = {
 208         .name = "edma_tc3",
 209         .parent = &pll1_sysclk2,
 210         .lpsc = DM646X_LPSC_TPTC3,
 211         .flags = ALWAYS_ENABLED,
 212 };
 213
 214 static struct clk uart0_clk = {
 215         .name = "uart0",
 216         .parent = &aux_clkin,
 217         .lpsc = DM646X_LPSC_UART0,
 218 };
 219
 220 static struct clk uart1_clk = {
 221         .name = "uart1",
 222         .parent = &aux_clkin,
 223         .lpsc = DM646X_LPSC_UART1,
 224 };
 225
 226 static struct clk uart2_clk = {
 227         .name = "uart2",
 228         .parent = &aux_clkin,
 229         .lpsc = DM646X_LPSC_UART2,
 230 };
 231
 232 static struct clk i2c_clk = {
 233         .name = "I2CCLK",
 234         .parent = &pll1_sysclk3,
 235         .lpsc = DM646X_LPSC_I2C,
 236 };
 237
 238 static struct clk gpio_clk = {
 239         .name = "gpio",
 240         .parent = &pll1_sysclk3,
 241         .lpsc = DM646X_LPSC_GPIO,
 242 };
 243
 244 static struct clk mcasp0_clk = {
 245         .name = "mcasp0",
 246         .parent = &pll1_sysclk3,
 247         .lpsc = DM646X_LPSC_McASP0,
 248 };
 249
 250 static struct clk mcasp1_clk = {
 251         .name = "mcasp1",
 252         .parent = &pll1_sysclk3,
 253         .lpsc = DM646X_LPSC_McASP1,
 254 };
 255
 256 static struct clk aemif_clk = {
 257         .name = "aemif",
 258         .parent = &pll1_sysclk3,
 259         .lpsc = DM646X_LPSC_AEMIF,
 260         .flags = ALWAYS_ENABLED,
 261 };
 262
 263 static struct clk emac_clk = {
 264         .name = "emac",
 265         .parent = &pll1_sysclk3,
 266         .lpsc = DM646X_LPSC_EMAC,
 267 };
 268
 269 static struct clk pwm0_clk = {
 270         .name = "pwm0",
 271         .parent = &pll1_sysclk3,
 272         .lpsc = DM646X_LPSC_PWM0,
 273         .usecount = 1,            /* REVIST: disabling hangs system */
 274 };
 275
 276 static struct clk pwm1_clk = {
 277         .name = "pwm1",
 278         .parent = &pll1_sysclk3,
 279         .lpsc = DM646X_LPSC_PWM1,
 280         .usecount = 1,            /* REVIST: disabling hangs system */
 281 };
 282
 283 static struct clk timer0_clk = {
 284         .name = "timer0",
 285         .parent = &pll1_sysclk3,
 286         .lpsc = DM646X_LPSC_TIMER0,
 287 };
 288
 289 static struct clk timer1_clk = {
 290         .name = "timer1",
 291         .parent = &pll1_sysclk3,
 292         .lpsc = DM646X_LPSC_TIMER1,
 293 };
 294
 295 static struct clk timer2_clk = {
 296         .name = "timer2",
 297         .parent = &pll1_sysclk3,
 298         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 299 };
 300
 301
 302 static struct clk ide_clk = {
 303         .name = "ide",
 304         .parent = &pll1_sysclk4,
 305         .lpsc = DAVINCI_LPSC_ATA,
 306 };
 307
 308 static struct clk vpif0_clk = {
 309         .name = "vpif0",
 310         .parent = &ref_clk,
 311         .lpsc = DM646X_LPSC_VPSSMSTR,
 312         .flags = ALWAYS_ENABLED,
 313 };
 314
 315 static struct clk vpif1_clk = {
 316         .name = "vpif1",
 317         .parent = &ref_clk,
 318         .lpsc = DM646X_LPSC_VPSSSLV,
 319         .flags = ALWAYS_ENABLED,
 320 };
 321
 322 static struct clk_lookup dm646x_clks[] = {
 323         CLK(NULL, "ref", &ref_clk),
 324         CLK(NULL, "aux", &aux_clkin),
 325         CLK(NULL, "pll1", &pll1_clk),
 326         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 327         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 328         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 329         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 330         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 331         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 332         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 333         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 334         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 335         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 336         CLK(NULL, "pll2", &pll2_clk),
 337         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 338         CLK(NULL, "dsp", &dsp_clk),
 339         CLK(NULL, "arm", &arm_clk),
 340         CLK(NULL, "edma_cc", &edma_cc_clk),
 341         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 342         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 343         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 344         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 345         CLK("serial8250.0", NULL, &uart0_clk),
 346         CLK("serial8250.1", NULL, &uart1_clk),
 347         CLK("serial8250.2", NULL, &uart2_clk),
 348         CLK("i2c_davinci.1", NULL, &i2c_clk),
 349         CLK(NULL, "gpio", &gpio_clk),
 350         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
 351         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 352         CLK(NULL, "aemif", &aemif_clk),
 353         CLK("davinci_emac.1", NULL, &emac_clk),
 354         CLK("davinci_mdio.0", "fck", &emac_clk),
 355         CLK(NULL, "pwm0", &pwm0_clk),
 356         CLK(NULL, "pwm1", &pwm1_clk),
 357         CLK(NULL, "timer0", &timer0_clk),
 358         CLK(NULL, "timer1", &timer1_clk),
 359         CLK("watchdog", NULL, &timer2_clk),
 360         CLK("palm_bk3710", NULL, &ide_clk),
 361         CLK(NULL, "vpif0", &vpif0_clk),
 362         CLK(NULL, "vpif1", &vpif1_clk),
 363         CLK(NULL, NULL, NULL),
 364 };
 365
 366 static struct emac_platform_data dm646x_emac_pdata = {
 367         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 368         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 369         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 370         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 371         .version                = EMAC_VERSION_2,
 372 };
 373
 374 static struct resource dm646x_emac_resources[] = {
 375         {
 376                 .start  = DM646X_EMAC_BASE,
 377                 .end    = DM646X_EMAC_BASE + SZ_16K - 1,
 378                 .flags  = IORESOURCE_MEM,
 379         },
 380         {
 381                 .start  = IRQ_DM646X_EMACRXTHINT,
 382                 .end    = IRQ_DM646X_EMACRXTHINT,
 383                 .flags  = IORESOURCE_IRQ,
 384         },
 385         {
 386                 .start  = IRQ_DM646X_EMACRXINT,
 387                 .end    = IRQ_DM646X_EMACRXINT,
 388                 .flags  = IORESOURCE_IRQ,
 389         },
 390         {
 391                 .start  = IRQ_DM646X_EMACTXINT,
 392                 .end    = IRQ_DM646X_EMACTXINT,
 393                 .flags  = IORESOURCE_IRQ,
 394         },
 395         {
 396                 .start  = IRQ_DM646X_EMACMISCINT,
 397                 .end    = IRQ_DM646X_EMACMISCINT,
 398                 .flags  = IORESOURCE_IRQ,
 399         },
 400 };
 401
 402 static struct platform_device dm646x_emac_device = {
 403         .name           = "davinci_emac",
 404         .id             = 1,
 405         .dev = {
 406                 .platform_data  = &dm646x_emac_pdata,
 407         },
 408         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 409         .resource       = dm646x_emac_resources,
 410 };
 411
 412 static struct resource dm646x_mdio_resources[] = {
 413         {
 414                 .start  = DM646X_EMAC_MDIO_BASE,
 415                 .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
 416                 .flags  = IORESOURCE_MEM,
 417         },
 418 };
 419
 420 static struct platform_device dm646x_mdio_device = {
 421         .name           = "davinci_mdio",
 422         .id             = 0,
 423         .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
 424         .resource       = dm646x_mdio_resources,
 425 };
 426
 427 /*
 428  * Device specific mux setup
 429  *
 430  *      soc     description     mux  mode   mode  mux    dbg
 431  *                              reg  offset mask  mode
 432  */
 433 static const struct mux_config dm646x_pins[] = {
 434 #ifdef CONFIG_DAVINCI_MUX
 435 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 436
 437 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 438
 439 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 440
 441 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 442
 443 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 444
 445 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 446
 447 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 448
 449 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 450
 451 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 452
 453 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 454
 455 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 456
 457 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 458
 459 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 460
 461 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 462 #endif
 463 };
 464
 465 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 466         [IRQ_DM646X_VP_VERTINT0]        = 7,
 467         [IRQ_DM646X_VP_VERTINT1]        = 7,
 468         [IRQ_DM646X_VP_VERTINT2]        = 7,
 469         [IRQ_DM646X_VP_VERTINT3]        = 7,
 470         [IRQ_DM646X_VP_ERRINT]          = 7,
 471         [IRQ_DM646X_RESERVED_1]         = 7,
 472         [IRQ_DM646X_RESERVED_2]         = 7,
 473         [IRQ_DM646X_WDINT]              = 7,
 474         [IRQ_DM646X_CRGENINT0]          = 7,
 475         [IRQ_DM646X_CRGENINT1]          = 7,
 476         [IRQ_DM646X_TSIFINT0]           = 7,
 477         [IRQ_DM646X_TSIFINT1]           = 7,
 478         [IRQ_DM646X_VDCEINT]            = 7,
 479         [IRQ_DM646X_USBINT]             = 7,
 480         [IRQ_DM646X_USBDMAINT]          = 7,
 481         [IRQ_DM646X_PCIINT]             = 7,
 482         [IRQ_CCINT0]                    = 7,    /* dma */
 483         [IRQ_CCERRINT]                  = 7,    /* dma */
 484         [IRQ_TCERRINT0]                 = 7,    /* dma */
 485         [IRQ_TCERRINT]                  = 7,    /* dma */
 486         [IRQ_DM646X_TCERRINT2]          = 7,
 487         [IRQ_DM646X_TCERRINT3]          = 7,
 488         [IRQ_DM646X_IDE]                = 7,
 489         [IRQ_DM646X_HPIINT]             = 7,
 490         [IRQ_DM646X_EMACRXTHINT]        = 7,
 491         [IRQ_DM646X_EMACRXINT]          = 7,
 492         [IRQ_DM646X_EMACTXINT]          = 7,
 493         [IRQ_DM646X_EMACMISCINT]        = 7,
 494         [IRQ_DM646X_MCASP0TXINT]        = 7,
 495         [IRQ_DM646X_MCASP0RXINT]        = 7,
 496         [IRQ_AEMIFINT]                  = 7,
 497         [IRQ_DM646X_RESERVED_3]         = 7,
 498         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 499         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 500         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 501         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 502         [IRQ_PWMINT0]                   = 7,
 503         [IRQ_PWMINT1]                   = 7,
 504         [IRQ_DM646X_VLQINT]             = 7,
 505         [IRQ_I2C]                       = 7,
 506         [IRQ_UARTINT0]                  = 7,
 507         [IRQ_UARTINT1]                  = 7,
 508         [IRQ_DM646X_UARTINT2]           = 7,
 509         [IRQ_DM646X_SPINT0]             = 7,
 510         [IRQ_DM646X_SPINT1]             = 7,
 511         [IRQ_DM646X_DSP2ARMINT]         = 7,
 512         [IRQ_DM646X_RESERVED_4]         = 7,
 513         [IRQ_DM646X_PSCINT]             = 7,
 514         [IRQ_DM646X_GPIO0]              = 7,
 515         [IRQ_DM646X_GPIO1]              = 7,
 516         [IRQ_DM646X_GPIO2]              = 7,
 517         [IRQ_DM646X_GPIO3]              = 7,
 518         [IRQ_DM646X_GPIO4]              = 7,
 519         [IRQ_DM646X_GPIO5]              = 7,
 520         [IRQ_DM646X_GPIO6]              = 7,
 521         [IRQ_DM646X_GPIO7]              = 7,
 522         [IRQ_DM646X_GPIOBNK0]           = 7,
 523         [IRQ_DM646X_GPIOBNK1]           = 7,
 524         [IRQ_DM646X_GPIOBNK2]           = 7,
 525         [IRQ_DM646X_DDRINT]             = 7,
 526         [IRQ_DM646X_AEMIFINT]           = 7,
 527         [IRQ_COMMTX]                    = 7,
 528         [IRQ_COMMRX]                    = 7,
 529         [IRQ_EMUINT]                    = 7,
 530 };
 531
 532 /*----------------------------------------------------------------------*/
 533
 534 /* Four Transfer Controllers on DM646x */
 535 static s8
 536 dm646x_queue_tc_mapping[][2] = {
 537         /* {event queue no, TC no} */
 538         {0, 0},
 539         {1, 1},
 540         {2, 2},
 541         {3, 3},
 542         {-1, -1},
 543 };
 544
 545 static s8
 546 dm646x_queue_priority_mapping[][2] = {
 547         /* {event queue no, Priority} */
 548         {0, 4},
 549         {1, 0},
 550         {2, 5},
 551         {3, 1},
 552         {-1, -1},
 553 };
 554
 555 static struct edma_soc_info edma_cc0_info = {
 556         .n_channel              = 64,
 557         .n_region               = 6,    /* 0-1, 4-7 */
 558         .n_slot                 = 512,
 559         .n_tc                   = 4,
 560         .n_cc                   = 1,
 561         .queue_tc_mapping       = dm646x_queue_tc_mapping,
 562         .queue_priority_mapping = dm646x_queue_priority_mapping,
 563         .default_queue          = EVENTQ_1,
 564 };
 565
 566 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
 567         &edma_cc0_info,
 568 };
 569
 570 static struct resource edma_resources[] = {
 571         {
 572                 .name   = "edma_cc0",
 573                 .start  = 0x01c00000,
 574                 .end    = 0x01c00000 + SZ_64K - 1,
 575                 .flags  = IORESOURCE_MEM,
 576         },
 577         {
 578                 .name   = "edma_tc0",
 579                 .start  = 0x01c10000,
 580                 .end    = 0x01c10000 + SZ_1K - 1,
 581                 .flags  = IORESOURCE_MEM,
 582         },
 583         {
 584                 .name   = "edma_tc1",
 585                 .start  = 0x01c10400,
 586                 .end    = 0x01c10400 + SZ_1K - 1,
 587                 .flags  = IORESOURCE_MEM,
 588         },
 589         {
 590                 .name   = "edma_tc2",
 591                 .start  = 0x01c10800,
 592                 .end    = 0x01c10800 + SZ_1K - 1,
 593                 .flags  = IORESOURCE_MEM,
 594         },
 595         {
 596                 .name   = "edma_tc3",
 597                 .start  = 0x01c10c00,
 598                 .end    = 0x01c10c00 + SZ_1K - 1,
 599                 .flags  = IORESOURCE_MEM,
 600         },
 601         {
 602                 .name   = "edma0",
 603                 .start  = IRQ_CCINT0,
 604                 .flags  = IORESOURCE_IRQ,
 605         },
 606         {
 607                 .name   = "edma0_err",
 608                 .start  = IRQ_CCERRINT,
 609                 .flags  = IORESOURCE_IRQ,
 610         },
 611         /* not using TC*_ERR */
 612 };
 613
 614 static struct platform_device dm646x_edma_device = {
 615         .name                   = "edma",
 616         .id                     = 0,
 617         .dev.platform_data      = dm646x_edma_info,
 618         .num_resources          = ARRAY_SIZE(edma_resources),
 619         .resource               = edma_resources,
 620 };
 621
 622 static struct resource dm646x_mcasp0_resources[] = {
 623         {
 624                 .name   = "mcasp0",
 625                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 626                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629         /* first TX, then RX */
 630         {
 631                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 632                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 633                 .flags  = IORESOURCE_DMA,
 634         },
 635         {
 636                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 637                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 638                 .flags  = IORESOURCE_DMA,
 639         },
 640 };
 641
 642 static struct resource dm646x_mcasp1_resources[] = {
 643         {
 644                 .name   = "mcasp1",
 645                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 646                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 647                 .flags  = IORESOURCE_MEM,
 648         },
 649         /* DIT mode, only TX event */
 650         {
 651                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 652                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 653                 .flags  = IORESOURCE_DMA,
 654         },
 655         /* DIT mode, dummy entry */
 656         {
 657                 .start  = -1,
 658                 .end    = -1,
 659                 .flags  = IORESOURCE_DMA,
 660         },
 661 };
 662
 663 static struct platform_device dm646x_mcasp0_device = {
 664         .name           = "davinci-mcasp",
 665         .id             = 0,
 666         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 667         .resource       = dm646x_mcasp0_resources,
 668 };
 669
 670 static struct platform_device dm646x_mcasp1_device = {
 671         .name           = "davinci-mcasp",
 672         .id             = 1,
 673         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 674         .resource       = dm646x_mcasp1_resources,
 675 };
 676
 677 static struct platform_device dm646x_dit_device = {
 678         .name   = "spdif-dit",
 679         .id     = -1,
 680 };
 681
 682 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 683
 684 static struct resource vpif_resource[] = {
 685         {
 686                 .start  = DAVINCI_VPIF_BASE,
 687                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 688                 .flags  = IORESOURCE_MEM,
 689         }
 690 };
 691
 692 static struct platform_device vpif_dev = {
 693         .name           = "vpif",
 694         .id             = -1,
 695         .dev            = {
 696                         .dma_mask               = &vpif_dma_mask,
 697                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 698         },
 699         .resource       = vpif_resource,
 700         .num_resources  = ARRAY_SIZE(vpif_resource),
 701 };
 702
 703 static struct resource vpif_display_resource[] = {
 704         {
 705                 .start = IRQ_DM646X_VP_VERTINT2,
 706                 .end   = IRQ_DM646X_VP_VERTINT2,
 707                 .flags = IORESOURCE_IRQ,
 708         },
 709         {
 710                 .start = IRQ_DM646X_VP_VERTINT3,
 711                 .end   = IRQ_DM646X_VP_VERTINT3,
 712                 .flags = IORESOURCE_IRQ,
 713         },
 714 };
 715
 716 static struct platform_device vpif_display_dev = {
 717         .name           = "vpif_display",
 718         .id             = -1,
 719         .dev            = {
 720                         .dma_mask               = &vpif_dma_mask,
 721                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 722         },
 723         .resource       = vpif_display_resource,
 724         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 725 };
 726
 727 static struct resource vpif_capture_resource[] = {
 728         {
 729                 .start = IRQ_DM646X_VP_VERTINT0,
 730                 .end   = IRQ_DM646X_VP_VERTINT0,
 731                 .flags = IORESOURCE_IRQ,
 732         },
 733         {
 734                 .start = IRQ_DM646X_VP_VERTINT1,
 735                 .end   = IRQ_DM646X_VP_VERTINT1,
 736                 .flags = IORESOURCE_IRQ,
 737         },
 738 };
 739
 740 static struct platform_device vpif_capture_dev = {
 741         .name           = "vpif_capture",
 742         .id             = -1,
 743         .dev            = {
 744                         .dma_mask               = &vpif_dma_mask,
 745                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 746         },
 747         .resource       = vpif_capture_resource,
 748         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 749 };
 750
 751 /*----------------------------------------------------------------------*/
 752
 753 static struct map_desc dm646x_io_desc[] = {
 754         {
 755                 .virtual        = IO_VIRT,
 756                 .pfn            = __phys_to_pfn(IO_PHYS),
 757                 .length         = IO_SIZE,
 758                 .type           = MT_DEVICE
 759         },
 760 };
 761
 762 /* Contents of JTAG ID register used to identify exact cpu type */
 763 static struct davinci_id dm646x_ids[] = {
 764         {
 765                 .variant        = 0x0,
 766                 .part_no        = 0xb770,
 767                 .manufacturer   = 0x017,
 768                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 769                 .name           = "dm6467_rev1.x",
 770         },
 771         {
 772                 .variant        = 0x1,
 773                 .part_no        = 0xb770,
 774                 .manufacturer   = 0x017,
 775                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 776                 .name           = "dm6467_rev3.x",
 777         },
 778 };
 779
 780 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 781
 782 /*
 783  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 784  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 785  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 786  * T1_TOP: Timer 1, top   :  <unused>
 787  */
 788 static struct davinci_timer_info dm646x_timer_info = {
 789         .timers         = davinci_timer_instance,
 790         .clockevent_id  = T0_BOT,
 791         .clocksource_id = T0_TOP,
 792 };
 793
 794 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
 795         {
 796                 .mapbase        = DAVINCI_UART0_BASE,
 797                 .irq            = IRQ_UARTINT0,
 798                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 799                                   UPF_IOREMAP,
 800                 .iotype         = UPIO_MEM32,
 801                 .regshift       = 2,
 802         },
 803         {
 804                 .flags  = 0,
 805         }
 806 };
 807 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
 808         {
 809                 .mapbase        = DAVINCI_UART1_BASE,
 810                 .irq            = IRQ_UARTINT1,
 811                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 812                                   UPF_IOREMAP,
 813                 .iotype         = UPIO_MEM32,
 814                 .regshift       = 2,
 815         },
 816         {
 817                 .flags  = 0,
 818         }
 819 };
 820 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
 821         {
 822                 .mapbase        = DAVINCI_UART2_BASE,
 823                 .irq            = IRQ_DM646X_UARTINT2,
 824                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 825                                   UPF_IOREMAP,
 826                 .iotype         = UPIO_MEM32,
 827                 .regshift       = 2,
 828         },
 829         {
 830                 .flags  = 0,
 831         }
 832 };
 833
 834 struct platform_device dm646x_serial_device[] = {
 835         {
 836                 .name                   = "serial8250",
 837                 .id                     = PLAT8250_DEV_PLATFORM,
 838                 .dev                    = {
 839                         .platform_data  = dm646x_serial0_platform_data,
 840                 }
 841         },
 842         {
 843                 .name                   = "serial8250",
 844                 .id                     = PLAT8250_DEV_PLATFORM1,
 845                 .dev                    = {
 846                         .platform_data  = dm646x_serial1_platform_data,
 847                 }
 848         },
 849         {
 850                 .name                   = "serial8250",
 851                 .id                     = PLAT8250_DEV_PLATFORM2,
 852                 .dev                    = {
 853                         .platform_data  = dm646x_serial2_platform_data,
 854                 }
 855         },
 856         {
 857         }
 858 };
 859
 860 static struct davinci_soc_info davinci_soc_info_dm646x = {
 861         .io_desc                = dm646x_io_desc,
 862         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 863         .jtag_id_reg            = 0x01c40028,
 864         .ids                    = dm646x_ids,
 865         .ids_num                = ARRAY_SIZE(dm646x_ids),
 866         .cpu_clks               = dm646x_clks,
 867         .psc_bases              = dm646x_psc_bases,
 868         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 869         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 870         .pinmux_pins            = dm646x_pins,
 871         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 872         .intc_base              = DAVINCI_ARM_INTC_BASE,
 873         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 874         .intc_irq_prios         = dm646x_default_priorities,
 875         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 876         .timer_info             = &dm646x_timer_info,
 877         .gpio_type              = GPIO_TYPE_DAVINCI,
 878         .gpio_base              = DAVINCI_GPIO_BASE,
 879         .gpio_num               = 43, /* Only 33 usable */
 880         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 881         .emac_pdata             = &dm646x_emac_pdata,
 882         .sram_dma               = 0x10010000,
 883         .sram_len               = SZ_32K,
 884 };
 885
 886 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 887 {
 888         dm646x_mcasp0_device.dev.platform_data = pdata;
 889         platform_device_register(&dm646x_mcasp0_device);
 890 }
 891
 892 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 893 {
 894         dm646x_mcasp1_device.dev.platform_data = pdata;
 895         platform_device_register(&dm646x_mcasp1_device);
 896         platform_device_register(&dm646x_dit_device);
 897 }
 898
 899 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 900                        struct vpif_capture_config *capture_config)
 901 {
 902         unsigned int value;
 903
 904         value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 905         value &= ~VSCLKDIS_MASK;
 906         __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 907
 908         value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 909         value &= ~VDD3P3V_VID_MASK;
 910         __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 911
 912         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 913         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 914         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 915         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 916
 917         vpif_display_dev.dev.platform_data = display_config;
 918         vpif_capture_dev.dev.platform_data = capture_config;
 919         platform_device_register(&vpif_dev);
 920         platform_device_register(&vpif_display_dev);
 921         platform_device_register(&vpif_capture_dev);
 922 }
 923
 924 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 925 {
 926         edma_cc0_info.rsv = rsv;
 927
 928         return platform_device_register(&dm646x_edma_device);
 929 }
 930
 931 void __init dm646x_init(void)
 932 {
 933         davinci_common_init(&davinci_soc_info_dm646x);
 934         davinci_map_sysmod();
 935 }
 936
 937 static int __init dm646x_init_devices(void)
 938 {
 939         if (!cpu_is_davinci_dm646x())
 940                 return 0;
 941
 942         platform_device_register(&dm646x_mdio_device);
 943         platform_device_register(&dm646x_emac_device);
 944
 945         return 0;
 946 }
 947 postcore_initcall(dm646x_init_devices);