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x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_54xx_data.c
blob6bbb1e679e3024b475f3d700a37e6b0d7c5e0019
1 /*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
24
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
32 #include "cm1_54xx.h"
33 #include "cm2_54xx.h"
34 #include "prm54xx.h"
35 #include "i2c.h"
36 #include "mmc.h"
37 #include "wd_timer.h"
38
39 /* Base offset for all OMAP5 interrupts external to MPUSS */
40 #define OMAP54XX_IRQ_GIC_START 32
41
42 /* Base offset for all OMAP5 dma requests */
43 #define OMAP54XX_DMA_REQ_START 1
44
45
46 /*
47 * IP blocks
48 */
49
50 /*
51 * 'dmm' class
52 * instance(s): dmm
53 */
54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
55 .name = "dmm",
56 };
57
58 /* dmm */
59 static struct omap_hwmod omap54xx_dmm_hwmod = {
60 .name = "dmm",
61 .class = &omap54xx_dmm_hwmod_class,
62 .clkdm_name = "emif_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
66 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
67 },
68 },
69 };
70
71 /*
72 * 'l3' class
73 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
74 */
75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
76 .name = "l3",
77 };
78
79 /* l3_instr */
80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
81 .name = "l3_instr",
82 .class = &omap54xx_l3_hwmod_class,
83 .clkdm_name = "l3instr_clkdm",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
87 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
88 .modulemode = MODULEMODE_HWCTRL,
89 },
90 },
91 };
92
93 /* l3_main_1 */
94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
95 .name = "l3_main_1",
96 .class = &omap54xx_l3_hwmod_class,
97 .clkdm_name = "l3main1_clkdm",
98 .prcm = {
99 .omap4 = {
100 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
101 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
102 },
103 },
104 };
105
106 /* l3_main_2 */
107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
108 .name = "l3_main_2",
109 .class = &omap54xx_l3_hwmod_class,
110 .clkdm_name = "l3main2_clkdm",
111 .prcm = {
112 .omap4 = {
113 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
114 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
115 },
116 },
117 };
118
119 /* l3_main_3 */
120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
121 .name = "l3_main_3",
122 .class = &omap54xx_l3_hwmod_class,
123 .clkdm_name = "l3instr_clkdm",
124 .prcm = {
125 .omap4 = {
126 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
127 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
128 .modulemode = MODULEMODE_HWCTRL,
129 },
130 },
131 };
132
133 /*
134 * 'l4' class
135 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
136 */
137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
138 .name = "l4",
139 };
140
141 /* l4_abe */
142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
143 .name = "l4_abe",
144 .class = &omap54xx_l4_hwmod_class,
145 .clkdm_name = "abe_clkdm",
146 .prcm = {
147 .omap4 = {
148 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
149 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
150 },
151 },
152 };
153
154 /* l4_cfg */
155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
156 .name = "l4_cfg",
157 .class = &omap54xx_l4_hwmod_class,
158 .clkdm_name = "l4cfg_clkdm",
159 .prcm = {
160 .omap4 = {
161 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
162 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
163 },
164 },
165 };
166
167 /* l4_per */
168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
169 .name = "l4_per",
170 .class = &omap54xx_l4_hwmod_class,
171 .clkdm_name = "l4per_clkdm",
172 .prcm = {
173 .omap4 = {
174 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
175 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
176 },
177 },
178 };
179
180 /* l4_wkup */
181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
182 .name = "l4_wkup",
183 .class = &omap54xx_l4_hwmod_class,
184 .clkdm_name = "wkupaon_clkdm",
185 .prcm = {
186 .omap4 = {
187 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
188 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
189 },
190 },
191 };
192
193 /*
194 * 'mpu_bus' class
195 * instance(s): mpu_private
196 */
197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
198 .name = "mpu_bus",
199 };
200
201 /* mpu_private */
202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
203 .name = "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class,
205 .clkdm_name = "mpu_clkdm",
206 .prcm = {
207 .omap4 = {
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
209 },
210 },
211 };
212
213 /*
214 * 'counter' class
215 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
216 */
217
218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
219 .rev_offs = 0x0000,
220 .sysc_offs = 0x0010,
221 .sysc_flags = SYSC_HAS_SIDLEMODE,
222 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
223 .sysc_fields = &omap_hwmod_sysc_type1,
224 };
225
226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
227 .name = "counter",
228 .sysc = &omap54xx_counter_sysc,
229 };
230
231 /* counter_32k */
232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
233 .name = "counter_32k",
234 .class = &omap54xx_counter_hwmod_class,
235 .clkdm_name = "wkupaon_clkdm",
236 .flags = HWMOD_SWSUP_SIDLE,
237 .main_clk = "wkupaon_iclk_mux",
238 .prcm = {
239 .omap4 = {
240 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
241 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
242 },
243 },
244 };
245
246 /*
247 * 'dma' class
248 * dma controller for data exchange between memory to memory (i.e. internal or
249 * external memory) and gp peripherals to memory or memory to gp peripherals
250 */
251
252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
253 .rev_offs = 0x0000,
254 .sysc_offs = 0x002c,
255 .syss_offs = 0x0028,
256 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
257 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
258 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
259 SYSS_HAS_RESET_STATUS),
260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
261 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
262 .sysc_fields = &omap_hwmod_sysc_type1,
263 };
264
265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
266 .name = "dma",
267 .sysc = &omap54xx_dma_sysc,
268 };
269
270 /* dma dev_attr */
271 static struct omap_dma_dev_attr dma_dev_attr = {
272 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
273 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
274 .lch_count = 32,
275 };
276
277 /* dma_system */
278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
279 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
280 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
281 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
282 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
283 { .irq = -1 }
284 };
285
286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
287 .name = "dma_system",
288 .class = &omap54xx_dma_hwmod_class,
289 .clkdm_name = "dma_clkdm",
290 .mpu_irqs = omap54xx_dma_system_irqs,
291 .main_clk = "l3_iclk_div",
292 .prcm = {
293 .omap4 = {
294 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
295 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
296 },
297 },
298 .dev_attr = &dma_dev_attr,
299 };
300
301 /*
302 * 'dmic' class
303 * digital microphone controller
304 */
305
306 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
307 .rev_offs = 0x0000,
308 .sysc_offs = 0x0010,
309 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
312 SIDLE_SMART_WKUP),
313 .sysc_fields = &omap_hwmod_sysc_type2,
314 };
315
316 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
317 .name = "dmic",
318 .sysc = &omap54xx_dmic_sysc,
319 };
320
321 /* dmic */
322 static struct omap_hwmod omap54xx_dmic_hwmod = {
323 .name = "dmic",
324 .class = &omap54xx_dmic_hwmod_class,
325 .clkdm_name = "abe_clkdm",
326 .main_clk = "dmic_gfclk",
327 .prcm = {
328 .omap4 = {
329 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
330 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
332 },
333 },
334 };
335
336 /*
337 * 'emif' class
338 * external memory interface no1 (wrapper)
339 */
340
341 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
342 .rev_offs = 0x0000,
343 };
344
345 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
346 .name = "emif",
347 .sysc = &omap54xx_emif_sysc,
348 };
349
350 /* emif1 */
351 static struct omap_hwmod omap54xx_emif1_hwmod = {
352 .name = "emif1",
353 .class = &omap54xx_emif_hwmod_class,
354 .clkdm_name = "emif_clkdm",
355 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
356 .main_clk = "dpll_core_h11x2_ck",
357 .prcm = {
358 .omap4 = {
359 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
360 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
362 },
363 },
364 };
365
366 /* emif2 */
367 static struct omap_hwmod omap54xx_emif2_hwmod = {
368 .name = "emif2",
369 .class = &omap54xx_emif_hwmod_class,
370 .clkdm_name = "emif_clkdm",
371 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
372 .main_clk = "dpll_core_h11x2_ck",
373 .prcm = {
374 .omap4 = {
375 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
376 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
377 .modulemode = MODULEMODE_HWCTRL,
378 },
379 },
380 };
381
382 /*
383 * 'gpio' class
384 * general purpose io module
385 */
386
387 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
388 .rev_offs = 0x0000,
389 .sysc_offs = 0x0010,
390 .syss_offs = 0x0114,
391 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
392 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
393 SYSS_HAS_RESET_STATUS),
394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
395 SIDLE_SMART_WKUP),
396 .sysc_fields = &omap_hwmod_sysc_type1,
397 };
398
399 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
400 .name = "gpio",
401 .sysc = &omap54xx_gpio_sysc,
402 .rev = 2,
403 };
404
405 /* gpio dev_attr */
406 static struct omap_gpio_dev_attr gpio_dev_attr = {
407 .bank_width = 32,
408 .dbck_flag = true,
409 };
410
411 /* gpio1 */
412 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
413 { .role = "dbclk", .clk = "gpio1_dbclk" },
414 };
415
416 static struct omap_hwmod omap54xx_gpio1_hwmod = {
417 .name = "gpio1",
418 .class = &omap54xx_gpio_hwmod_class,
419 .clkdm_name = "wkupaon_clkdm",
420 .main_clk = "wkupaon_iclk_mux",
421 .prcm = {
422 .omap4 = {
423 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
424 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
425 .modulemode = MODULEMODE_HWCTRL,
426 },
427 },
428 .opt_clks = gpio1_opt_clks,
429 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
430 .dev_attr = &gpio_dev_attr,
431 };
432
433 /* gpio2 */
434 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
435 { .role = "dbclk", .clk = "gpio2_dbclk" },
436 };
437
438 static struct omap_hwmod omap54xx_gpio2_hwmod = {
439 .name = "gpio2",
440 .class = &omap54xx_gpio_hwmod_class,
441 .clkdm_name = "l4per_clkdm",
442 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
443 .main_clk = "l4_root_clk_div",
444 .prcm = {
445 .omap4 = {
446 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
447 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
448 .modulemode = MODULEMODE_HWCTRL,
449 },
450 },
451 .opt_clks = gpio2_opt_clks,
452 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
453 .dev_attr = &gpio_dev_attr,
454 };
455
456 /* gpio3 */
457 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
458 { .role = "dbclk", .clk = "gpio3_dbclk" },
459 };
460
461 static struct omap_hwmod omap54xx_gpio3_hwmod = {
462 .name = "gpio3",
463 .class = &omap54xx_gpio_hwmod_class,
464 .clkdm_name = "l4per_clkdm",
465 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
466 .main_clk = "l4_root_clk_div",
467 .prcm = {
468 .omap4 = {
469 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
470 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
471 .modulemode = MODULEMODE_HWCTRL,
472 },
473 },
474 .opt_clks = gpio3_opt_clks,
475 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
476 .dev_attr = &gpio_dev_attr,
477 };
478
479 /* gpio4 */
480 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
481 { .role = "dbclk", .clk = "gpio4_dbclk" },
482 };
483
484 static struct omap_hwmod omap54xx_gpio4_hwmod = {
485 .name = "gpio4",
486 .class = &omap54xx_gpio_hwmod_class,
487 .clkdm_name = "l4per_clkdm",
488 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
489 .main_clk = "l4_root_clk_div",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
493 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
494 .modulemode = MODULEMODE_HWCTRL,
495 },
496 },
497 .opt_clks = gpio4_opt_clks,
498 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
499 .dev_attr = &gpio_dev_attr,
500 };
501
502 /* gpio5 */
503 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
504 { .role = "dbclk", .clk = "gpio5_dbclk" },
505 };
506
507 static struct omap_hwmod omap54xx_gpio5_hwmod = {
508 .name = "gpio5",
509 .class = &omap54xx_gpio_hwmod_class,
510 .clkdm_name = "l4per_clkdm",
511 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 .main_clk = "l4_root_clk_div",
513 .prcm = {
514 .omap4 = {
515 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
516 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
517 .modulemode = MODULEMODE_HWCTRL,
518 },
519 },
520 .opt_clks = gpio5_opt_clks,
521 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
522 .dev_attr = &gpio_dev_attr,
523 };
524
525 /* gpio6 */
526 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
527 { .role = "dbclk", .clk = "gpio6_dbclk" },
528 };
529
530 static struct omap_hwmod omap54xx_gpio6_hwmod = {
531 .name = "gpio6",
532 .class = &omap54xx_gpio_hwmod_class,
533 .clkdm_name = "l4per_clkdm",
534 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
535 .main_clk = "l4_root_clk_div",
536 .prcm = {
537 .omap4 = {
538 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
539 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
540 .modulemode = MODULEMODE_HWCTRL,
541 },
542 },
543 .opt_clks = gpio6_opt_clks,
544 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
545 .dev_attr = &gpio_dev_attr,
546 };
547
548 /* gpio7 */
549 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
550 { .role = "dbclk", .clk = "gpio7_dbclk" },
551 };
552
553 static struct omap_hwmod omap54xx_gpio7_hwmod = {
554 .name = "gpio7",
555 .class = &omap54xx_gpio_hwmod_class,
556 .clkdm_name = "l4per_clkdm",
557 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
558 .main_clk = "l4_root_clk_div",
559 .prcm = {
560 .omap4 = {
561 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
562 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
563 .modulemode = MODULEMODE_HWCTRL,
564 },
565 },
566 .opt_clks = gpio7_opt_clks,
567 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
568 .dev_attr = &gpio_dev_attr,
569 };
570
571 /* gpio8 */
572 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
573 { .role = "dbclk", .clk = "gpio8_dbclk" },
574 };
575
576 static struct omap_hwmod omap54xx_gpio8_hwmod = {
577 .name = "gpio8",
578 .class = &omap54xx_gpio_hwmod_class,
579 .clkdm_name = "l4per_clkdm",
580 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
581 .main_clk = "l4_root_clk_div",
582 .prcm = {
583 .omap4 = {
584 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
585 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
586 .modulemode = MODULEMODE_HWCTRL,
587 },
588 },
589 .opt_clks = gpio8_opt_clks,
590 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
591 .dev_attr = &gpio_dev_attr,
592 };
593
594 /*
595 * 'i2c' class
596 * multimaster high-speed i2c controller
597 */
598
599 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
600 .sysc_offs = 0x0010,
601 .syss_offs = 0x0090,
602 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
603 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
604 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
605 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
606 SIDLE_SMART_WKUP),
607 .clockact = CLOCKACT_TEST_ICLK,
608 .sysc_fields = &omap_hwmod_sysc_type1,
609 };
610
611 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
612 .name = "i2c",
613 .sysc = &omap54xx_i2c_sysc,
614 .reset = &omap_i2c_reset,
615 .rev = OMAP_I2C_IP_VERSION_2,
616 };
617
618 /* i2c dev_attr */
619 static struct omap_i2c_dev_attr i2c_dev_attr = {
620 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
621 };
622
623 /* i2c1 */
624 static struct omap_hwmod omap54xx_i2c1_hwmod = {
625 .name = "i2c1",
626 .class = &omap54xx_i2c_hwmod_class,
627 .clkdm_name = "l4per_clkdm",
628 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
629 .main_clk = "func_96m_fclk",
630 .prcm = {
631 .omap4 = {
632 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
633 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
634 .modulemode = MODULEMODE_SWCTRL,
635 },
636 },
637 .dev_attr = &i2c_dev_attr,
638 };
639
640 /* i2c2 */
641 static struct omap_hwmod omap54xx_i2c2_hwmod = {
642 .name = "i2c2",
643 .class = &omap54xx_i2c_hwmod_class,
644 .clkdm_name = "l4per_clkdm",
645 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
646 .main_clk = "func_96m_fclk",
647 .prcm = {
648 .omap4 = {
649 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
650 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
651 .modulemode = MODULEMODE_SWCTRL,
652 },
653 },
654 .dev_attr = &i2c_dev_attr,
655 };
656
657 /* i2c3 */
658 static struct omap_hwmod omap54xx_i2c3_hwmod = {
659 .name = "i2c3",
660 .class = &omap54xx_i2c_hwmod_class,
661 .clkdm_name = "l4per_clkdm",
662 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
663 .main_clk = "func_96m_fclk",
664 .prcm = {
665 .omap4 = {
666 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
667 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
668 .modulemode = MODULEMODE_SWCTRL,
669 },
670 },
671 .dev_attr = &i2c_dev_attr,
672 };
673
674 /* i2c4 */
675 static struct omap_hwmod omap54xx_i2c4_hwmod = {
676 .name = "i2c4",
677 .class = &omap54xx_i2c_hwmod_class,
678 .clkdm_name = "l4per_clkdm",
679 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
680 .main_clk = "func_96m_fclk",
681 .prcm = {
682 .omap4 = {
683 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
684 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
685 .modulemode = MODULEMODE_SWCTRL,
686 },
687 },
688 .dev_attr = &i2c_dev_attr,
689 };
690
691 /* i2c5 */
692 static struct omap_hwmod omap54xx_i2c5_hwmod = {
693 .name = "i2c5",
694 .class = &omap54xx_i2c_hwmod_class,
695 .clkdm_name = "l4per_clkdm",
696 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
697 .main_clk = "func_96m_fclk",
698 .prcm = {
699 .omap4 = {
700 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
701 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
702 .modulemode = MODULEMODE_SWCTRL,
703 },
704 },
705 .dev_attr = &i2c_dev_attr,
706 };
707
708 /*
709 * 'kbd' class
710 * keyboard controller
711 */
712
713 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
714 .rev_offs = 0x0000,
715 .sysc_offs = 0x0010,
716 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
717 SYSC_HAS_SOFTRESET),
718 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
719 .sysc_fields = &omap_hwmod_sysc_type1,
720 };
721
722 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
723 .name = "kbd",
724 .sysc = &omap54xx_kbd_sysc,
725 };
726
727 /* kbd */
728 static struct omap_hwmod omap54xx_kbd_hwmod = {
729 .name = "kbd",
730 .class = &omap54xx_kbd_hwmod_class,
731 .clkdm_name = "wkupaon_clkdm",
732 .main_clk = "sys_32k_ck",
733 .prcm = {
734 .omap4 = {
735 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
736 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
737 .modulemode = MODULEMODE_SWCTRL,
738 },
739 },
740 };
741
742 /*
743 * 'mailbox' class
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
746 */
747
748 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
749 .rev_offs = 0x0000,
750 .sysc_offs = 0x0010,
751 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
752 SYSC_HAS_SOFTRESET),
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type2,
755 };
756
757 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
758 .name = "mailbox",
759 .sysc = &omap54xx_mailbox_sysc,
760 };
761
762 /* mailbox */
763 static struct omap_hwmod omap54xx_mailbox_hwmod = {
764 .name = "mailbox",
765 .class = &omap54xx_mailbox_hwmod_class,
766 .clkdm_name = "l4cfg_clkdm",
767 .prcm = {
768 .omap4 = {
769 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
770 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
771 },
772 },
773 };
774
775 /*
776 * 'mcbsp' class
777 * multi channel buffered serial port controller
778 */
779
780 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
781 .sysc_offs = 0x008c,
782 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
783 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
784 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
785 .sysc_fields = &omap_hwmod_sysc_type1,
786 };
787
788 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
789 .name = "mcbsp",
790 .sysc = &omap54xx_mcbsp_sysc,
791 .rev = MCBSP_CONFIG_TYPE4,
792 };
793
794 /* mcbsp1 */
795 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
796 { .role = "pad_fck", .clk = "pad_clks_ck" },
797 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
798 };
799
800 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
801 .name = "mcbsp1",
802 .class = &omap54xx_mcbsp_hwmod_class,
803 .clkdm_name = "abe_clkdm",
804 .main_clk = "mcbsp1_gfclk",
805 .prcm = {
806 .omap4 = {
807 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
808 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
809 .modulemode = MODULEMODE_SWCTRL,
810 },
811 },
812 .opt_clks = mcbsp1_opt_clks,
813 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
814 };
815
816 /* mcbsp2 */
817 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
818 { .role = "pad_fck", .clk = "pad_clks_ck" },
819 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
820 };
821
822 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
823 .name = "mcbsp2",
824 .class = &omap54xx_mcbsp_hwmod_class,
825 .clkdm_name = "abe_clkdm",
826 .main_clk = "mcbsp2_gfclk",
827 .prcm = {
828 .omap4 = {
829 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
830 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
831 .modulemode = MODULEMODE_SWCTRL,
832 },
833 },
834 .opt_clks = mcbsp2_opt_clks,
835 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
836 };
837
838 /* mcbsp3 */
839 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
840 { .role = "pad_fck", .clk = "pad_clks_ck" },
841 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
842 };
843
844 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
845 .name = "mcbsp3",
846 .class = &omap54xx_mcbsp_hwmod_class,
847 .clkdm_name = "abe_clkdm",
848 .main_clk = "mcbsp3_gfclk",
849 .prcm = {
850 .omap4 = {
851 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
852 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
853 .modulemode = MODULEMODE_SWCTRL,
854 },
855 },
856 .opt_clks = mcbsp3_opt_clks,
857 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
858 };
859
860 /*
861 * 'mcpdm' class
862 * multi channel pdm controller (proprietary interface with phoenix power
863 * ic)
864 */
865
866 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
867 .rev_offs = 0x0000,
868 .sysc_offs = 0x0010,
869 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
870 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
872 SIDLE_SMART_WKUP),
873 .sysc_fields = &omap_hwmod_sysc_type2,
874 };
875
876 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
877 .name = "mcpdm",
878 .sysc = &omap54xx_mcpdm_sysc,
879 };
880
881 /* mcpdm */
882 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
883 .name = "mcpdm",
884 .class = &omap54xx_mcpdm_hwmod_class,
885 .clkdm_name = "abe_clkdm",
886 /*
887 * It's suspected that the McPDM requires an off-chip main
888 * functional clock, controlled via I2C. This IP block is
889 * currently reset very early during boot, before I2C is
890 * available, so it doesn't seem that we have any choice in
891 * the kernel other than to avoid resetting it. XXX This is
892 * really a hardware issue workaround: every IP block should
893 * be able to source its main functional clock from either
894 * on-chip or off-chip sources. McPDM seems to be the only
895 * current exception.
896 */
897
898 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
899 .main_clk = "pad_clks_ck",
900 .prcm = {
901 .omap4 = {
902 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
903 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
904 .modulemode = MODULEMODE_SWCTRL,
905 },
906 },
907 };
908
909 /*
910 * 'mcspi' class
911 * multichannel serial port interface (mcspi) / master/slave synchronous serial
912 * bus
913 */
914
915 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
916 .rev_offs = 0x0000,
917 .sysc_offs = 0x0010,
918 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
919 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
921 SIDLE_SMART_WKUP),
922 .sysc_fields = &omap_hwmod_sysc_type2,
923 };
924
925 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
926 .name = "mcspi",
927 .sysc = &omap54xx_mcspi_sysc,
928 .rev = OMAP4_MCSPI_REV,
929 };
930
931 /* mcspi1 */
932 /* mcspi1 dev_attr */
933 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
934 .num_chipselect = 4,
935 };
936
937 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
938 .name = "mcspi1",
939 .class = &omap54xx_mcspi_hwmod_class,
940 .clkdm_name = "l4per_clkdm",
941 .main_clk = "func_48m_fclk",
942 .prcm = {
943 .omap4 = {
944 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
945 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
946 .modulemode = MODULEMODE_SWCTRL,
947 },
948 },
949 .dev_attr = &mcspi1_dev_attr,
950 };
951
952 /* mcspi2 */
953 /* mcspi2 dev_attr */
954 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
955 .num_chipselect = 2,
956 };
957
958 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
959 .name = "mcspi2",
960 .class = &omap54xx_mcspi_hwmod_class,
961 .clkdm_name = "l4per_clkdm",
962 .main_clk = "func_48m_fclk",
963 .prcm = {
964 .omap4 = {
965 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
966 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
968 },
969 },
970 .dev_attr = &mcspi2_dev_attr,
971 };
972
973 /* mcspi3 */
974 /* mcspi3 dev_attr */
975 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
976 .num_chipselect = 2,
977 };
978
979 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
980 .name = "mcspi3",
981 .class = &omap54xx_mcspi_hwmod_class,
982 .clkdm_name = "l4per_clkdm",
983 .main_clk = "func_48m_fclk",
984 .prcm = {
985 .omap4 = {
986 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
987 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
988 .modulemode = MODULEMODE_SWCTRL,
989 },
990 },
991 .dev_attr = &mcspi3_dev_attr,
992 };
993
994 /* mcspi4 */
995 /* mcspi4 dev_attr */
996 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
997 .num_chipselect = 1,
998 };
999
1000 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1001 .name = "mcspi4",
1002 .class = &omap54xx_mcspi_hwmod_class,
1003 .clkdm_name = "l4per_clkdm",
1004 .main_clk = "func_48m_fclk",
1005 .prcm = {
1006 .omap4 = {
1007 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1008 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1009 .modulemode = MODULEMODE_SWCTRL,
1010 },
1011 },
1012 .dev_attr = &mcspi4_dev_attr,
1013 };
1014
1015 /*
1016 * 'mmc' class
1017 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1018 */
1019
1020 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1021 .rev_offs = 0x0000,
1022 .sysc_offs = 0x0010,
1023 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1024 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1025 SYSC_HAS_SOFTRESET),
1026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1027 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1028 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1029 .sysc_fields = &omap_hwmod_sysc_type2,
1030 };
1031
1032 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1033 .name = "mmc",
1034 .sysc = &omap54xx_mmc_sysc,
1035 };
1036
1037 /* mmc1 */
1038 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1039 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1040 };
1041
1042 /* mmc1 dev_attr */
1043 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1044 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1045 };
1046
1047 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1048 .name = "mmc1",
1049 .class = &omap54xx_mmc_hwmod_class,
1050 .clkdm_name = "l3init_clkdm",
1051 .main_clk = "mmc1_fclk",
1052 .prcm = {
1053 .omap4 = {
1054 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1055 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1056 .modulemode = MODULEMODE_SWCTRL,
1057 },
1058 },
1059 .opt_clks = mmc1_opt_clks,
1060 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1061 .dev_attr = &mmc1_dev_attr,
1062 };
1063
1064 /* mmc2 */
1065 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1066 .name = "mmc2",
1067 .class = &omap54xx_mmc_hwmod_class,
1068 .clkdm_name = "l3init_clkdm",
1069 .main_clk = "mmc2_fclk",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1073 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1074 .modulemode = MODULEMODE_SWCTRL,
1075 },
1076 },
1077 };
1078
1079 /* mmc3 */
1080 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1081 .name = "mmc3",
1082 .class = &omap54xx_mmc_hwmod_class,
1083 .clkdm_name = "l4per_clkdm",
1084 .main_clk = "func_48m_fclk",
1085 .prcm = {
1086 .omap4 = {
1087 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1088 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1089 .modulemode = MODULEMODE_SWCTRL,
1090 },
1091 },
1092 };
1093
1094 /* mmc4 */
1095 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1096 .name = "mmc4",
1097 .class = &omap54xx_mmc_hwmod_class,
1098 .clkdm_name = "l4per_clkdm",
1099 .main_clk = "func_48m_fclk",
1100 .prcm = {
1101 .omap4 = {
1102 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1103 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1104 .modulemode = MODULEMODE_SWCTRL,
1105 },
1106 },
1107 };
1108
1109 /* mmc5 */
1110 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1111 .name = "mmc5",
1112 .class = &omap54xx_mmc_hwmod_class,
1113 .clkdm_name = "l4per_clkdm",
1114 .main_clk = "func_96m_fclk",
1115 .prcm = {
1116 .omap4 = {
1117 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1118 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1120 },
1121 },
1122 };
1123
1124 /*
1125 * 'mpu' class
1126 * mpu sub-system
1127 */
1128
1129 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1130 .name = "mpu",
1131 };
1132
1133 /* mpu */
1134 static struct omap_hwmod omap54xx_mpu_hwmod = {
1135 .name = "mpu",
1136 .class = &omap54xx_mpu_hwmod_class,
1137 .clkdm_name = "mpu_clkdm",
1138 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1139 .main_clk = "dpll_mpu_m2_ck",
1140 .prcm = {
1141 .omap4 = {
1142 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1143 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1144 },
1145 },
1146 };
1147
1148 /*
1149 * 'timer' class
1150 * general purpose timer module with accurate 1ms tick
1151 * This class contains several variants: ['timer_1ms', 'timer']
1152 */
1153
1154 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1155 .rev_offs = 0x0000,
1156 .sysc_offs = 0x0010,
1157 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1158 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1159 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1160 SIDLE_SMART_WKUP),
1161 .sysc_fields = &omap_hwmod_sysc_type2,
1162 .clockact = CLOCKACT_TEST_ICLK,
1163 };
1164
1165 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1166 .name = "timer",
1167 .sysc = &omap54xx_timer_1ms_sysc,
1168 };
1169
1170 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1171 .rev_offs = 0x0000,
1172 .sysc_offs = 0x0010,
1173 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1174 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1175 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1176 SIDLE_SMART_WKUP),
1177 .sysc_fields = &omap_hwmod_sysc_type2,
1178 };
1179
1180 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1181 .name = "timer",
1182 .sysc = &omap54xx_timer_sysc,
1183 };
1184
1185 /* timer1 */
1186 static struct omap_hwmod omap54xx_timer1_hwmod = {
1187 .name = "timer1",
1188 .class = &omap54xx_timer_1ms_hwmod_class,
1189 .clkdm_name = "wkupaon_clkdm",
1190 .main_clk = "timer1_gfclk_mux",
1191 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1192 .prcm = {
1193 .omap4 = {
1194 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1195 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1196 .modulemode = MODULEMODE_SWCTRL,
1197 },
1198 },
1199 };
1200
1201 /* timer2 */
1202 static struct omap_hwmod omap54xx_timer2_hwmod = {
1203 .name = "timer2",
1204 .class = &omap54xx_timer_1ms_hwmod_class,
1205 .clkdm_name = "l4per_clkdm",
1206 .main_clk = "timer2_gfclk_mux",
1207 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1208 .prcm = {
1209 .omap4 = {
1210 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1211 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1212 .modulemode = MODULEMODE_SWCTRL,
1213 },
1214 },
1215 };
1216
1217 /* timer3 */
1218 static struct omap_hwmod omap54xx_timer3_hwmod = {
1219 .name = "timer3",
1220 .class = &omap54xx_timer_hwmod_class,
1221 .clkdm_name = "l4per_clkdm",
1222 .main_clk = "timer3_gfclk_mux",
1223 .prcm = {
1224 .omap4 = {
1225 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1226 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_SWCTRL,
1228 },
1229 },
1230 };
1231
1232 /* timer4 */
1233 static struct omap_hwmod omap54xx_timer4_hwmod = {
1234 .name = "timer4",
1235 .class = &omap54xx_timer_hwmod_class,
1236 .clkdm_name = "l4per_clkdm",
1237 .main_clk = "timer4_gfclk_mux",
1238 .prcm = {
1239 .omap4 = {
1240 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1241 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1242 .modulemode = MODULEMODE_SWCTRL,
1243 },
1244 },
1245 };
1246
1247 /* timer5 */
1248 static struct omap_hwmod omap54xx_timer5_hwmod = {
1249 .name = "timer5",
1250 .class = &omap54xx_timer_hwmod_class,
1251 .clkdm_name = "abe_clkdm",
1252 .main_clk = "timer5_gfclk_mux",
1253 .prcm = {
1254 .omap4 = {
1255 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1256 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1257 .modulemode = MODULEMODE_SWCTRL,
1258 },
1259 },
1260 };
1261
1262 /* timer6 */
1263 static struct omap_hwmod omap54xx_timer6_hwmod = {
1264 .name = "timer6",
1265 .class = &omap54xx_timer_hwmod_class,
1266 .clkdm_name = "abe_clkdm",
1267 .main_clk = "timer6_gfclk_mux",
1268 .prcm = {
1269 .omap4 = {
1270 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1271 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1272 .modulemode = MODULEMODE_SWCTRL,
1273 },
1274 },
1275 };
1276
1277 /* timer7 */
1278 static struct omap_hwmod omap54xx_timer7_hwmod = {
1279 .name = "timer7",
1280 .class = &omap54xx_timer_hwmod_class,
1281 .clkdm_name = "abe_clkdm",
1282 .main_clk = "timer7_gfclk_mux",
1283 .prcm = {
1284 .omap4 = {
1285 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1286 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1287 .modulemode = MODULEMODE_SWCTRL,
1288 },
1289 },
1290 };
1291
1292 /* timer8 */
1293 static struct omap_hwmod omap54xx_timer8_hwmod = {
1294 .name = "timer8",
1295 .class = &omap54xx_timer_hwmod_class,
1296 .clkdm_name = "abe_clkdm",
1297 .main_clk = "timer8_gfclk_mux",
1298 .prcm = {
1299 .omap4 = {
1300 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1301 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1302 .modulemode = MODULEMODE_SWCTRL,
1303 },
1304 },
1305 };
1306
1307 /* timer9 */
1308 static struct omap_hwmod omap54xx_timer9_hwmod = {
1309 .name = "timer9",
1310 .class = &omap54xx_timer_hwmod_class,
1311 .clkdm_name = "l4per_clkdm",
1312 .main_clk = "timer9_gfclk_mux",
1313 .prcm = {
1314 .omap4 = {
1315 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1316 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1317 .modulemode = MODULEMODE_SWCTRL,
1318 },
1319 },
1320 };
1321
1322 /* timer10 */
1323 static struct omap_hwmod omap54xx_timer10_hwmod = {
1324 .name = "timer10",
1325 .class = &omap54xx_timer_1ms_hwmod_class,
1326 .clkdm_name = "l4per_clkdm",
1327 .main_clk = "timer10_gfclk_mux",
1328 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1329 .prcm = {
1330 .omap4 = {
1331 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1332 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1333 .modulemode = MODULEMODE_SWCTRL,
1334 },
1335 },
1336 };
1337
1338 /* timer11 */
1339 static struct omap_hwmod omap54xx_timer11_hwmod = {
1340 .name = "timer11",
1341 .class = &omap54xx_timer_hwmod_class,
1342 .clkdm_name = "l4per_clkdm",
1343 .main_clk = "timer11_gfclk_mux",
1344 .prcm = {
1345 .omap4 = {
1346 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1347 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1348 .modulemode = MODULEMODE_SWCTRL,
1349 },
1350 },
1351 };
1352
1353 /*
1354 * 'uart' class
1355 * universal asynchronous receiver/transmitter (uart)
1356 */
1357
1358 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1359 .rev_offs = 0x0050,
1360 .sysc_offs = 0x0054,
1361 .syss_offs = 0x0058,
1362 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1363 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1364 SYSS_HAS_RESET_STATUS),
1365 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1366 SIDLE_SMART_WKUP),
1367 .sysc_fields = &omap_hwmod_sysc_type1,
1368 };
1369
1370 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1371 .name = "uart",
1372 .sysc = &omap54xx_uart_sysc,
1373 };
1374
1375 /* uart1 */
1376 static struct omap_hwmod omap54xx_uart1_hwmod = {
1377 .name = "uart1",
1378 .class = &omap54xx_uart_hwmod_class,
1379 .clkdm_name = "l4per_clkdm",
1380 .main_clk = "func_48m_fclk",
1381 .prcm = {
1382 .omap4 = {
1383 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1384 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1385 .modulemode = MODULEMODE_SWCTRL,
1386 },
1387 },
1388 };
1389
1390 /* uart2 */
1391 static struct omap_hwmod omap54xx_uart2_hwmod = {
1392 .name = "uart2",
1393 .class = &omap54xx_uart_hwmod_class,
1394 .clkdm_name = "l4per_clkdm",
1395 .main_clk = "func_48m_fclk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1399 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403 };
1404
1405 /* uart3 */
1406 static struct omap_hwmod omap54xx_uart3_hwmod = {
1407 .name = "uart3",
1408 .class = &omap54xx_uart_hwmod_class,
1409 .clkdm_name = "l4per_clkdm",
1410 .flags = DEBUG_OMAP4UART3_FLAGS,
1411 .main_clk = "func_48m_fclk",
1412 .prcm = {
1413 .omap4 = {
1414 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1415 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1416 .modulemode = MODULEMODE_SWCTRL,
1417 },
1418 },
1419 };
1420
1421 /* uart4 */
1422 static struct omap_hwmod omap54xx_uart4_hwmod = {
1423 .name = "uart4",
1424 .class = &omap54xx_uart_hwmod_class,
1425 .clkdm_name = "l4per_clkdm",
1426 .flags = DEBUG_OMAP4UART4_FLAGS,
1427 .main_clk = "func_48m_fclk",
1428 .prcm = {
1429 .omap4 = {
1430 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1431 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1432 .modulemode = MODULEMODE_SWCTRL,
1433 },
1434 },
1435 };
1436
1437 /* uart5 */
1438 static struct omap_hwmod omap54xx_uart5_hwmod = {
1439 .name = "uart5",
1440 .class = &omap54xx_uart_hwmod_class,
1441 .clkdm_name = "l4per_clkdm",
1442 .main_clk = "func_48m_fclk",
1443 .prcm = {
1444 .omap4 = {
1445 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1446 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1447 .modulemode = MODULEMODE_SWCTRL,
1448 },
1449 },
1450 };
1451
1452 /* uart6 */
1453 static struct omap_hwmod omap54xx_uart6_hwmod = {
1454 .name = "uart6",
1455 .class = &omap54xx_uart_hwmod_class,
1456 .clkdm_name = "l4per_clkdm",
1457 .main_clk = "func_48m_fclk",
1458 .prcm = {
1459 .omap4 = {
1460 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1461 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1462 .modulemode = MODULEMODE_SWCTRL,
1463 },
1464 },
1465 };
1466
1467 /*
1468 * 'usb_otg_ss' class
1469 * 2.0 super speed (usb_otg_ss) controller
1470 */
1471
1472 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1473 .rev_offs = 0x0000,
1474 .sysc_offs = 0x0010,
1475 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1476 SYSC_HAS_SIDLEMODE),
1477 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1478 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1479 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1480 .sysc_fields = &omap_hwmod_sysc_type2,
1481 };
1482
1483 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1484 .name = "usb_otg_ss",
1485 .sysc = &omap54xx_usb_otg_ss_sysc,
1486 };
1487
1488 /* usb_otg_ss */
1489 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1490 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1491 };
1492
1493 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1494 .name = "usb_otg_ss",
1495 .class = &omap54xx_usb_otg_ss_hwmod_class,
1496 .clkdm_name = "l3init_clkdm",
1497 .flags = HWMOD_SWSUP_SIDLE,
1498 .main_clk = "dpll_core_h13x2_ck",
1499 .prcm = {
1500 .omap4 = {
1501 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1502 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1503 .modulemode = MODULEMODE_HWCTRL,
1504 },
1505 },
1506 .opt_clks = usb_otg_ss_opt_clks,
1507 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1508 };
1509
1510 /*
1511 * 'wd_timer' class
1512 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1513 * overflow condition
1514 */
1515
1516 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1517 .rev_offs = 0x0000,
1518 .sysc_offs = 0x0010,
1519 .syss_offs = 0x0014,
1520 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1521 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1522 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1523 SIDLE_SMART_WKUP),
1524 .sysc_fields = &omap_hwmod_sysc_type1,
1525 };
1526
1527 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1528 .name = "wd_timer",
1529 .sysc = &omap54xx_wd_timer_sysc,
1530 .pre_shutdown = &omap2_wd_timer_disable,
1531 };
1532
1533 /* wd_timer2 */
1534 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1535 .name = "wd_timer2",
1536 .class = &omap54xx_wd_timer_hwmod_class,
1537 .clkdm_name = "wkupaon_clkdm",
1538 .main_clk = "sys_32k_ck",
1539 .prcm = {
1540 .omap4 = {
1541 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1542 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1543 .modulemode = MODULEMODE_SWCTRL,
1544 },
1545 },
1546 };
1547
1548
1549 /*
1550 * Interfaces
1551 */
1552
1553 /* l3_main_1 -> dmm */
1554 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1555 .master = &omap54xx_l3_main_1_hwmod,
1556 .slave = &omap54xx_dmm_hwmod,
1557 .clk = "l3_iclk_div",
1558 .user = OCP_USER_SDMA,
1559 };
1560
1561 /* l3_main_3 -> l3_instr */
1562 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1563 .master = &omap54xx_l3_main_3_hwmod,
1564 .slave = &omap54xx_l3_instr_hwmod,
1565 .clk = "l3_iclk_div",
1566 .user = OCP_USER_MPU | OCP_USER_SDMA,
1567 };
1568
1569 /* l3_main_2 -> l3_main_1 */
1570 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1571 .master = &omap54xx_l3_main_2_hwmod,
1572 .slave = &omap54xx_l3_main_1_hwmod,
1573 .clk = "l3_iclk_div",
1574 .user = OCP_USER_MPU | OCP_USER_SDMA,
1575 };
1576
1577 /* l4_cfg -> l3_main_1 */
1578 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1579 .master = &omap54xx_l4_cfg_hwmod,
1580 .slave = &omap54xx_l3_main_1_hwmod,
1581 .clk = "l3_iclk_div",
1582 .user = OCP_USER_MPU | OCP_USER_SDMA,
1583 };
1584
1585 /* mpu -> l3_main_1 */
1586 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1587 .master = &omap54xx_mpu_hwmod,
1588 .slave = &omap54xx_l3_main_1_hwmod,
1589 .clk = "l3_iclk_div",
1590 .user = OCP_USER_MPU,
1591 };
1592
1593 /* l3_main_1 -> l3_main_2 */
1594 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1595 .master = &omap54xx_l3_main_1_hwmod,
1596 .slave = &omap54xx_l3_main_2_hwmod,
1597 .clk = "l3_iclk_div",
1598 .user = OCP_USER_MPU,
1599 };
1600
1601 /* l4_cfg -> l3_main_2 */
1602 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1603 .master = &omap54xx_l4_cfg_hwmod,
1604 .slave = &omap54xx_l3_main_2_hwmod,
1605 .clk = "l3_iclk_div",
1606 .user = OCP_USER_MPU | OCP_USER_SDMA,
1607 };
1608
1609 /* l3_main_1 -> l3_main_3 */
1610 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1611 .master = &omap54xx_l3_main_1_hwmod,
1612 .slave = &omap54xx_l3_main_3_hwmod,
1613 .clk = "l3_iclk_div",
1614 .user = OCP_USER_MPU,
1615 };
1616
1617 /* l3_main_2 -> l3_main_3 */
1618 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1619 .master = &omap54xx_l3_main_2_hwmod,
1620 .slave = &omap54xx_l3_main_3_hwmod,
1621 .clk = "l3_iclk_div",
1622 .user = OCP_USER_MPU | OCP_USER_SDMA,
1623 };
1624
1625 /* l4_cfg -> l3_main_3 */
1626 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1627 .master = &omap54xx_l4_cfg_hwmod,
1628 .slave = &omap54xx_l3_main_3_hwmod,
1629 .clk = "l3_iclk_div",
1630 .user = OCP_USER_MPU | OCP_USER_SDMA,
1631 };
1632
1633 /* l3_main_1 -> l4_abe */
1634 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1635 .master = &omap54xx_l3_main_1_hwmod,
1636 .slave = &omap54xx_l4_abe_hwmod,
1637 .clk = "abe_iclk",
1638 .user = OCP_USER_MPU | OCP_USER_SDMA,
1639 };
1640
1641 /* mpu -> l4_abe */
1642 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1643 .master = &omap54xx_mpu_hwmod,
1644 .slave = &omap54xx_l4_abe_hwmod,
1645 .clk = "abe_iclk",
1646 .user = OCP_USER_MPU | OCP_USER_SDMA,
1647 };
1648
1649 /* l3_main_1 -> l4_cfg */
1650 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1651 .master = &omap54xx_l3_main_1_hwmod,
1652 .slave = &omap54xx_l4_cfg_hwmod,
1653 .clk = "l4_root_clk_div",
1654 .user = OCP_USER_MPU | OCP_USER_SDMA,
1655 };
1656
1657 /* l3_main_2 -> l4_per */
1658 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1659 .master = &omap54xx_l3_main_2_hwmod,
1660 .slave = &omap54xx_l4_per_hwmod,
1661 .clk = "l4_root_clk_div",
1662 .user = OCP_USER_MPU | OCP_USER_SDMA,
1663 };
1664
1665 /* l3_main_1 -> l4_wkup */
1666 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1667 .master = &omap54xx_l3_main_1_hwmod,
1668 .slave = &omap54xx_l4_wkup_hwmod,
1669 .clk = "wkupaon_iclk_mux",
1670 .user = OCP_USER_MPU | OCP_USER_SDMA,
1671 };
1672
1673 /* mpu -> mpu_private */
1674 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1675 .master = &omap54xx_mpu_hwmod,
1676 .slave = &omap54xx_mpu_private_hwmod,
1677 .clk = "l3_iclk_div",
1678 .user = OCP_USER_MPU | OCP_USER_SDMA,
1679 };
1680
1681 /* l4_wkup -> counter_32k */
1682 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1683 .master = &omap54xx_l4_wkup_hwmod,
1684 .slave = &omap54xx_counter_32k_hwmod,
1685 .clk = "wkupaon_iclk_mux",
1686 .user = OCP_USER_MPU | OCP_USER_SDMA,
1687 };
1688
1689 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1690 {
1691 .pa_start = 0x4a056000,
1692 .pa_end = 0x4a056fff,
1693 .flags = ADDR_TYPE_RT
1694 },
1695 { }
1696 };
1697
1698 /* l4_cfg -> dma_system */
1699 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1700 .master = &omap54xx_l4_cfg_hwmod,
1701 .slave = &omap54xx_dma_system_hwmod,
1702 .clk = "l4_root_clk_div",
1703 .addr = omap54xx_dma_system_addrs,
1704 .user = OCP_USER_MPU | OCP_USER_SDMA,
1705 };
1706
1707 /* l4_abe -> dmic */
1708 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1709 .master = &omap54xx_l4_abe_hwmod,
1710 .slave = &omap54xx_dmic_hwmod,
1711 .clk = "abe_iclk",
1712 .user = OCP_USER_MPU,
1713 };
1714
1715 /* mpu -> emif1 */
1716 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1717 .master = &omap54xx_mpu_hwmod,
1718 .slave = &omap54xx_emif1_hwmod,
1719 .clk = "dpll_core_h11x2_ck",
1720 .user = OCP_USER_MPU | OCP_USER_SDMA,
1721 };
1722
1723 /* mpu -> emif2 */
1724 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1725 .master = &omap54xx_mpu_hwmod,
1726 .slave = &omap54xx_emif2_hwmod,
1727 .clk = "dpll_core_h11x2_ck",
1728 .user = OCP_USER_MPU | OCP_USER_SDMA,
1729 };
1730
1731 /* l4_wkup -> gpio1 */
1732 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1733 .master = &omap54xx_l4_wkup_hwmod,
1734 .slave = &omap54xx_gpio1_hwmod,
1735 .clk = "wkupaon_iclk_mux",
1736 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737 };
1738
1739 /* l4_per -> gpio2 */
1740 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1741 .master = &omap54xx_l4_per_hwmod,
1742 .slave = &omap54xx_gpio2_hwmod,
1743 .clk = "l4_root_clk_div",
1744 .user = OCP_USER_MPU | OCP_USER_SDMA,
1745 };
1746
1747 /* l4_per -> gpio3 */
1748 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1749 .master = &omap54xx_l4_per_hwmod,
1750 .slave = &omap54xx_gpio3_hwmod,
1751 .clk = "l4_root_clk_div",
1752 .user = OCP_USER_MPU | OCP_USER_SDMA,
1753 };
1754
1755 /* l4_per -> gpio4 */
1756 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1757 .master = &omap54xx_l4_per_hwmod,
1758 .slave = &omap54xx_gpio4_hwmod,
1759 .clk = "l4_root_clk_div",
1760 .user = OCP_USER_MPU | OCP_USER_SDMA,
1761 };
1762
1763 /* l4_per -> gpio5 */
1764 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1765 .master = &omap54xx_l4_per_hwmod,
1766 .slave = &omap54xx_gpio5_hwmod,
1767 .clk = "l4_root_clk_div",
1768 .user = OCP_USER_MPU | OCP_USER_SDMA,
1769 };
1770
1771 /* l4_per -> gpio6 */
1772 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1773 .master = &omap54xx_l4_per_hwmod,
1774 .slave = &omap54xx_gpio6_hwmod,
1775 .clk = "l4_root_clk_div",
1776 .user = OCP_USER_MPU | OCP_USER_SDMA,
1777 };
1778
1779 /* l4_per -> gpio7 */
1780 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1781 .master = &omap54xx_l4_per_hwmod,
1782 .slave = &omap54xx_gpio7_hwmod,
1783 .clk = "l4_root_clk_div",
1784 .user = OCP_USER_MPU | OCP_USER_SDMA,
1785 };
1786
1787 /* l4_per -> gpio8 */
1788 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1789 .master = &omap54xx_l4_per_hwmod,
1790 .slave = &omap54xx_gpio8_hwmod,
1791 .clk = "l4_root_clk_div",
1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
1793 };
1794
1795 /* l4_per -> i2c1 */
1796 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1797 .master = &omap54xx_l4_per_hwmod,
1798 .slave = &omap54xx_i2c1_hwmod,
1799 .clk = "l4_root_clk_div",
1800 .user = OCP_USER_MPU | OCP_USER_SDMA,
1801 };
1802
1803 /* l4_per -> i2c2 */
1804 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1805 .master = &omap54xx_l4_per_hwmod,
1806 .slave = &omap54xx_i2c2_hwmod,
1807 .clk = "l4_root_clk_div",
1808 .user = OCP_USER_MPU | OCP_USER_SDMA,
1809 };
1810
1811 /* l4_per -> i2c3 */
1812 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1813 .master = &omap54xx_l4_per_hwmod,
1814 .slave = &omap54xx_i2c3_hwmod,
1815 .clk = "l4_root_clk_div",
1816 .user = OCP_USER_MPU | OCP_USER_SDMA,
1817 };
1818
1819 /* l4_per -> i2c4 */
1820 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1821 .master = &omap54xx_l4_per_hwmod,
1822 .slave = &omap54xx_i2c4_hwmod,
1823 .clk = "l4_root_clk_div",
1824 .user = OCP_USER_MPU | OCP_USER_SDMA,
1825 };
1826
1827 /* l4_per -> i2c5 */
1828 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1829 .master = &omap54xx_l4_per_hwmod,
1830 .slave = &omap54xx_i2c5_hwmod,
1831 .clk = "l4_root_clk_div",
1832 .user = OCP_USER_MPU | OCP_USER_SDMA,
1833 };
1834
1835 /* l4_wkup -> kbd */
1836 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1837 .master = &omap54xx_l4_wkup_hwmod,
1838 .slave = &omap54xx_kbd_hwmod,
1839 .clk = "wkupaon_iclk_mux",
1840 .user = OCP_USER_MPU | OCP_USER_SDMA,
1841 };
1842
1843 /* l4_cfg -> mailbox */
1844 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
1845 .master = &omap54xx_l4_cfg_hwmod,
1846 .slave = &omap54xx_mailbox_hwmod,
1847 .clk = "l4_root_clk_div",
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849 };
1850
1851 /* l4_abe -> mcbsp1 */
1852 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1853 .master = &omap54xx_l4_abe_hwmod,
1854 .slave = &omap54xx_mcbsp1_hwmod,
1855 .clk = "abe_iclk",
1856 .user = OCP_USER_MPU,
1857 };
1858
1859 /* l4_abe -> mcbsp2 */
1860 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1861 .master = &omap54xx_l4_abe_hwmod,
1862 .slave = &omap54xx_mcbsp2_hwmod,
1863 .clk = "abe_iclk",
1864 .user = OCP_USER_MPU,
1865 };
1866
1867 /* l4_abe -> mcbsp3 */
1868 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1869 .master = &omap54xx_l4_abe_hwmod,
1870 .slave = &omap54xx_mcbsp3_hwmod,
1871 .clk = "abe_iclk",
1872 .user = OCP_USER_MPU,
1873 };
1874
1875 /* l4_abe -> mcpdm */
1876 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1877 .master = &omap54xx_l4_abe_hwmod,
1878 .slave = &omap54xx_mcpdm_hwmod,
1879 .clk = "abe_iclk",
1880 .user = OCP_USER_MPU,
1881 };
1882
1883 /* l4_per -> mcspi1 */
1884 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1885 .master = &omap54xx_l4_per_hwmod,
1886 .slave = &omap54xx_mcspi1_hwmod,
1887 .clk = "l4_root_clk_div",
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889 };
1890
1891 /* l4_per -> mcspi2 */
1892 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1893 .master = &omap54xx_l4_per_hwmod,
1894 .slave = &omap54xx_mcspi2_hwmod,
1895 .clk = "l4_root_clk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897 };
1898
1899 /* l4_per -> mcspi3 */
1900 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1901 .master = &omap54xx_l4_per_hwmod,
1902 .slave = &omap54xx_mcspi3_hwmod,
1903 .clk = "l4_root_clk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905 };
1906
1907 /* l4_per -> mcspi4 */
1908 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1909 .master = &omap54xx_l4_per_hwmod,
1910 .slave = &omap54xx_mcspi4_hwmod,
1911 .clk = "l4_root_clk_div",
1912 .user = OCP_USER_MPU | OCP_USER_SDMA,
1913 };
1914
1915 /* l4_per -> mmc1 */
1916 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1917 .master = &omap54xx_l4_per_hwmod,
1918 .slave = &omap54xx_mmc1_hwmod,
1919 .clk = "l3_iclk_div",
1920 .user = OCP_USER_MPU | OCP_USER_SDMA,
1921 };
1922
1923 /* l4_per -> mmc2 */
1924 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1925 .master = &omap54xx_l4_per_hwmod,
1926 .slave = &omap54xx_mmc2_hwmod,
1927 .clk = "l3_iclk_div",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929 };
1930
1931 /* l4_per -> mmc3 */
1932 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1933 .master = &omap54xx_l4_per_hwmod,
1934 .slave = &omap54xx_mmc3_hwmod,
1935 .clk = "l4_root_clk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937 };
1938
1939 /* l4_per -> mmc4 */
1940 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1941 .master = &omap54xx_l4_per_hwmod,
1942 .slave = &omap54xx_mmc4_hwmod,
1943 .clk = "l4_root_clk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945 };
1946
1947 /* l4_per -> mmc5 */
1948 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1949 .master = &omap54xx_l4_per_hwmod,
1950 .slave = &omap54xx_mmc5_hwmod,
1951 .clk = "l4_root_clk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953 };
1954
1955 /* l4_cfg -> mpu */
1956 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1957 .master = &omap54xx_l4_cfg_hwmod,
1958 .slave = &omap54xx_mpu_hwmod,
1959 .clk = "l4_root_clk_div",
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
1961 };
1962
1963 /* l4_wkup -> timer1 */
1964 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1965 .master = &omap54xx_l4_wkup_hwmod,
1966 .slave = &omap54xx_timer1_hwmod,
1967 .clk = "wkupaon_iclk_mux",
1968 .user = OCP_USER_MPU | OCP_USER_SDMA,
1969 };
1970
1971 /* l4_per -> timer2 */
1972 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1973 .master = &omap54xx_l4_per_hwmod,
1974 .slave = &omap54xx_timer2_hwmod,
1975 .clk = "l4_root_clk_div",
1976 .user = OCP_USER_MPU | OCP_USER_SDMA,
1977 };
1978
1979 /* l4_per -> timer3 */
1980 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1981 .master = &omap54xx_l4_per_hwmod,
1982 .slave = &omap54xx_timer3_hwmod,
1983 .clk = "l4_root_clk_div",
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985 };
1986
1987 /* l4_per -> timer4 */
1988 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1989 .master = &omap54xx_l4_per_hwmod,
1990 .slave = &omap54xx_timer4_hwmod,
1991 .clk = "l4_root_clk_div",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993 };
1994
1995 /* l4_abe -> timer5 */
1996 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1997 .master = &omap54xx_l4_abe_hwmod,
1998 .slave = &omap54xx_timer5_hwmod,
1999 .clk = "abe_iclk",
2000 .user = OCP_USER_MPU,
2001 };
2002
2003 /* l4_abe -> timer6 */
2004 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2005 .master = &omap54xx_l4_abe_hwmod,
2006 .slave = &omap54xx_timer6_hwmod,
2007 .clk = "abe_iclk",
2008 .user = OCP_USER_MPU,
2009 };
2010
2011 /* l4_abe -> timer7 */
2012 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2013 .master = &omap54xx_l4_abe_hwmod,
2014 .slave = &omap54xx_timer7_hwmod,
2015 .clk = "abe_iclk",
2016 .user = OCP_USER_MPU,
2017 };
2018
2019 /* l4_abe -> timer8 */
2020 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2021 .master = &omap54xx_l4_abe_hwmod,
2022 .slave = &omap54xx_timer8_hwmod,
2023 .clk = "abe_iclk",
2024 .user = OCP_USER_MPU,
2025 };
2026
2027 /* l4_per -> timer9 */
2028 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2029 .master = &omap54xx_l4_per_hwmod,
2030 .slave = &omap54xx_timer9_hwmod,
2031 .clk = "l4_root_clk_div",
2032 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033 };
2034
2035 /* l4_per -> timer10 */
2036 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2037 .master = &omap54xx_l4_per_hwmod,
2038 .slave = &omap54xx_timer10_hwmod,
2039 .clk = "l4_root_clk_div",
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041 };
2042
2043 /* l4_per -> timer11 */
2044 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2045 .master = &omap54xx_l4_per_hwmod,
2046 .slave = &omap54xx_timer11_hwmod,
2047 .clk = "l4_root_clk_div",
2048 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049 };
2050
2051 /* l4_per -> uart1 */
2052 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2053 .master = &omap54xx_l4_per_hwmod,
2054 .slave = &omap54xx_uart1_hwmod,
2055 .clk = "l4_root_clk_div",
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057 };
2058
2059 /* l4_per -> uart2 */
2060 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2061 .master = &omap54xx_l4_per_hwmod,
2062 .slave = &omap54xx_uart2_hwmod,
2063 .clk = "l4_root_clk_div",
2064 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065 };
2066
2067 /* l4_per -> uart3 */
2068 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2069 .master = &omap54xx_l4_per_hwmod,
2070 .slave = &omap54xx_uart3_hwmod,
2071 .clk = "l4_root_clk_div",
2072 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073 };
2074
2075 /* l4_per -> uart4 */
2076 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2077 .master = &omap54xx_l4_per_hwmod,
2078 .slave = &omap54xx_uart4_hwmod,
2079 .clk = "l4_root_clk_div",
2080 .user = OCP_USER_MPU | OCP_USER_SDMA,
2081 };
2082
2083 /* l4_per -> uart5 */
2084 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2085 .master = &omap54xx_l4_per_hwmod,
2086 .slave = &omap54xx_uart5_hwmod,
2087 .clk = "l4_root_clk_div",
2088 .user = OCP_USER_MPU | OCP_USER_SDMA,
2089 };
2090
2091 /* l4_per -> uart6 */
2092 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2093 .master = &omap54xx_l4_per_hwmod,
2094 .slave = &omap54xx_uart6_hwmod,
2095 .clk = "l4_root_clk_div",
2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2097 };
2098
2099 /* l4_cfg -> usb_otg_ss */
2100 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2101 .master = &omap54xx_l4_cfg_hwmod,
2102 .slave = &omap54xx_usb_otg_ss_hwmod,
2103 .clk = "dpll_core_h13x2_ck",
2104 .user = OCP_USER_MPU | OCP_USER_SDMA,
2105 };
2106
2107 /* l4_wkup -> wd_timer2 */
2108 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2109 .master = &omap54xx_l4_wkup_hwmod,
2110 .slave = &omap54xx_wd_timer2_hwmod,
2111 .clk = "wkupaon_iclk_mux",
2112 .user = OCP_USER_MPU | OCP_USER_SDMA,
2113 };
2114
2115 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2116 &omap54xx_l3_main_1__dmm,
2117 &omap54xx_l3_main_3__l3_instr,
2118 &omap54xx_l3_main_2__l3_main_1,
2119 &omap54xx_l4_cfg__l3_main_1,
2120 &omap54xx_mpu__l3_main_1,
2121 &omap54xx_l3_main_1__l3_main_2,
2122 &omap54xx_l4_cfg__l3_main_2,
2123 &omap54xx_l3_main_1__l3_main_3,
2124 &omap54xx_l3_main_2__l3_main_3,
2125 &omap54xx_l4_cfg__l3_main_3,
2126 &omap54xx_l3_main_1__l4_abe,
2127 &omap54xx_mpu__l4_abe,
2128 &omap54xx_l3_main_1__l4_cfg,
2129 &omap54xx_l3_main_2__l4_per,
2130 &omap54xx_l3_main_1__l4_wkup,
2131 &omap54xx_mpu__mpu_private,
2132 &omap54xx_l4_wkup__counter_32k,
2133 &omap54xx_l4_cfg__dma_system,
2134 &omap54xx_l4_abe__dmic,
2135 &omap54xx_mpu__emif1,
2136 &omap54xx_mpu__emif2,
2137 &omap54xx_l4_wkup__gpio1,
2138 &omap54xx_l4_per__gpio2,
2139 &omap54xx_l4_per__gpio3,
2140 &omap54xx_l4_per__gpio4,
2141 &omap54xx_l4_per__gpio5,
2142 &omap54xx_l4_per__gpio6,
2143 &omap54xx_l4_per__gpio7,
2144 &omap54xx_l4_per__gpio8,
2145 &omap54xx_l4_per__i2c1,
2146 &omap54xx_l4_per__i2c2,
2147 &omap54xx_l4_per__i2c3,
2148 &omap54xx_l4_per__i2c4,
2149 &omap54xx_l4_per__i2c5,
2150 &omap54xx_l4_wkup__kbd,
2151 &omap54xx_l4_cfg__mailbox,
2152 &omap54xx_l4_abe__mcbsp1,
2153 &omap54xx_l4_abe__mcbsp2,
2154 &omap54xx_l4_abe__mcbsp3,
2155 &omap54xx_l4_abe__mcpdm,
2156 &omap54xx_l4_per__mcspi1,
2157 &omap54xx_l4_per__mcspi2,
2158 &omap54xx_l4_per__mcspi3,
2159 &omap54xx_l4_per__mcspi4,
2160 &omap54xx_l4_per__mmc1,
2161 &omap54xx_l4_per__mmc2,
2162 &omap54xx_l4_per__mmc3,
2163 &omap54xx_l4_per__mmc4,
2164 &omap54xx_l4_per__mmc5,
2165 &omap54xx_l4_cfg__mpu,
2166 &omap54xx_l4_wkup__timer1,
2167 &omap54xx_l4_per__timer2,
2168 &omap54xx_l4_per__timer3,
2169 &omap54xx_l4_per__timer4,
2170 &omap54xx_l4_abe__timer5,
2171 &omap54xx_l4_abe__timer6,
2172 &omap54xx_l4_abe__timer7,
2173 &omap54xx_l4_abe__timer8,
2174 &omap54xx_l4_per__timer9,
2175 &omap54xx_l4_per__timer10,
2176 &omap54xx_l4_per__timer11,
2177 &omap54xx_l4_per__uart1,
2178 &omap54xx_l4_per__uart2,
2179 &omap54xx_l4_per__uart3,
2180 &omap54xx_l4_per__uart4,
2181 &omap54xx_l4_per__uart5,
2182 &omap54xx_l4_per__uart6,
2183 &omap54xx_l4_cfg__usb_otg_ss,
2184 &omap54xx_l4_wkup__wd_timer2,
2185 NULL,
2186 };
2187
2188 int __init omap54xx_hwmod_init(void)
2189 {
2190 omap_hwmod_init();
2191 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2192 }
Linux with added FPC-III support