arch/arm/mach-ux500/board-mop500-pins.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/bug.h>
  10 #include <linux/string.h>
  11 #include <linux/pinctrl/machine.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13 #include <linux/platform_data/pinctrl-nomadik.h>
  14
  15 #include <asm/mach-types.h>
  16
  17 #include "board-mop500.h"
  18
  19 enum custom_pin_cfg_t {
  20         PINS_FOR_DEFAULT,
  21         PINS_FOR_U9500,
  22 };
  23
  24 static enum custom_pin_cfg_t pinsfor;
  25
  26 /* These simply sets bias for pins */
  27 #define BIAS(a,b) static unsigned long a[] = { b }
  28
  29 BIAS(pd, PIN_PULL_DOWN);
  30 BIAS(in_nopull, PIN_INPUT_NOPULL);
  31 BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
  32 BIAS(in_pu, PIN_INPUT_PULLUP);
  33 BIAS(in_pd, PIN_INPUT_PULLDOWN);
  34 BIAS(out_hi, PIN_OUTPUT_HIGH);
  35 BIAS(out_lo, PIN_OUTPUT_LOW);
  36 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
  37
  38 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
  39 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
  40 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
  41
  42 /* These also force them into GPIO mode */
  43 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
  44 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
  45 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  46 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  47 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
  48 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
  49 /* Sleep modes */
  50 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  51         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  52 BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
  53         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  54 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  55         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  56 BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
  57         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  58 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
  59         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
  60 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  61         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  62 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
  63         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  64 BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  65         PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  66 BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
  67         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  68 BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  69         PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  70 BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
  71         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  72 BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
  73         PIN_SLPM_PDIS_ENABLED);
  74 BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
  75         PIN_SLPM_PDIS_DISABLED);
  76 BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
  77         PIN_SLPM_PDIS_DISABLED);
  78
  79 /* We use these to define hog settings that are always done on boot */
  80 #define DB8500_MUX_HOG(group,func) \
  81         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
  82 #define DB8500_PIN_HOG(pin,conf) \
  83         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
  84
  85 /* These are default states associated with device and changed runtime */
  86 #define DB8500_MUX(group,func,dev) \
  87         PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
  88 #define DB8500_PIN(pin,conf,dev) \
  89         PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
  90 #define DB8500_PIN_IDLE(pin, conf, dev) \
  91         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
  92                             pin, conf)
  93 #define DB8500_PIN_SLEEP(pin, conf, dev) \
  94         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
  95                             pin, conf)
  96 #define DB8500_MUX_STATE(group, func, dev, state) \
  97         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
  98 #define DB8500_PIN_STATE(pin, conf, dev, state) \
  99         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 100
 101 #define AB8500_MUX_HOG(group, func) \
 102         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
 103 #define AB8500_PIN_HOG(pin, conf) \
 104         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
 105
 106 #define AB8500_MUX_STATE(group, func, dev, state) \
 107         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
 108 #define AB8500_PIN_STATE(pin, conf, dev, state) \
 109         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
 110
 111 #define AB8505_MUX_HOG(group, func) \
 112         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
 113 #define AB8505_PIN_HOG(pin, conf) \
 114         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
 115
 116 #define AB8505_MUX_STATE(group, func, dev, state) \
 117         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
 118 #define AB8505_PIN_STATE(pin, conf, dev, state) \
 119         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
 120
 121 static struct pinctrl_map __initdata ab8500_pinmap[] = {
 122         /* Sysclkreq2 */
 123         AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
 124         AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
 125         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 126         AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
 127         AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
 128
 129         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 130         AB8500_MUX_HOG("gpio2_a_1", "gpio"),
 131         AB8500_PIN_HOG("GPIO2_T9", in_pd),
 132
 133         /* Sysclkreq4 */
 134         AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 135         AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 136         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 137         AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 138         AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 139
 140         /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
 141         AB8500_MUX_HOG("gpio4_a_1", "gpio"),
 142         AB8500_PIN_HOG("GPIO4_W2", in_pd),
 143
 144         /*
 145          * pins 6,7,8 and 9 are muxed in YCBCR0123
 146          * configured in INPUT PULL UP
 147          */
 148         AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
 149         AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
 150         AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
 151         AB8500_PIN_HOG("GPIO8_W18", in_nopull),
 152         AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
 153
 154         /*
 155          * pins 10,11,12 and 13 are muxed in GPIO
 156          * configured in INPUT PULL DOWN
 157          */
 158         AB8500_MUX_HOG("gpio10_d_1", "gpio"),
 159         AB8500_PIN_HOG("GPIO10_U17", in_pd),
 160
 161         AB8500_MUX_HOG("gpio11_d_1", "gpio"),
 162         AB8500_PIN_HOG("GPIO11_AA18", in_pd),
 163
 164         AB8500_MUX_HOG("gpio12_d_1", "gpio"),
 165         AB8500_PIN_HOG("GPIO12_U16", in_pd),
 166
 167         AB8500_MUX_HOG("gpio13_d_1", "gpio"),
 168         AB8500_PIN_HOG("GPIO13_W17", in_pd),
 169
 170         /*
 171          * pins 14,15 are muxed in PWM1 and PWM2
 172          * configured in INPUT PULL DOWN
 173          */
 174         AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
 175         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 176
 177         AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
 178         AB8500_PIN_HOG("GPIO15_B17", in_pd),
 179
 180         /*
 181          * pins 16 is muxed in GPIO
 182          * configured in INPUT PULL DOWN
 183          */
 184         AB8500_MUX_HOG("gpio16_a_1", "gpio"),
 185         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 186
 187         /*
 188          * pins 17,18,19 and 20 are muxed in AUDIO interface 1
 189          * configured in INPUT PULL DOWN
 190          */
 191         AB8500_MUX_HOG("adi1_d_1", "adi1"),
 192         AB8500_PIN_HOG("GPIO17_P5", in_pd),
 193         AB8500_PIN_HOG("GPIO18_R5", in_pd),
 194         AB8500_PIN_HOG("GPIO19_U5", in_pd),
 195         AB8500_PIN_HOG("GPIO20_T5", in_pd),
 196
 197         /*
 198          * pins 21,22 and 23 are muxed in USB UICC
 199          * configured in INPUT PULL DOWN
 200          */
 201         AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
 202         AB8500_PIN_HOG("GPIO21_H19", in_pd),
 203         AB8500_PIN_HOG("GPIO22_G20", in_pd),
 204         AB8500_PIN_HOG("GPIO23_G19", in_pd),
 205
 206         /*
 207          * pins 24,25 are muxed in GPIO
 208          * configured in INPUT PULL DOWN
 209          */
 210         AB8500_MUX_HOG("gpio24_a_1", "gpio"),
 211         AB8500_PIN_HOG("GPIO24_T14", in_pd),
 212
 213         AB8500_MUX_HOG("gpio25_a_1", "gpio"),
 214         AB8500_PIN_HOG("GPIO25_R16", in_pd),
 215
 216         /*
 217          * pins 26 is muxed in GPIO
 218          * configured in OUTPUT LOW
 219          */
 220         AB8500_MUX_HOG("gpio26_d_1", "gpio"),
 221         AB8500_PIN_HOG("GPIO26_M16", out_lo),
 222
 223         /*
 224          * pins 27,28 are muxed in DMIC12
 225          * configured in INPUT PULL DOWN
 226          */
 227         AB8500_MUX_HOG("dmic12_d_1", "dmic"),
 228         AB8500_PIN_HOG("GPIO27_J6", in_pd),
 229         AB8500_PIN_HOG("GPIO28_K6", in_pd),
 230
 231         /*
 232          * pins 29,30 are muxed in DMIC34
 233          * configured in INPUT PULL DOWN
 234          */
 235         AB8500_MUX_HOG("dmic34_d_1", "dmic"),
 236         AB8500_PIN_HOG("GPIO29_G6", in_pd),
 237         AB8500_PIN_HOG("GPIO30_H6", in_pd),
 238
 239         /*
 240          * pins 31,32 are muxed in DMIC56
 241          * configured in INPUT PULL DOWN
 242          */
 243         AB8500_MUX_HOG("dmic56_d_1", "dmic"),
 244         AB8500_PIN_HOG("GPIO31_F5", in_pd),
 245         AB8500_PIN_HOG("GPIO32_G5", in_pd),
 246
 247         /*
 248          * pins 34 is muxed in EXTCPENA
 249          * configured INPUT PULL DOWN
 250          */
 251         AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
 252         AB8500_PIN_HOG("GPIO34_R17", in_pd),
 253
 254         /*
 255          * pins 35 is muxed in GPIO
 256          * configured in OUTPUT LOW
 257          */
 258         AB8500_MUX_HOG("gpio35_d_1", "gpio"),
 259         AB8500_PIN_HOG("GPIO35_W15", in_pd),
 260
 261         /*
 262          * pins 36,37,38 and 39 are muxed in GPIO
 263          * configured in INPUT PULL DOWN
 264          */
 265         AB8500_MUX_HOG("gpio36_a_1", "gpio"),
 266         AB8500_PIN_HOG("GPIO36_A17", in_pd),
 267
 268         AB8500_MUX_HOG("gpio37_a_1", "gpio"),
 269         AB8500_PIN_HOG("GPIO37_E15", in_pd),
 270
 271         AB8500_MUX_HOG("gpio38_a_1", "gpio"),
 272         AB8500_PIN_HOG("GPIO38_C17", in_pd),
 273
 274         AB8500_MUX_HOG("gpio39_a_1", "gpio"),
 275         AB8500_PIN_HOG("GPIO39_E16", in_pd),
 276
 277         /*
 278          * pins 40 and 41 are muxed in MODCSLSDA
 279          * configured INPUT PULL DOWN
 280          */
 281         AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
 282         AB8500_PIN_HOG("GPIO40_T19", in_pd),
 283         AB8500_PIN_HOG("GPIO41_U19", in_pd),
 284
 285         /*
 286          * pins 42 is muxed in GPIO
 287          * configured INPUT PULL DOWN
 288          */
 289         AB8500_MUX_HOG("gpio42_a_1", "gpio"),
 290         AB8500_PIN_HOG("GPIO42_U2", in_pd),
 291 };
 292
 293 static struct pinctrl_map __initdata ab8505_pinmap[] = {
 294         /* Sysclkreq2 */
 295         AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 296         AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 297         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 298         AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 299         AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 300
 301         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 302         AB8505_MUX_HOG("gpio2_a_1", "gpio"),
 303         AB8505_PIN_HOG("GPIO2_R5", in_pd),
 304
 305         /* Sysclkreq4 */
 306         AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
 307         AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
 308         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 309         AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
 310         AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
 311
 312         AB8505_MUX_HOG("gpio10_d_1", "gpio"),
 313         AB8505_PIN_HOG("GPIO10_B16", in_pd),
 314
 315         AB8505_MUX_HOG("gpio11_d_1", "gpio"),
 316         AB8505_PIN_HOG("GPIO11_B17", in_pd),
 317
 318         AB8505_MUX_HOG("gpio13_d_1", "gpio"),
 319         AB8505_PIN_HOG("GPIO13_D17", in_nopull),
 320
 321         AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
 322         AB8505_PIN_HOG("GPIO14_C16", in_pd),
 323
 324         AB8505_MUX_HOG("adi2_d_1", "adi2"),
 325         AB8505_PIN_HOG("GPIO17_P2", in_pd),
 326         AB8505_PIN_HOG("GPIO18_N3", in_pd),
 327         AB8505_PIN_HOG("GPIO19_T1", in_pd),
 328         AB8505_PIN_HOG("GPIO20_P3", in_pd),
 329
 330         AB8505_MUX_HOG("gpio34_a_1", "gpio"),
 331         AB8505_PIN_HOG("GPIO34_H14", in_pd),
 332
 333         AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
 334         AB8505_PIN_HOG("GPIO40_J15", in_pd),
 335         AB8505_PIN_HOG("GPIO41_J14", in_pd),
 336
 337         AB8505_MUX_HOG("gpio50_d_1", "gpio"),
 338         AB8505_PIN_HOG("GPIO50_L4", in_nopull),
 339
 340         AB8505_MUX_HOG("resethw_d_1", "resethw"),
 341         AB8505_PIN_HOG("GPIO52_D16", in_pd),
 342
 343         AB8505_MUX_HOG("service_d_1", "service"),
 344         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 345 };
 346
 347 /* Pin control settings */
 348 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 349         /*
 350          * uMSP0, mux in 4 pins, regular placement of RX/TX
 351          * explicitly set the pins to no pull
 352          */
 353         DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
 354         DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
 355         DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
 356         DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
 357         DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
 358         DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
 359         /* MSP2 for HDMI, pull down TXD, TCK, TFS  */
 360         DB8500_MUX_HOG("msp2_a_1", "msp2"),
 361         DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
 362         DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
 363         DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
 364         DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
 365         /*
 366          * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
 367          * pull-up
 368          * TODO: is this really correct? Snowball doesn't have a LCD.
 369          */
 370         DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
 371         DB8500_PIN_HOG("GPIO68_E1", in_pu),
 372         DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
 373         /*
 374          * STMPE1601/tc35893 keypad IRQ GPIO 218
 375          * TODO: set for snowball and HREF really??
 376          */
 377         DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
 378         /*
 379          * UART0, we do not mux in u0 here.
 380          * uart-0 pins gpio configuration should be kept intact to prevent
 381          * a glitch in tx line when the tty dev is opened. Later these pins
 382          * are configured by uart driver
 383          */
 384         DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
 385         DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
 386         DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
 387         DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
 388         /*
 389          * Mux in UART2 on altfunction C and set pull-ups.
 390          * TODO: is this used on U8500 variants and Snowball really?
 391          * The setting on GPIO31 conflicts with magnetometer use on hrefv60
 392          */
 393         /* default state for UART2 */
 394         DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
 395         DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
 396         DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
 397         /* Sleep state for UART2 */
 398         DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
 399         DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
 400         /*
 401          * The following pin sets were known as "runtime pins" before being
 402          * converted to the pinctrl model. Here we model them as "default"
 403          * states.
 404          */
 405         /* Mux in UART0 after initialization */
 406         DB8500_MUX("u0_a_1", "u0", "uart0"),
 407         DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
 408         DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
 409         DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
 410         DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
 411         /* Sleep state for UART0 */
 412         DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
 413         DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
 414         DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
 415         DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
 416         /* Mux in UART1 after initialization */
 417         DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
 418         DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
 419         DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
 420         /* Sleep state for UART1 */
 421         DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
 422         DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
 423         /* MSP1 for ALSA codec */
 424         DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
 425         DB8500_MUX_HOG("msp1_a_1", "msp1"),
 426         DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
 427         DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
 428         DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
 429         DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
 430         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
 431         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
 432         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
 433         /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
 434         DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
 435         DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
 436         /* LCD VSI1 sleep state */
 437         DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
 438         /* Mux in i2c0 block, default state */
 439         DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
 440         /* i2c0 sleep state */
 441         DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
 442         DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
 443         /* Mux in i2c1 block, default state  */
 444         DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
 445         /* i2c1 sleep state */
 446         DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
 447         DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
 448         /* Mux in i2c2 block, default state  */
 449         DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
 450         /* i2c2 sleep state */
 451         DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
 452         DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
 453         /* Mux in i2c3 block, default state  */
 454         DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
 455         /* i2c3 sleep state */
 456         DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
 457         DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
 458         /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
 459         DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
 460         DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
 461         DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
 462         DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
 463         DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
 464         DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
 465         DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
 466         DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
 467         DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
 468         DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
 469         DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
 470         /* SDI0 sleep state */
 471         DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
 472         DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
 473         DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
 474         DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
 475         DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
 476         DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
 477         DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
 478         DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
 479         DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
 480         DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
 481
 482         /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
 483         DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
 484         DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
 485         DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
 486         DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
 487         DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
 488         DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
 489         DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
 490         DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
 491         /* SDI1 sleep state */
 492         DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
 493         DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
 494         DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
 495         DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
 496         DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
 497         DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
 498         DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
 499
 500         /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
 501         DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
 502         DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
 503         DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
 504         DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
 505         DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
 506         DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
 507         DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
 508         DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
 509         DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
 510         DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
 511         DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
 512         DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
 513         /* SDI2 sleep state */
 514         DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
 515         DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
 516         DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
 517         DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
 518         DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
 519         DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
 520         DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
 521         DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
 522         DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
 523         DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
 524         DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
 525
 526         /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
 527         DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
 528         DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
 529         DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
 530         DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
 531         DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
 532         DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
 533         DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
 534         DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
 535         DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
 536         DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
 537         DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
 538         DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
 539         /*SDI4 sleep state */
 540         DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
 541         DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
 542         DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
 543         DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
 544         DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
 545         DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
 546         DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
 547         DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
 548         DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
 549         DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
 550         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 551
 552         /* Mux in USB pins, drive STP high */
 553         /* USB default state */
 554         DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
 555         DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
 556         /* USB sleep state */
 557         DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
 558         DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
 559         DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
 560         DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
 561         DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
 562         DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
 563         DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
 564         DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
 565         DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
 566         DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
 567         DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
 568         DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
 569
 570         /* Mux in SPI2 pins on the "other C1" altfunction */
 571         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
 572         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
 573         DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
 574         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
 575         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
 576         /* SPI2 idle state */
 577         DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
 578         DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
 579         DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 580         /* SPI2 sleep state */
 581         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
 582         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
 583         DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
 584         DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
 585
 586         /* ske default state */
 587         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 588         DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
 589         DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
 590         DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
 591         DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
 592         DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
 593         DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
 594         DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
 595         DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
 596         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 597         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 598         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 599         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 600         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 601         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 602         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 603         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 604         /* ske sleep state */
 605         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 606         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 607         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 608         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 609         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 610         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 611         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 612         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 613         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 614         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 615         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 616         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 617         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 618         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 619         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 620         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 621
 622         /* STM APE pins states */
 623         DB8500_MUX_STATE("stmape_c_1", "stmape",
 624                 "stm", "ape_mipi34"),
 625         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 626                 "stm", "ape_mipi34"), /* clk */
 627         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 628                 "stm", "ape_mipi34"), /* dat3 */
 629         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 630                 "stm", "ape_mipi34"), /* dat2 */
 631         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 632                 "stm", "ape_mipi34"), /* dat1 */
 633         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 634                 "stm", "ape_mipi34"), /* dat0 */
 635
 636         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 637                 "stm", "ape_mipi34_sleep"), /* clk */
 638         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 639                 "stm", "ape_mipi34_sleep"), /* dat3 */
 640         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 641                 "stm", "ape_mipi34_sleep"), /* dat2 */
 642         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 643                 "stm", "ape_mipi34_sleep"), /* dat1 */
 644         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 645                 "stm", "ape_mipi34_sleep"), /* dat0 */
 646
 647         DB8500_MUX_STATE("stmape_oc1_1", "stmape",
 648                 "stm", "ape_microsd"),
 649         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 650                 "stm", "ape_microsd"), /* clk */
 651         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 652                 "stm", "ape_microsd"), /* dat0 */
 653         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 654                 "stm", "ape_microsd"), /* dat1 */
 655         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 656                 "stm", "ape_microsd"), /* dat2 */
 657         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 658                 "stm", "ape_microsd"), /* dat3 */
 659
 660         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 661                 "stm", "ape_microsd_sleep"), /* clk */
 662         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 663                 "stm", "ape_microsd_sleep"), /* dat0 */
 664         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 665                 "stm", "ape_microsd_sleep"), /* dat1 */
 666         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 667                 "stm", "ape_microsd_sleep"), /* dat2 */
 668         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 669                 "stm", "ape_microsd_sleep"), /* dat3 */
 670
 671         /*  STM Modem pins states */
 672         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 673                 "stm", "mod_mipi34"),
 674         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 675                 "stm", "mod_mipi34"),
 676         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 677                 "stm", "mod_mipi34"),
 678         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 679                 "stm", "mod_mipi34"), /* clk */
 680         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 681                 "stm", "mod_mipi34"), /* dat3 */
 682         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 683                 "stm", "mod_mipi34"), /* dat2 */
 684         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 685                 "stm", "mod_mipi34"), /* dat1 */
 686         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 687                 "stm", "mod_mipi34"), /* dat0 */
 688         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 689                 "stm", "mod_mipi34"), /* uartmod rx */
 690         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 691                 "stm", "mod_mipi34"), /* uartmod tx */
 692
 693         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 694                 "stm", "mod_mipi34_sleep"), /* clk */
 695         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 696                 "stm", "mod_mipi34_sleep"), /* dat3 */
 697         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 698                 "stm", "mod_mipi34_sleep"), /* dat2 */
 699         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 700                 "stm", "mod_mipi34_sleep"), /* dat1 */
 701         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 702                 "stm", "mod_mipi34_sleep"), /* dat0 */
 703         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 704                 "stm", "mod_mipi34_sleep"), /* uartmod rx */
 705         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 706                 "stm", "mod_mipi34_sleep"), /* uartmod tx */
 707
 708         DB8500_MUX_STATE("stmmod_b_1", "stmmod",
 709                 "stm", "mod_microsd"),
 710         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 711                 "stm", "mod_microsd"),
 712         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 713                 "stm", "mod_microsd"),
 714         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 715                 "stm", "mod_microsd"), /* clk */
 716         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 717                 "stm", "mod_microsd"), /* dat0 */
 718         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 719                 "stm", "mod_microsd"), /* dat1 */
 720         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 721                 "stm", "mod_microsd"), /* dat2 */
 722         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 723                 "stm", "mod_microsd"), /* dat3 */
 724         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 725                 "stm", "mod_microsd"), /* uartmod rx */
 726         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 727                 "stm", "mod_microsd"), /* uartmod tx */
 728
 729         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 730                 "stm", "mod_microsd_sleep"), /* clk */
 731         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 732                 "stm", "mod_microsd_sleep"), /* dat0 */
 733         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 734                 "stm", "mod_microsd_sleep"), /* dat1 */
 735         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 736                 "stm", "mod_microsd_sleep"), /* dat2 */
 737         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 738                 "stm", "mod_microsd_sleep"), /* dat3 */
 739         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 740                 "stm", "mod_microsd_sleep"), /* uartmod rx */
 741         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 742                 "stm", "mod_microsd_sleep"), /* uartmod tx */
 743
 744         /*  STM dual Modem/APE pins state */
 745         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 746                 "stm", "mod_mipi34_ape_mipi60"),
 747         DB8500_MUX_STATE("stmape_c_2", "stmape",
 748                 "stm", "mod_mipi34_ape_mipi60"),
 749         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 750                 "stm", "mod_mipi34_ape_mipi60"),
 751         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 752                 "stm", "mod_mipi34_ape_mipi60"),
 753         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 754                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 755         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 756                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 757         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 758                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 759         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 760                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 761         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 762                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 763         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 764                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
 765         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 766                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
 767         DB8500_PIN_STATE("GPIO155_C19", in_nopull,
 768                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 769         DB8500_PIN_STATE("GPIO156_C17", in_nopull,
 770                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 771         DB8500_PIN_STATE("GPIO157_A18", in_nopull,
 772                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 773         DB8500_PIN_STATE("GPIO158_C18", in_nopull,
 774                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 775         DB8500_PIN_STATE("GPIO159_B19", in_nopull,
 776                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 777
 778         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 779                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 780         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 781                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 782         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 783                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 784         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 785                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 786         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 787                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 788         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 789                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
 790         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 791                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
 792         DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
 793                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 794         DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
 795                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 796         DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
 797                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 798         DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
 799                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 800         DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
 801                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 802 };
 803
 804 /*
 805  * These are specifically for the MOP500 and HREFP (pre-v60) version of the
 806  * board, which utilized a TC35892 GPIO expander instead of using a lot of
 807  * on-chip pins as the HREFv60 and later does.
 808  */
 809 static struct pinctrl_map __initdata mop500_pinmap[] = {
 810         /* Mux in SSP0, pull down RXD pin */
 811         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
 812         DB8500_PIN_HOG("GPIO145_C13", pd),
 813         /*
 814          * XENON Flashgun on image processor GPIO (controlled from image
 815          * processor firmware), mux in these image processor GPIO lines 0
 816          * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
 817          * the pins.
 818          */
 819         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 820         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 821         DB8500_PIN_HOG("GPIO6_AF6", in_pu),
 822         DB8500_PIN_HOG("GPIO7_AG5", in_pu),
 823         /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
 824         DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
 825         /* Mux in UART1 and set the pull-ups */
 826         DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
 827         DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
 828         DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
 829         /*
 830          * Runtime stuff: make it possible to mux in the SKE keypad
 831          * and bias the pins
 832          */
 833         /* ske default state */
 834         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 835         DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
 836         DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
 837         DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
 838         DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
 839         DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
 840         DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
 841         DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
 842         DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
 843         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 844         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 845         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 846         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 847         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 848         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 849         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 850         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 851         /* ske sleep state */
 852         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 853         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 854         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 855         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 856         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 857         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 858         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 859         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 860         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 861         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 862         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 863         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 864         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 865         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 866         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 867         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 868
 869         /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
 870         DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
 871         DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
 872 };
 873
 874 /*
 875  * The HREFv60 series of platforms is using available pins on the DB8500
 876  * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
 877  * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
 878  */
 879 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
 880         /* Drive WLAN_ENA low */
 881         DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
 882         /*
 883          * XENON Flashgun on image processor GPIO (controlled from image
 884          * processor firmware), mux in these image processor GPIO lines 0
 885          * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
 886          * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
 887          * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
 888          */
 889         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 890         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 891         DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
 892         DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
 893         DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
 894         DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
 895         DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
 896         /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
 897         DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
 898         DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
 899         /*
 900          * Display Interface 1 uses GPIO 65 for RST (reset).
 901          * Display Interface 2 uses GPIO 66 for RST (reset).
 902          * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
 903          */
 904         DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
 905         DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
 906         /*
 907          * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
 908          * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
 909          * reset signals low.
 910          */
 911         DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
 912         DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
 913         DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
 914         /*
 915          * Drive D19-D23 for the ETM PTM trace interface low,
 916          * (presumably pins are unconnected therefore grounded here,
 917          * the "other alt C1" setting enables these pins)
 918          */
 919         DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
 920         DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
 921         DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
 922         DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
 923         DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
 924         /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
 925         DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
 926         DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
 927         /* NFC ENA and RESET to low, pulldown IRQ line */
 928         DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
 929         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
 930         DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
 931         /*
 932          * SKE keyboard partly on alt A and partly on "Other alt C1"
 933          * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
 934          * rows of 6 keys, then pull up force sensing interrup and
 935          * drive reset and force sensing WU low.
 936          */
 937         DB8500_MUX_HOG("kp_a_1", "kp"),
 938         DB8500_MUX_HOG("kp_oc1_1", "kp"),
 939         DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
 940         DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
 941         DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
 942         DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
 943         DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
 944         DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
 945         DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
 946         DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
 947         DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
 948         DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
 949         DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
 950         /* DiPro Sensor interrupt */
 951         DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
 952         /* Audio Amplifier HF enable */
 953         DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
 954         /* GBF interface, pull low to reset state */
 955         DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
 956         /* MSP : HDTV INTERFACE GPIO line */
 957         DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
 958         /* Accelerometer interrupt lines */
 959         DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
 960         DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
 961         /* SD card detect GPIO pin */
 962         DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
 963         /*
 964          * Runtime stuff
 965          * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
 966          * etc.
 967          */
 968         DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 969         DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
 970         DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 971 };
 972
 973 static struct pinctrl_map __initdata u9500_pinmap[] = {
 974         /* Mux in UART1 (just RX/TX) and set the pull-ups */
 975         DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
 976         DB8500_PIN_HOG("GPIO4_AH6", in_pu),
 977         DB8500_PIN_HOG("GPIO5_AG6", out_hi),
 978         /* WLAN_IRQ line */
 979         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
 980         /* HSI */
 981         DB8500_MUX_HOG("hsir_a_1", "hsi"),
 982         DB8500_MUX_HOG("hsit_a_2", "hsi"),
 983         DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
 984         DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
 985         DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
 986         DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
 987         DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
 988         DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
 989         DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
 990         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 991 };
 992
 993 static struct pinctrl_map __initdata u8500_pinmap[] = {
 994         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
 995         DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
 996 };
 997
 998 static struct pinctrl_map __initdata snowball_pinmap[] = {
 999         /* Mux in SSP0 connected to AB8500, pull down RXD pin */
1000         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
1001         DB8500_PIN_HOG("GPIO145_C13", pd),
1002         /* Always drive the MC0 DAT31DIR line high on these boards */
1003         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
1004         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
1005         DB8500_MUX_HOG("sm_b_1", "sm"),
1006         /* User LED */
1007         DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
1008         /* Drive RSTn_LAN high */
1009         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
1010         /*  Accelerometer/Magnetometer */
1011         DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
1012         DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
1013         DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
1014         /* WLAN/GBF */
1015         DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
1016         DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
1017         DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
1018         DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
1019 };
1020
1021 /*
1022  * passing "pinsfor=" in kernel cmdline allows for custom
1023  * configuration of GPIOs on u8500 derived boards.
1024  */
1025 static int __init early_pinsfor(char *p)
1026 {
1027         pinsfor = PINS_FOR_DEFAULT;
1028
1029         if (strcmp(p, "u9500-21") == 0)
1030                 pinsfor = PINS_FOR_U9500;
1031
1032         return 0;
1033 }
1034 early_param("pinsfor", early_pinsfor);
1035
1036 int pins_for_u9500(void)
1037 {
1038         if (pinsfor == PINS_FOR_U9500)
1039                 return 1;
1040
1041         return 0;
1042 }
1043
1044 static void __init mop500_href_family_pinmaps_init(void)
1045 {
1046         switch (pinsfor) {
1047         case PINS_FOR_U9500:
1048                 pinctrl_register_mappings(u9500_pinmap,
1049                                           ARRAY_SIZE(u9500_pinmap));
1050                 break;
1051         case PINS_FOR_DEFAULT:
1052                 pinctrl_register_mappings(u8500_pinmap,
1053                                           ARRAY_SIZE(u8500_pinmap));
1054         default:
1055                 break;
1056         }
1057 }
1058
1059 void __init mop500_pinmaps_init(void)
1060 {
1061         pinctrl_register_mappings(mop500_family_pinmap,
1062                                   ARRAY_SIZE(mop500_family_pinmap));
1063         pinctrl_register_mappings(mop500_pinmap,
1064                                   ARRAY_SIZE(mop500_pinmap));
1065         mop500_href_family_pinmaps_init();
1066         if (machine_is_u8520())
1067                 pinctrl_register_mappings(ab8505_pinmap,
1068                                           ARRAY_SIZE(ab8505_pinmap));
1069         else
1070                 pinctrl_register_mappings(ab8500_pinmap,
1071                                           ARRAY_SIZE(ab8500_pinmap));
1072 }
1073
1074 void __init snowball_pinmaps_init(void)
1075 {
1076         pinctrl_register_mappings(mop500_family_pinmap,
1077                                   ARRAY_SIZE(mop500_family_pinmap));
1078         pinctrl_register_mappings(snowball_pinmap,
1079                                   ARRAY_SIZE(snowball_pinmap));
1080         pinctrl_register_mappings(u8500_pinmap,
1081                                   ARRAY_SIZE(u8500_pinmap));
1082         pinctrl_register_mappings(ab8500_pinmap,
1083                                   ARRAY_SIZE(ab8500_pinmap));
1084 }
1085
1086 void __init hrefv60_pinmaps_init(void)
1087 {
1088         pinctrl_register_mappings(mop500_family_pinmap,
1089                                   ARRAY_SIZE(mop500_family_pinmap));
1090         pinctrl_register_mappings(hrefv60_pinmap,
1091                                   ARRAY_SIZE(hrefv60_pinmap));
1092         mop500_href_family_pinmaps_init();
1093         pinctrl_register_mappings(ab8500_pinmap,
1094                                   ARRAY_SIZE(ab8500_pinmap));
1095 }