x86/xen: resume timer irqs early
[linux/fpc-iii.git] / arch / arm / mm / mmu.c
blobb7c987dbb6041aed84a02ed5ac10c2c902bbf6df
1 /*
2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
17 #include <linux/fs.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
21 #include <asm/cp15.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/setup.h>
26 #include <asm/smp_plat.h>
27 #include <asm/tlb.h>
28 #include <asm/highmem.h>
29 #include <asm/system_info.h>
30 #include <asm/traps.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/pci.h>
36 #include "mm.h"
37 #include "tcm.h"
40 * empty_zero_page is a special page that is used for
41 * zero-initialized data and COW.
43 struct page *empty_zero_page;
44 EXPORT_SYMBOL(empty_zero_page);
47 * The pmd table for the upper-most set of pages.
49 pmd_t *top_pmd;
51 #define CPOLICY_UNCACHED 0
52 #define CPOLICY_BUFFERED 1
53 #define CPOLICY_WRITETHROUGH 2
54 #define CPOLICY_WRITEBACK 3
55 #define CPOLICY_WRITEALLOC 4
57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
58 static unsigned int ecc_mask __initdata = 0;
59 pgprot_t pgprot_user;
60 pgprot_t pgprot_kernel;
61 pgprot_t pgprot_hyp_device;
62 pgprot_t pgprot_s2;
63 pgprot_t pgprot_s2_device;
65 EXPORT_SYMBOL(pgprot_user);
66 EXPORT_SYMBOL(pgprot_kernel);
68 struct cachepolicy {
69 const char policy[16];
70 unsigned int cr_mask;
71 pmdval_t pmd;
72 pteval_t pte;
73 pteval_t pte_s2;
76 #ifdef CONFIG_ARM_LPAE
77 #define s2_policy(policy) policy
78 #else
79 #define s2_policy(policy) 0
80 #endif
82 static struct cachepolicy cache_policies[] __initdata = {
84 .policy = "uncached",
85 .cr_mask = CR_W|CR_C,
86 .pmd = PMD_SECT_UNCACHED,
87 .pte = L_PTE_MT_UNCACHED,
88 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
89 }, {
90 .policy = "buffered",
91 .cr_mask = CR_C,
92 .pmd = PMD_SECT_BUFFERED,
93 .pte = L_PTE_MT_BUFFERABLE,
94 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
95 }, {
96 .policy = "writethrough",
97 .cr_mask = 0,
98 .pmd = PMD_SECT_WT,
99 .pte = L_PTE_MT_WRITETHROUGH,
100 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
101 }, {
102 .policy = "writeback",
103 .cr_mask = 0,
104 .pmd = PMD_SECT_WB,
105 .pte = L_PTE_MT_WRITEBACK,
106 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
107 }, {
108 .policy = "writealloc",
109 .cr_mask = 0,
110 .pmd = PMD_SECT_WBWA,
111 .pte = L_PTE_MT_WRITEALLOC,
112 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
116 #ifdef CONFIG_CPU_CP15
118 * These are useful for identifying cache coherency
119 * problems by allowing the cache or the cache and
120 * writebuffer to be turned off. (Note: the write
121 * buffer should not be on and the cache off).
123 static int __init early_cachepolicy(char *p)
125 int i;
127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
128 int len = strlen(cache_policies[i].policy);
130 if (memcmp(p, cache_policies[i].policy, len) == 0) {
131 cachepolicy = i;
132 cr_alignment &= ~cache_policies[i].cr_mask;
133 cr_no_alignment &= ~cache_policies[i].cr_mask;
134 break;
137 if (i == ARRAY_SIZE(cache_policies))
138 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
140 * This restriction is partly to do with the way we boot; it is
141 * unpredictable to have memory mapped using two different sets of
142 * memory attributes (shared, type, and cache attribs). We can not
143 * change these attributes once the initial assembly has setup the
144 * page tables.
146 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
147 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
148 cachepolicy = CPOLICY_WRITEBACK;
150 flush_cache_all();
151 set_cr(cr_alignment);
152 return 0;
154 early_param("cachepolicy", early_cachepolicy);
156 static int __init early_nocache(char *__unused)
158 char *p = "buffered";
159 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
160 early_cachepolicy(p);
161 return 0;
163 early_param("nocache", early_nocache);
165 static int __init early_nowrite(char *__unused)
167 char *p = "uncached";
168 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
169 early_cachepolicy(p);
170 return 0;
172 early_param("nowb", early_nowrite);
174 #ifndef CONFIG_ARM_LPAE
175 static int __init early_ecc(char *p)
177 if (memcmp(p, "on", 2) == 0)
178 ecc_mask = PMD_PROTECTION;
179 else if (memcmp(p, "off", 3) == 0)
180 ecc_mask = 0;
181 return 0;
183 early_param("ecc", early_ecc);
184 #endif
186 static int __init noalign_setup(char *__unused)
188 cr_alignment &= ~CR_A;
189 cr_no_alignment &= ~CR_A;
190 set_cr(cr_alignment);
191 return 1;
193 __setup("noalign", noalign_setup);
195 #ifndef CONFIG_SMP
196 void adjust_cr(unsigned long mask, unsigned long set)
198 unsigned long flags;
200 mask &= ~CR_A;
202 set &= mask;
204 local_irq_save(flags);
206 cr_no_alignment = (cr_no_alignment & ~mask) | set;
207 cr_alignment = (cr_alignment & ~mask) | set;
209 set_cr((get_cr() & ~mask) | set);
211 local_irq_restore(flags);
213 #endif
215 #else /* ifdef CONFIG_CPU_CP15 */
217 static int __init early_cachepolicy(char *p)
219 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
221 early_param("cachepolicy", early_cachepolicy);
223 static int __init noalign_setup(char *__unused)
225 pr_warning("noalign kernel parameter not supported without cp15\n");
227 __setup("noalign", noalign_setup);
229 #endif /* ifdef CONFIG_CPU_CP15 / else */
231 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
232 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
233 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
235 static struct mem_type mem_types[] = {
236 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
237 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
238 L_PTE_SHARED,
239 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
240 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
241 L_PTE_SHARED,
242 .prot_l1 = PMD_TYPE_TABLE,
243 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
244 .domain = DOMAIN_IO,
246 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
248 .prot_l1 = PMD_TYPE_TABLE,
249 .prot_sect = PROT_SECT_DEVICE,
250 .domain = DOMAIN_IO,
252 [MT_DEVICE_CACHED] = { /* ioremap_cached */
253 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
254 .prot_l1 = PMD_TYPE_TABLE,
255 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
256 .domain = DOMAIN_IO,
258 [MT_DEVICE_WC] = { /* ioremap_wc */
259 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PROT_SECT_DEVICE,
262 .domain = DOMAIN_IO,
264 [MT_UNCACHED] = {
265 .prot_pte = PROT_PTE_DEVICE,
266 .prot_l1 = PMD_TYPE_TABLE,
267 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
268 .domain = DOMAIN_IO,
270 [MT_CACHECLEAN] = {
271 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
272 .domain = DOMAIN_KERNEL,
274 #ifndef CONFIG_ARM_LPAE
275 [MT_MINICLEAN] = {
276 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
277 .domain = DOMAIN_KERNEL,
279 #endif
280 [MT_LOW_VECTORS] = {
281 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
282 L_PTE_RDONLY,
283 .prot_l1 = PMD_TYPE_TABLE,
284 .domain = DOMAIN_USER,
286 [MT_HIGH_VECTORS] = {
287 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
288 L_PTE_USER | L_PTE_RDONLY,
289 .prot_l1 = PMD_TYPE_TABLE,
290 .domain = DOMAIN_USER,
292 [MT_MEMORY] = {
293 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
294 .prot_l1 = PMD_TYPE_TABLE,
295 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
296 .domain = DOMAIN_KERNEL,
298 [MT_ROM] = {
299 .prot_sect = PMD_TYPE_SECT,
300 .domain = DOMAIN_KERNEL,
302 [MT_MEMORY_NONCACHED] = {
303 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
304 L_PTE_MT_BUFFERABLE,
305 .prot_l1 = PMD_TYPE_TABLE,
306 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_KERNEL,
309 [MT_MEMORY_DTCM] = {
310 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
311 L_PTE_XN,
312 .prot_l1 = PMD_TYPE_TABLE,
313 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
314 .domain = DOMAIN_KERNEL,
316 [MT_MEMORY_ITCM] = {
317 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
318 .prot_l1 = PMD_TYPE_TABLE,
319 .domain = DOMAIN_KERNEL,
321 [MT_MEMORY_SO] = {
322 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
323 L_PTE_MT_UNCACHED | L_PTE_XN,
324 .prot_l1 = PMD_TYPE_TABLE,
325 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
326 PMD_SECT_UNCACHED | PMD_SECT_XN,
327 .domain = DOMAIN_KERNEL,
329 [MT_MEMORY_DMA_READY] = {
330 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
331 .prot_l1 = PMD_TYPE_TABLE,
332 .domain = DOMAIN_KERNEL,
336 const struct mem_type *get_mem_type(unsigned int type)
338 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
340 EXPORT_SYMBOL(get_mem_type);
343 * Adjust the PMD section entries according to the CPU in use.
345 static void __init build_mem_type_table(void)
347 struct cachepolicy *cp;
348 unsigned int cr = get_cr();
349 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
350 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
351 int cpu_arch = cpu_architecture();
352 int i;
354 if (cpu_arch < CPU_ARCH_ARMv6) {
355 #if defined(CONFIG_CPU_DCACHE_DISABLE)
356 if (cachepolicy > CPOLICY_BUFFERED)
357 cachepolicy = CPOLICY_BUFFERED;
358 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
359 if (cachepolicy > CPOLICY_WRITETHROUGH)
360 cachepolicy = CPOLICY_WRITETHROUGH;
361 #endif
363 if (cpu_arch < CPU_ARCH_ARMv5) {
364 if (cachepolicy >= CPOLICY_WRITEALLOC)
365 cachepolicy = CPOLICY_WRITEBACK;
366 ecc_mask = 0;
368 if (is_smp())
369 cachepolicy = CPOLICY_WRITEALLOC;
372 * Strip out features not present on earlier architectures.
373 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
374 * without extended page tables don't have the 'Shared' bit.
376 if (cpu_arch < CPU_ARCH_ARMv5)
377 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
378 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
379 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
380 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
381 mem_types[i].prot_sect &= ~PMD_SECT_S;
384 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
385 * "update-able on write" bit on ARM610). However, Xscale and
386 * Xscale3 require this bit to be cleared.
388 if (cpu_is_xscale() || cpu_is_xsc3()) {
389 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
390 mem_types[i].prot_sect &= ~PMD_BIT4;
391 mem_types[i].prot_l1 &= ~PMD_BIT4;
393 } else if (cpu_arch < CPU_ARCH_ARMv6) {
394 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
395 if (mem_types[i].prot_l1)
396 mem_types[i].prot_l1 |= PMD_BIT4;
397 if (mem_types[i].prot_sect)
398 mem_types[i].prot_sect |= PMD_BIT4;
403 * Mark the device areas according to the CPU/architecture.
405 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
406 if (!cpu_is_xsc3()) {
408 * Mark device regions on ARMv6+ as execute-never
409 * to prevent speculative instruction fetches.
411 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
412 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
413 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
414 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
416 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
418 * For ARMv7 with TEX remapping,
419 * - shared device is SXCB=1100
420 * - nonshared device is SXCB=0100
421 * - write combine device mem is SXCB=0001
422 * (Uncached Normal memory)
424 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
425 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
426 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
427 } else if (cpu_is_xsc3()) {
429 * For Xscale3,
430 * - shared device is TEXCB=00101
431 * - nonshared device is TEXCB=01000
432 * - write combine device mem is TEXCB=00100
433 * (Inner/Outer Uncacheable in xsc3 parlance)
435 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
436 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
437 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
438 } else {
440 * For ARMv6 and ARMv7 without TEX remapping,
441 * - shared device is TEXCB=00001
442 * - nonshared device is TEXCB=01000
443 * - write combine device mem is TEXCB=00100
444 * (Uncached Normal in ARMv6 parlance).
446 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
447 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
448 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
450 } else {
452 * On others, write combining is "Uncached/Buffered"
454 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
458 * Now deal with the memory-type mappings
460 cp = &cache_policies[cachepolicy];
461 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
462 s2_pgprot = cp->pte_s2;
463 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
464 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
467 * We don't use domains on ARMv6 (since this causes problems with
468 * v6/v7 kernels), so we must use a separate memory type for user
469 * r/o, kernel r/w to map the vectors page.
471 #ifndef CONFIG_ARM_LPAE
472 if (cpu_arch == CPU_ARCH_ARMv6)
473 vecs_pgprot |= L_PTE_MT_VECTORS;
474 #endif
477 * ARMv6 and above have extended page tables.
479 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
480 #ifndef CONFIG_ARM_LPAE
482 * Mark cache clean areas and XIP ROM read only
483 * from SVC mode and no access from userspace.
485 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
486 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
487 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
488 #endif
490 if (is_smp()) {
492 * Mark memory with the "shared" attribute
493 * for SMP systems
495 user_pgprot |= L_PTE_SHARED;
496 kern_pgprot |= L_PTE_SHARED;
497 vecs_pgprot |= L_PTE_SHARED;
498 s2_pgprot |= L_PTE_SHARED;
499 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
500 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
501 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
502 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
503 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
504 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
505 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
506 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
507 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
512 * Non-cacheable Normal - intended for memory areas that must
513 * not cause dirty cache line writebacks when used
515 if (cpu_arch >= CPU_ARCH_ARMv6) {
516 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
517 /* Non-cacheable Normal is XCB = 001 */
518 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
519 PMD_SECT_BUFFERED;
520 } else {
521 /* For both ARMv6 and non-TEX-remapping ARMv7 */
522 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
523 PMD_SECT_TEX(1);
525 } else {
526 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
529 #ifdef CONFIG_ARM_LPAE
531 * Do not generate access flag faults for the kernel mappings.
533 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
534 mem_types[i].prot_pte |= PTE_EXT_AF;
535 if (mem_types[i].prot_sect)
536 mem_types[i].prot_sect |= PMD_SECT_AF;
538 kern_pgprot |= PTE_EXT_AF;
539 vecs_pgprot |= PTE_EXT_AF;
540 #endif
542 for (i = 0; i < 16; i++) {
543 pteval_t v = pgprot_val(protection_map[i]);
544 protection_map[i] = __pgprot(v | user_pgprot);
547 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
548 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
550 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
551 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
552 L_PTE_DIRTY | kern_pgprot);
553 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
554 pgprot_s2_device = __pgprot(s2_device_pgprot);
555 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
557 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
558 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
559 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
560 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
561 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
562 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
563 mem_types[MT_ROM].prot_sect |= cp->pmd;
565 switch (cp->pmd) {
566 case PMD_SECT_WT:
567 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
568 break;
569 case PMD_SECT_WB:
570 case PMD_SECT_WBWA:
571 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
572 break;
574 printk("Memory policy: ECC %sabled, Data cache %s\n",
575 ecc_mask ? "en" : "dis", cp->policy);
577 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
578 struct mem_type *t = &mem_types[i];
579 if (t->prot_l1)
580 t->prot_l1 |= PMD_DOMAIN(t->domain);
581 if (t->prot_sect)
582 t->prot_sect |= PMD_DOMAIN(t->domain);
586 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
587 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
588 unsigned long size, pgprot_t vma_prot)
590 if (!pfn_valid(pfn))
591 return pgprot_noncached(vma_prot);
592 else if (file->f_flags & O_SYNC)
593 return pgprot_writecombine(vma_prot);
594 return vma_prot;
596 EXPORT_SYMBOL(phys_mem_access_prot);
597 #endif
599 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
601 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
603 void *ptr = __va(memblock_alloc(sz, align));
604 memset(ptr, 0, sz);
605 return ptr;
608 static void __init *early_alloc(unsigned long sz)
610 return early_alloc_aligned(sz, sz);
613 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
615 if (pmd_none(*pmd)) {
616 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
617 __pmd_populate(pmd, __pa(pte), prot);
619 BUG_ON(pmd_bad(*pmd));
620 return pte_offset_kernel(pmd, addr);
623 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
624 unsigned long end, unsigned long pfn,
625 const struct mem_type *type)
627 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
628 do {
629 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
630 pfn++;
631 } while (pte++, addr += PAGE_SIZE, addr != end);
634 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
635 unsigned long end, phys_addr_t phys,
636 const struct mem_type *type)
638 pmd_t *p = pmd;
640 #ifndef CONFIG_ARM_LPAE
642 * In classic MMU format, puds and pmds are folded in to
643 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
644 * group of L1 entries making up one logical pointer to
645 * an L2 table (2MB), where as PMDs refer to the individual
646 * L1 entries (1MB). Hence increment to get the correct
647 * offset for odd 1MB sections.
648 * (See arch/arm/include/asm/pgtable-2level.h)
650 if (addr & SECTION_SIZE)
651 pmd++;
652 #endif
653 do {
654 *pmd = __pmd(phys | type->prot_sect);
655 phys += SECTION_SIZE;
656 } while (pmd++, addr += SECTION_SIZE, addr != end);
658 flush_pmd_entry(p);
661 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
662 unsigned long end, phys_addr_t phys,
663 const struct mem_type *type)
665 pmd_t *pmd = pmd_offset(pud, addr);
666 unsigned long next;
668 do {
670 * With LPAE, we must loop over to map
671 * all the pmds for the given range.
673 next = pmd_addr_end(addr, end);
676 * Try a section mapping - addr, next and phys must all be
677 * aligned to a section boundary.
679 if (type->prot_sect &&
680 ((addr | next | phys) & ~SECTION_MASK) == 0) {
681 __map_init_section(pmd, addr, next, phys, type);
682 } else {
683 alloc_init_pte(pmd, addr, next,
684 __phys_to_pfn(phys), type);
687 phys += next - addr;
689 } while (pmd++, addr = next, addr != end);
692 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
693 unsigned long end, phys_addr_t phys,
694 const struct mem_type *type)
696 pud_t *pud = pud_offset(pgd, addr);
697 unsigned long next;
699 do {
700 next = pud_addr_end(addr, end);
701 alloc_init_pmd(pud, addr, next, phys, type);
702 phys += next - addr;
703 } while (pud++, addr = next, addr != end);
706 #ifndef CONFIG_ARM_LPAE
707 static void __init create_36bit_mapping(struct map_desc *md,
708 const struct mem_type *type)
710 unsigned long addr, length, end;
711 phys_addr_t phys;
712 pgd_t *pgd;
714 addr = md->virtual;
715 phys = __pfn_to_phys(md->pfn);
716 length = PAGE_ALIGN(md->length);
718 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
719 printk(KERN_ERR "MM: CPU does not support supersection "
720 "mapping for 0x%08llx at 0x%08lx\n",
721 (long long)__pfn_to_phys((u64)md->pfn), addr);
722 return;
725 /* N.B. ARMv6 supersections are only defined to work with domain 0.
726 * Since domain assignments can in fact be arbitrary, the
727 * 'domain == 0' check below is required to insure that ARMv6
728 * supersections are only allocated for domain 0 regardless
729 * of the actual domain assignments in use.
731 if (type->domain) {
732 printk(KERN_ERR "MM: invalid domain in supersection "
733 "mapping for 0x%08llx at 0x%08lx\n",
734 (long long)__pfn_to_phys((u64)md->pfn), addr);
735 return;
738 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
739 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
740 " at 0x%08lx invalid alignment\n",
741 (long long)__pfn_to_phys((u64)md->pfn), addr);
742 return;
746 * Shift bits [35:32] of address into bits [23:20] of PMD
747 * (See ARMv6 spec).
749 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
751 pgd = pgd_offset_k(addr);
752 end = addr + length;
753 do {
754 pud_t *pud = pud_offset(pgd, addr);
755 pmd_t *pmd = pmd_offset(pud, addr);
756 int i;
758 for (i = 0; i < 16; i++)
759 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
761 addr += SUPERSECTION_SIZE;
762 phys += SUPERSECTION_SIZE;
763 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
764 } while (addr != end);
766 #endif /* !CONFIG_ARM_LPAE */
769 * Create the page directory entries and any necessary
770 * page tables for the mapping specified by `md'. We
771 * are able to cope here with varying sizes and address
772 * offsets, and we take full advantage of sections and
773 * supersections.
775 static void __init create_mapping(struct map_desc *md)
777 unsigned long addr, length, end;
778 phys_addr_t phys;
779 const struct mem_type *type;
780 pgd_t *pgd;
782 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
783 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
784 " at 0x%08lx in user region\n",
785 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
786 return;
789 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
790 md->virtual >= PAGE_OFFSET &&
791 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
792 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
793 " at 0x%08lx out of vmalloc space\n",
794 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
797 type = &mem_types[md->type];
799 #ifndef CONFIG_ARM_LPAE
801 * Catch 36-bit addresses
803 if (md->pfn >= 0x100000) {
804 create_36bit_mapping(md, type);
805 return;
807 #endif
809 addr = md->virtual & PAGE_MASK;
810 phys = __pfn_to_phys(md->pfn);
811 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
813 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
814 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
815 "be mapped using pages, ignoring.\n",
816 (long long)__pfn_to_phys(md->pfn), addr);
817 return;
820 pgd = pgd_offset_k(addr);
821 end = addr + length;
822 do {
823 unsigned long next = pgd_addr_end(addr, end);
825 alloc_init_pud(pgd, addr, next, phys, type);
827 phys += next - addr;
828 addr = next;
829 } while (pgd++, addr != end);
833 * Create the architecture specific mappings
835 void __init iotable_init(struct map_desc *io_desc, int nr)
837 struct map_desc *md;
838 struct vm_struct *vm;
839 struct static_vm *svm;
841 if (!nr)
842 return;
844 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
846 for (md = io_desc; nr; md++, nr--) {
847 create_mapping(md);
849 vm = &svm->vm;
850 vm->addr = (void *)(md->virtual & PAGE_MASK);
851 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
852 vm->phys_addr = __pfn_to_phys(md->pfn);
853 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
854 vm->flags |= VM_ARM_MTYPE(md->type);
855 vm->caller = iotable_init;
856 add_static_vm_early(svm++);
860 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
861 void *caller)
863 struct vm_struct *vm;
864 struct static_vm *svm;
866 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
868 vm = &svm->vm;
869 vm->addr = (void *)addr;
870 vm->size = size;
871 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
872 vm->caller = caller;
873 add_static_vm_early(svm);
876 #ifndef CONFIG_ARM_LPAE
879 * The Linux PMD is made of two consecutive section entries covering 2MB
880 * (see definition in include/asm/pgtable-2level.h). However a call to
881 * create_mapping() may optimize static mappings by using individual
882 * 1MB section mappings. This leaves the actual PMD potentially half
883 * initialized if the top or bottom section entry isn't used, leaving it
884 * open to problems if a subsequent ioremap() or vmalloc() tries to use
885 * the virtual space left free by that unused section entry.
887 * Let's avoid the issue by inserting dummy vm entries covering the unused
888 * PMD halves once the static mappings are in place.
891 static void __init pmd_empty_section_gap(unsigned long addr)
893 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
896 static void __init fill_pmd_gaps(void)
898 struct static_vm *svm;
899 struct vm_struct *vm;
900 unsigned long addr, next = 0;
901 pmd_t *pmd;
903 list_for_each_entry(svm, &static_vmlist, list) {
904 vm = &svm->vm;
905 addr = (unsigned long)vm->addr;
906 if (addr < next)
907 continue;
910 * Check if this vm starts on an odd section boundary.
911 * If so and the first section entry for this PMD is free
912 * then we block the corresponding virtual address.
914 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
915 pmd = pmd_off_k(addr);
916 if (pmd_none(*pmd))
917 pmd_empty_section_gap(addr & PMD_MASK);
921 * Then check if this vm ends on an odd section boundary.
922 * If so and the second section entry for this PMD is empty
923 * then we block the corresponding virtual address.
925 addr += vm->size;
926 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
927 pmd = pmd_off_k(addr) + 1;
928 if (pmd_none(*pmd))
929 pmd_empty_section_gap(addr);
932 /* no need to look at any vm entry until we hit the next PMD */
933 next = (addr + PMD_SIZE - 1) & PMD_MASK;
937 #else
938 #define fill_pmd_gaps() do { } while (0)
939 #endif
941 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
942 static void __init pci_reserve_io(void)
944 struct static_vm *svm;
946 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
947 if (svm)
948 return;
950 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
952 #else
953 #define pci_reserve_io() do { } while (0)
954 #endif
956 #ifdef CONFIG_DEBUG_LL
957 void __init debug_ll_io_init(void)
959 struct map_desc map;
961 debug_ll_addr(&map.pfn, &map.virtual);
962 if (!map.pfn || !map.virtual)
963 return;
964 map.pfn = __phys_to_pfn(map.pfn);
965 map.virtual &= PAGE_MASK;
966 map.length = PAGE_SIZE;
967 map.type = MT_DEVICE;
968 iotable_init(&map, 1);
970 #endif
972 static void * __initdata vmalloc_min =
973 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
976 * vmalloc=size forces the vmalloc area to be exactly 'size'
977 * bytes. This can be used to increase (or decrease) the vmalloc
978 * area - the default is 240m.
980 static int __init early_vmalloc(char *arg)
982 unsigned long vmalloc_reserve = memparse(arg, NULL);
984 if (vmalloc_reserve < SZ_16M) {
985 vmalloc_reserve = SZ_16M;
986 printk(KERN_WARNING
987 "vmalloc area too small, limiting to %luMB\n",
988 vmalloc_reserve >> 20);
991 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
992 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
993 printk(KERN_WARNING
994 "vmalloc area is too big, limiting to %luMB\n",
995 vmalloc_reserve >> 20);
998 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
999 return 0;
1001 early_param("vmalloc", early_vmalloc);
1003 phys_addr_t arm_lowmem_limit __initdata = 0;
1005 void __init sanity_check_meminfo(void)
1007 phys_addr_t memblock_limit = 0;
1008 int i, j, highmem = 0;
1009 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1011 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1012 struct membank *bank = &meminfo.bank[j];
1013 phys_addr_t size_limit;
1015 *bank = meminfo.bank[i];
1016 size_limit = bank->size;
1018 if (bank->start >= vmalloc_limit)
1019 highmem = 1;
1020 else
1021 size_limit = vmalloc_limit - bank->start;
1023 bank->highmem = highmem;
1025 #ifdef CONFIG_HIGHMEM
1027 * Split those memory banks which are partially overlapping
1028 * the vmalloc area greatly simplifying things later.
1030 if (!highmem && bank->size > size_limit) {
1031 if (meminfo.nr_banks >= NR_BANKS) {
1032 printk(KERN_CRIT "NR_BANKS too low, "
1033 "ignoring high memory\n");
1034 } else {
1035 memmove(bank + 1, bank,
1036 (meminfo.nr_banks - i) * sizeof(*bank));
1037 meminfo.nr_banks++;
1038 i++;
1039 bank[1].size -= size_limit;
1040 bank[1].start = vmalloc_limit;
1041 bank[1].highmem = highmem = 1;
1042 j++;
1044 bank->size = size_limit;
1046 #else
1048 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1050 if (highmem) {
1051 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1052 "(!CONFIG_HIGHMEM).\n",
1053 (unsigned long long)bank->start,
1054 (unsigned long long)bank->start + bank->size - 1);
1055 continue;
1059 * Check whether this memory bank would partially overlap
1060 * the vmalloc area.
1062 if (bank->size > size_limit) {
1063 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1064 "to -%.8llx (vmalloc region overlap).\n",
1065 (unsigned long long)bank->start,
1066 (unsigned long long)bank->start + bank->size - 1,
1067 (unsigned long long)bank->start + size_limit - 1);
1068 bank->size = size_limit;
1070 #endif
1071 if (!bank->highmem) {
1072 phys_addr_t bank_end = bank->start + bank->size;
1074 if (bank_end > arm_lowmem_limit)
1075 arm_lowmem_limit = bank_end;
1078 * Find the first non-section-aligned page, and point
1079 * memblock_limit at it. This relies on rounding the
1080 * limit down to be section-aligned, which happens at
1081 * the end of this function.
1083 * With this algorithm, the start or end of almost any
1084 * bank can be non-section-aligned. The only exception
1085 * is that the start of the bank 0 must be section-
1086 * aligned, since otherwise memory would need to be
1087 * allocated when mapping the start of bank 0, which
1088 * occurs before any free memory is mapped.
1090 if (!memblock_limit) {
1091 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1092 memblock_limit = bank->start;
1093 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1094 memblock_limit = bank_end;
1097 j++;
1099 #ifdef CONFIG_HIGHMEM
1100 if (highmem) {
1101 const char *reason = NULL;
1103 if (cache_is_vipt_aliasing()) {
1105 * Interactions between kmap and other mappings
1106 * make highmem support with aliasing VIPT caches
1107 * rather difficult.
1109 reason = "with VIPT aliasing cache";
1111 if (reason) {
1112 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1113 reason);
1114 while (j > 0 && meminfo.bank[j - 1].highmem)
1115 j--;
1118 #endif
1119 meminfo.nr_banks = j;
1120 high_memory = __va(arm_lowmem_limit - 1) + 1;
1123 * Round the memblock limit down to a section size. This
1124 * helps to ensure that we will allocate memory from the
1125 * last full section, which should be mapped.
1127 if (memblock_limit)
1128 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1129 if (!memblock_limit)
1130 memblock_limit = arm_lowmem_limit;
1132 memblock_set_current_limit(memblock_limit);
1135 static inline void prepare_page_table(void)
1137 unsigned long addr;
1138 phys_addr_t end;
1141 * Clear out all the mappings below the kernel image.
1143 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1144 pmd_clear(pmd_off_k(addr));
1146 #ifdef CONFIG_XIP_KERNEL
1147 /* The XIP kernel is mapped in the module area -- skip over it */
1148 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1149 #endif
1150 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1151 pmd_clear(pmd_off_k(addr));
1154 * Find the end of the first block of lowmem.
1156 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1157 if (end >= arm_lowmem_limit)
1158 end = arm_lowmem_limit;
1161 * Clear out all the kernel space mappings, except for the first
1162 * memory bank, up to the vmalloc region.
1164 for (addr = __phys_to_virt(end);
1165 addr < VMALLOC_START; addr += PMD_SIZE)
1166 pmd_clear(pmd_off_k(addr));
1169 #ifdef CONFIG_ARM_LPAE
1170 /* the first page is reserved for pgd */
1171 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1172 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1173 #else
1174 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1175 #endif
1178 * Reserve the special regions of memory
1180 void __init arm_mm_memblock_reserve(void)
1183 * Reserve the page tables. These are already in use,
1184 * and can only be in node 0.
1186 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1188 #ifdef CONFIG_SA1111
1190 * Because of the SA1111 DMA bug, we want to preserve our
1191 * precious DMA-able memory...
1193 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1194 #endif
1198 * Set up the device mappings. Since we clear out the page tables for all
1199 * mappings above VMALLOC_START, we will remove any debug device mappings.
1200 * This means you have to be careful how you debug this function, or any
1201 * called function. This means you can't use any function or debugging
1202 * method which may touch any device, otherwise the kernel _will_ crash.
1204 static void __init devicemaps_init(const struct machine_desc *mdesc)
1206 struct map_desc map;
1207 unsigned long addr;
1208 void *vectors;
1211 * Allocate the vector page early.
1213 vectors = early_alloc(PAGE_SIZE * 2);
1215 early_trap_init(vectors);
1217 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1218 pmd_clear(pmd_off_k(addr));
1221 * Map the kernel if it is XIP.
1222 * It is always first in the modulearea.
1224 #ifdef CONFIG_XIP_KERNEL
1225 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1226 map.virtual = MODULES_VADDR;
1227 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1228 map.type = MT_ROM;
1229 create_mapping(&map);
1230 #endif
1233 * Map the cache flushing regions.
1235 #ifdef FLUSH_BASE
1236 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1237 map.virtual = FLUSH_BASE;
1238 map.length = SZ_1M;
1239 map.type = MT_CACHECLEAN;
1240 create_mapping(&map);
1241 #endif
1242 #ifdef FLUSH_BASE_MINICACHE
1243 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1244 map.virtual = FLUSH_BASE_MINICACHE;
1245 map.length = SZ_1M;
1246 map.type = MT_MINICLEAN;
1247 create_mapping(&map);
1248 #endif
1251 * Create a mapping for the machine vectors at the high-vectors
1252 * location (0xffff0000). If we aren't using high-vectors, also
1253 * create a mapping at the low-vectors virtual address.
1255 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1256 map.virtual = 0xffff0000;
1257 map.length = PAGE_SIZE;
1258 #ifdef CONFIG_KUSER_HELPERS
1259 map.type = MT_HIGH_VECTORS;
1260 #else
1261 map.type = MT_LOW_VECTORS;
1262 #endif
1263 create_mapping(&map);
1265 if (!vectors_high()) {
1266 map.virtual = 0;
1267 map.length = PAGE_SIZE * 2;
1268 map.type = MT_LOW_VECTORS;
1269 create_mapping(&map);
1272 /* Now create a kernel read-only mapping */
1273 map.pfn += 1;
1274 map.virtual = 0xffff0000 + PAGE_SIZE;
1275 map.length = PAGE_SIZE;
1276 map.type = MT_LOW_VECTORS;
1277 create_mapping(&map);
1280 * Ask the machine support to map in the statically mapped devices.
1282 if (mdesc->map_io)
1283 mdesc->map_io();
1284 else
1285 debug_ll_io_init();
1286 fill_pmd_gaps();
1288 /* Reserve fixed i/o space in VMALLOC region */
1289 pci_reserve_io();
1292 * Finally flush the caches and tlb to ensure that we're in a
1293 * consistent state wrt the writebuffer. This also ensures that
1294 * any write-allocated cache lines in the vector page are written
1295 * back. After this point, we can start to touch devices again.
1297 local_flush_tlb_all();
1298 flush_cache_all();
1301 static void __init kmap_init(void)
1303 #ifdef CONFIG_HIGHMEM
1304 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1305 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1306 #endif
1309 static void __init map_lowmem(void)
1311 struct memblock_region *reg;
1313 /* Map all the lowmem memory banks. */
1314 for_each_memblock(memory, reg) {
1315 phys_addr_t start = reg->base;
1316 phys_addr_t end = start + reg->size;
1317 struct map_desc map;
1319 if (end > arm_lowmem_limit)
1320 end = arm_lowmem_limit;
1321 if (start >= end)
1322 break;
1324 map.pfn = __phys_to_pfn(start);
1325 map.virtual = __phys_to_virt(start);
1326 map.length = end - start;
1327 map.type = MT_MEMORY;
1329 create_mapping(&map);
1334 * paging_init() sets up the page tables, initialises the zone memory
1335 * maps, and sets up the zero page, bad page and bad page tables.
1337 void __init paging_init(const struct machine_desc *mdesc)
1339 void *zero_page;
1341 build_mem_type_table();
1342 prepare_page_table();
1343 map_lowmem();
1344 dma_contiguous_remap();
1345 devicemaps_init(mdesc);
1346 kmap_init();
1347 tcm_init();
1349 top_pmd = pmd_off_k(0xffff0000);
1351 /* allocate the zero page. */
1352 zero_page = early_alloc(PAGE_SIZE);
1354 bootmem_init();
1356 empty_zero_page = virt_to_page(zero_page);
1357 __flush_dcache_page(NULL, empty_zero_page);